KR100629678B1 - Method for fabricating Chip scale package - Google Patents

Method for fabricating Chip scale package Download PDF

Info

Publication number
KR100629678B1
KR100629678B1 KR1019990036263A KR19990036263A KR100629678B1 KR 100629678 B1 KR100629678 B1 KR 100629678B1 KR 1019990036263 A KR1019990036263 A KR 1019990036263A KR 19990036263 A KR19990036263 A KR 19990036263A KR 100629678 B1 KR100629678 B1 KR 100629678B1
Authority
KR
South Korea
Prior art keywords
lead
semiconductor chip
solder
chip
scale package
Prior art date
Application number
KR1019990036263A
Other languages
Korean (ko)
Other versions
KR20010019706A (en
Inventor
최일흥
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1019990036263A priority Critical patent/KR100629678B1/en
Publication of KR20010019706A publication Critical patent/KR20010019706A/en
Application granted granted Critical
Publication of KR100629678B1 publication Critical patent/KR100629678B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 센터 본딩 패드를 갖는 반도체 칩이 어탯치된 리드 온 칩(Lead On Chip,이하 LOC라 칭한다) 방식 리드의 인너 리드에 솔더 범프를 형성하고, 솔더 범프-리드-반도체 칩을 몰딩한 후 솔더 범프를 외부로 노출시킨 후, 노출된 솔더 범프에 외부 입출력 단자 역할을 하는 솔더볼을 어탯치하여 반도체 칩과 리드는 LOC 방식으로 제작하고, LOC 방식 리드와 외부 기기의 신호 입출력은 볼 그리드 어레이(Ball Grid Array,이하 BGA라 칭한다) 방식이 되도록 하여 반도체 칩의 크기에 더욱 근접되도록 제작된 칩 스케일 패키지 및 그 제조 방법에 관한 것이다.According to the present invention, a solder bump is formed on an inner lead of a lead on chip (LOC) type lead to which a semiconductor chip having a center bonding pad is attached, and a solder bump-lead-semiconductor chip is molded. After exposing the solder bumps to outside, attach the solder balls that serve as external I / O terminals to the exposed solder bumps, and the semiconductor chip and leads are manufactured in the LOC method. The present invention relates to a chip scale package manufactured in such a manner as to be a ball grid array (hereinafter referred to as BGA), and closer to the size of a semiconductor chip, and a method of manufacturing the same.

칩 스케일 패키지, 솔더 범프Chip Scale Package, Solder Bump

Description

칩 스케일 패키지 제조 방법{Method for fabricating Chip scale package}Method for fabricating chip scale package

도 1은 본 발명에 의한 칩 스케일 패키지에 적용되도록 솔더 범프가 형성된 리드의 일실시예를 도시한 평면도.1 is a plan view showing an embodiment of a lead in which the solder bump is formed to be applied to the chip scale package according to the present invention.

도 2는 도 1에 도시된 리드의 측면도.2 is a side view of the lid shown in FIG. 1;

도 3a 내지 도 3f는 본 발명에 의한 칩 스케일 패키지를 제작하는 순서를 도시한 공정도.3A to 3F are process diagrams showing a procedure for manufacturing a chip scale package according to the present invention.

도 4는 본 발명에 의한 칩 스케일 패키지의 구성 및 구조를 설명하기 위한 칩 스케일 패키지의 부분 단면 사시도.4 is a partial cross-sectional perspective view of the chip scale package for explaining the configuration and structure of the chip scale package according to the present invention.

본 발명은 칩 스케일 패키지(Chip Scale Pacakge,이하 CSP라 칭한다) 및 그 제조 방법에 관한 것으로, 더욱 상세하게는 센터 본딩 패드를 갖는 반도체 칩이 어탯치된 리드 온 칩(Lead On Chip,이하 LOC라 칭한다) 방식 리드의 인너 리드에 솔더 범프를 형성하고, 솔더 범프-리드-반도체 칩을 몰딩한 후, 솔더 범프를 외부로 노출시키고 노출된 솔더 범프에 외부 입출력 단자 역할을 하는 솔더볼을 어탯치하 여 반도체 칩과 리드는 LOC 방식으로 제작하고, LOC 방식 리드와 외부 기기의 신호 입출력은 볼 그리드 어레이(Ball Grid Array,이하 BGA라 칭한다) 방식이 되도록 하여 반도체 칩의 크기에 더욱 근접되도록 제작된 칩 스케일 패키지 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip scale package (hereinafter referred to as CSP) and a manufacturing method thereof, and more particularly to a lead on chip (LOC) attached to a semiconductor chip having a center bonding pad. Form solder bumps on the inner leads of the method leads, mold the solder bump-lead-semiconductor chips, expose the solder bumps to the outside, and attach the solder balls that serve as external input / output terminals to the exposed solder bumps Chip and package are manufactured by LOC method and the signal input / output of LOC method lead and external device is made by Ball Grid Array (hereinafter referred to as BGA) method. And a method for producing the same.

최근들어 반도체 제품의 제작 기술이 크게 발달되면서 반도체 제품의 성능은 크게 향상되면서 크기는 더욱 콤팩트화되어 가고 있는 추세이다.Recently, as the manufacturing technology of semiconductor products is greatly developed, the performance of semiconductor products is greatly improved, and the size thereof is becoming more compact.

이와 같이 반도체 제품의 성능은 향상시키면서도 크기는 더욱 콤팩트화 시키기 위해서는 반도체 칩의 성능 개선 뿐만 아니라 반도체 칩을 외부 기기와 전기적으로 연결시키는 패키지 기술의 개발이 요구된다.As such, in order to improve the performance of semiconductor products and to make them more compact, development of a package technology for electrically connecting the semiconductor chip with an external device is required as well as improving the performance of the semiconductor chip.

특히 최근에는 반도체 칩의 전체 크기의 약 120%에 근접하는 칩 스케일 패키지(Chip Scale Package) 기술이 크게 개발되면서 반도체 제품의 전체 크기가 획기적으로 감소된 바 있다.In particular, the recent development of the chip scale package technology, which approximates about 120% of the total size of the semiconductor chip, has greatly reduced the overall size of the semiconductor product.

이와 같은 칩 스케일 패키지를 가능케 하는 패키지 방식으로는 반도체 칩의 상면에 리드의 인너 리드가 위치되도록 하는 리드 온 칩 방식과, 일측면에 회로 패턴이 형성되고 타측면에 회로 패턴과 연결된 솔더볼 패드가 형성된 인쇄회로기판에 반도체 칩을 어탯치하고 반도체 칩의 본딩 패드와 회로 패턴을 와이어 본딩 또는 빔리드 본딩한 후, 솔더볼 패드에 솔더볼을 어탯치한 볼 그리드 어레이 방법으로 크게 구분할 수 있다.As a package method for enabling such a chip scale package, a lead-on chip method in which an inner lead of a lead is positioned on an upper surface of a semiconductor chip, and a circuit pattern formed on one side and solder ball pads connected to the circuit pattern on the other side are formed. After attaching a semiconductor chip to a printed circuit board, wire bonding or beam lead bonding the bonding pad and the circuit pattern of the semiconductor chip, the solder ball pad can be classified into a ball grid array method.

그러나, 리드 온 칩 방식으로 제작된 패키지는 여전히 외부 기기와 전기적으로 연결되는 아웃터 리드가 필수적인 바, 이로 인하여 패키지 전체 크기가 증가됨 은 물론 아웃터 리드를 가공하기 위하여 트리밍/포밍 등의 공정이 필수적으로 필요한 문제점이 있다.However, the package manufactured by the lead-on-chip method still requires an outer lead electrically connected to an external device, which increases the overall size of the package and necessitates a trimming / forming process to process the outer lead. There is a problem.

또한, 볼 그리드 어레이 방식 패키지는 리드 온 칩 방식 패키지와 전혀 다른 구조를 갖기 때문에 패키지 제조 설비 전체를 교체하여야 함으로 인하여 종래 패키지 제조 설비를 사용할 수 없게 되어 설비 비용 증가 되는 문제점이 있다.In addition, since the ball grid array type package has a completely different structure from the lead-on-chip type package, the entire package manufacturing facility needs to be replaced, thereby making it impossible to use the conventional package manufacturing facility, thereby increasing the facility cost.

따라서, 본 발명은 이와 같은 종래 문제점들을 감안한 것으로써, 본 발명 칩 스케일 패키지 및 그 제조 방법의 목적은 종래 패키지 제조 설비를 그대로 이용하면서도 종래 반도체 패키지를 제작하기 위하여 필수적이었던 트리밍/포밍 공정이 필요없는 즉, 외부 기기와 입출력을 위한 별도의 아웃터 리드가 필요 없어 반도체 패키지의 크기를 더욱 감소시키면서도 반도체 패키지의 취급이 용이하고, 신뢰성을 크게 향상시킴에 있다.Accordingly, the present invention has been made in view of such conventional problems, and the object of the chip scale package and its manufacturing method of the present invention is to eliminate the trimming / forming process, which is essential for manufacturing a conventional semiconductor package while still using the conventional package manufacturing equipment. That is, since there is no need for a separate outer lead for external devices and input / output, the semiconductor package can be easily handled and the reliability can be greatly improved while further reducing the size of the semiconductor package.

본 발명의 다른 목적은 후술될 본 발명의 상세한 설명에 의하여 보다 명확해질 것이다.Other objects of the present invention will become more apparent from the following detailed description of the invention.

이와 같은 본 발명의 목적을 달성하기 위한 본 발명에 의한 칩 스케일 패키지는 센터에 본딩 패드가 배열된 반도체 칩과, 반도체 칩의 상면에 안착된 복수개의 리드들과, 리드와 본딩 패드를 전기적으로 연결하는 와이어와, 리드들의 상면에 형성된 솔더 범프와, 솔더 범프가 노출되도록 반도체 칩과 리드를 감싸는 몰드 수지와, 솔더 범프에 어탯치된 솔더 볼을 포함한다.In order to achieve the object of the present invention, a chip scale package according to the present invention includes a semiconductor chip in which a bonding pad is arranged in a center, a plurality of leads seated on an upper surface of the semiconductor chip, and an electrical connection between the lead and the bonding pad. And a solder bump formed on the upper surfaces of the leads, a mold resin surrounding the semiconductor chip and the leads to expose the solder bumps, and solder balls attached to the solder bumps.

또한, 본 발명의 목적을 달성하기 위한 본 발명에 의한 칩 스케일 패키지 제조 방법은 센터에 본딩 패드가 배열된 반도체 칩의 상면에 솔더 범프가 형성된 복수개의 리드를 비도전성 테이프를 매개로 접착하고, 반도체 칩과 리드를 도전성 와이어로 와이어 본딩한 후, 솔더 범프, 리드, 반도체 칩을 몰드 수지로 몰딩한 후, 솔더 범프가 함몰되도록 몰딩된 몰드 수지를 그라인딩(grinding)하여 솔더 범프가 외부로 노출되도록 하고, 솔더 범프에 솔더볼을 어탯치한다.In addition, the chip scale package manufacturing method according to the present invention for achieving the object of the present invention by bonding a plurality of leads with a solder bump formed on the upper surface of the semiconductor chip, the bonding pad is arranged in the center via a non-conductive tape, After wire bonding the chip and the lead with conductive wires, molding the solder bumps, leads, and semiconductor chips with the mold resin, and then grinding the molded mold resin so that the solder bumps are recessed so that the solder bumps are exposed to the outside. Attach the solder balls to the solder bumps.

이하, 본 발명에 의한 칩 스케일 패키지 및 그 제조 방법을 첨부된 도면을 참조하여 구체적으로 설명하면 다음과 같다.Hereinafter, a chip scale package according to the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings.

본 발명에 의한 칩 스케일 패키지(100)는 도 4에 전체적인 형상 및 구조가 도시되어 있다.Chip scale package 100 according to the present invention is shown in Figure 4 the overall shape and structure.

본 발명에 의한 칩 스케일 패키지(100)는 전체적으로 보아 센터에 본딩 패드(10)가 형성된 반도체 칩(20), 반도체 칩(20)의 상면에 형성된 본딩 패드(10)의 바깥쪽으로 본딩 패드(10)와 평행하게 형성된 비전도성 접착 테이프(30), 비전도성 접착 테이프(30)에 일측 단부가 부착된 복수개의 리드(40), 본딩 패드(10)와 리드(40)를 연결하는 와이어(5), 각 리드(40)에 하나씩 전기적으로 연결된 솔더 범프(50), 솔더 범프(50)가 외부에 대하여 노출되도록 하면서도 반도체 칩(20)의 일부 또는 전부를 감싸는 몰딩 수지(60), 솔더 범프(50)에 부착된 솔더 볼(70)로 구성된다.In the chip scale package 100 according to the present invention, the bonding pad 10 is formed on the outside of the bonding chip 10 formed on the upper surface of the semiconductor chip 20 and the bonding pad 10 formed at the center. A non-conductive adhesive tape 30 formed in parallel with the plurality of leads 40 having one end attached to the non-conductive adhesive tape 30, a wire 5 connecting the bonding pad 10 and the lead 40, Solder bumps 50 electrically connected to each lead 40 and molding resins 60 and solder bumps 50 covering part or all of the semiconductor chip 20 while allowing the solder bumps 50 to be exposed to the outside. It consists of a solder ball 70 attached to it.

이와 같이 구성된 칩 스케일 패키지(100)를 제작하는 방법을 첨부된 도 1 내지 도 3을 참조하여 설명하면 다음과 같다.A method of manufacturing the chip scale package 100 configured as described above will be described with reference to FIGS. 1 to 3.

먼저, 첨부된 도 1 내지 도 3a를 통하여 본 발명에 의하여 리드(40)에 솔더 범프(50)를 형성하는 과정을 설명하면 다음과 같다.First, the process of forming the solder bumps 50 in the lead 40 by the present invention through the accompanying Figures 1 to 3a as follows.

첨부된 도 1에는 본 발명에 의한 칩 스케일 패키지(100)의 리드(40)가 도시되어 있다.1, the lid 40 of the chip scale package 100 according to the present invention is shown.

도 1에 점선으로 도시된 도면부호 20은 앞서 설명한 반도체 칩(20)이 위치할 부분으로 도면부호 20에 의하여 리드(40)과 반도체 칩(20)의 위치 관계를 알 수 있다.Reference numeral 20 shown as a dotted line in FIG. 1 indicates a position where the semiconductor chip 20 described above is to be located, and the positional relationship between the lead 40 and the semiconductor chip 20 may be determined by the reference numeral 20.

도면부호 10는 앞서 언급한 반도체 칩(20)의 센터에 형성된 본딩 패드의 위치를 도시하고 있으며, 도면부호 30은 앞서 설명한 본딩 패드(10)와 소정 거리 평행하게 이격된 곳에 형성된 비전도성 접착 테이프이다.Reference numeral 10 denotes a position of the bonding pad formed at the center of the semiconductor chip 20 mentioned above, and reference numeral 30 is a non-conductive adhesive tape formed at a predetermined distance in parallel with the above-described bonding pad 10. .

리드(40)는 반도체 칩(20)의 중심을 기준으로 좌우로 대칭된 형상을 갖는 바, 도 1에 도시된 리드(40)중 오른쪽에 도시된 리드(40)를 일실시예로 설명하면 다음과 같다.The lead 40 has a shape symmetrically from side to side with respect to the center of the semiconductor chip 20. The lead 40 shown on the right side of the lead 40 shown in FIG. Same as

먼저, 비도전성 접착 테이프(30)가 뻗은 방향과 수직을 이루면서 상호 소정 간격을 이루도록 이격된 2 개의 선(line) Ⅰ,Ⅱ상에는 일실시예로 동일 간격을 갖는 3 개의 가상 원(circle;41,42,43)을 형성한다. 이 가상 원(41,42,43)이 형성되는 위치는 후술될 솔더 범프가 안착될 위치이다.First, three virtual circles 41 having equal spacing on two lines I and II spaced apart from each other at a predetermined distance from each other while being perpendicular to the direction in which the non-conductive adhesive tape 30 extends. 42,43). The positions at which the virtual circles 41, 42, 43 are formed are the positions at which solder bumps to be described later are seated.

리드(40)는 가상 원(41,42,43)의 개수와 동일한 개수를 갖으며, 각 리드(40)의 일측 단부는 비도전성 접착 테이프(30)에 접착되고, 타측 단부는 이미 정의되어 있는 가상 원(41,42,43)을 통과하는 형상을 갖을 수 있다.The leads 40 have the same number of virtual circles 41, 42, 43, one end of each lead 40 is bonded to the non-conductive adhesive tape 30, and the other end is already defined. It may have a shape passing through the virtual circles (41, 42, 43).

다르게 리드(40)의 타측 단부가 가상 원(41,42,43)에 위치될 정도의 길이를 갖아도 충분하다.Alternatively, it is sufficient to have a length such that the other end of the lid 40 is positioned in the virtual circles 41, 42, 43.

이와 같이 가상 원(41,42,43)이 상면에 형성된 리드(40)에는 포토 레지스트(미도시)가 도포되고, 포토 레지스트가 도포된 리드(40)의 상면에는 가상 원(41,42,43)에 해당하는 부분만이 개구된 마스크(미도시)가 올려진 다음 노광/현상 과정에 의하여 리드(40)중 가상 원(41,42,43)에 해당하는 부분이 외부로 노출되도록 한다.A photoresist (not shown) is applied to the lead 40 having the virtual circles 41, 42, and 43 formed on the upper surface, and the virtual circles 41, 42, 43 are applied to the upper surface of the lead 40 to which the photoresist is applied. Next, a mask (not shown) opening only a portion corresponding to) is raised, and a portion corresponding to the virtual circles 41, 42, and 43 of the lid 40 is exposed to the outside by an exposure / development process.

이후, 리드(40)를 에칭 용액에 넣어 리드(40)중 개구된 부분이 두께의 약 절반 정도가 에칭 되도록 하여 가상 원(41,42,43)과 동일한 형상을 갖는 요홈이 되도록 한다.Thereafter, the lead 40 is placed in an etching solution so that the opened portion of the lead 40 is etched about half of the thickness so as to have a groove having the same shape as the virtual circles 41, 42, 43.

이와 같이 가상 원(41,42,43)과 동일한 형상을 갖는 요홈을 이하 솔더 범프 홈(solder bump goove;44,45,46)이라 정의하기로 한다.As described above, recesses having the same shape as the virtual circles 41, 42, and 43 are referred to as solder bump gooves 44, 45, and 46.

이후 에칭이 종료된 리드(40)를 에칭 용액에서 꺼내어 세정 한 후, 리드(40)에 도포되어 있는 포토 레지스트를 모두 제거한다.Thereafter, after the etching is finished, the lead 40 is removed from the etching solution and cleaned, and then all photoresist applied to the lead 40 is removed.

이와 같은 공정을 거쳐 제작된 리드(40)를 측면에서 보았을 때, 도 2와 같은 형상을 갖게 된다.When viewed from the side of the lead 40 produced through such a process, it has a shape as shown in FIG.

이후, 솔더 범프 홈(44,45,46)에는 리드(40)로부터 소정 높이를 갖도록 돌출된 솔더 범프(47,48,49)가 형성되어 도 3a에 도시된 바와 같이 본 발명에 의한 리드(40)의 제작이 완료된다.Thereafter, the solder bump grooves 44, 45, and 46 are formed with solder bumps 47, 48, and 49 protruding from the lead 40 to have a predetermined height, and the lead 40 according to the present invention is illustrated in FIG. 3A. ) Production is completed.

이어서, 도 3b에 도시된 바와 같이 반도체 칩(20)의 상면에는 비전도성 접착 테이프(30)가 부착되고, 비전도성 접착 테이프(30)의 상면에는 도 3a에 도시된 리드(40)가 안착된다.Subsequently, as shown in FIG. 3B, a nonconductive adhesive tape 30 is attached to an upper surface of the semiconductor chip 20, and a lead 40 shown in FIG. 3A is seated on an upper surface of the nonconductive adhesive tape 30. .

이후, 와이어 본더(미도시)에 의하여 반도체 칩(20)에 형성된 본딩 패드(10)와 복수개의 리드(40)는 도전성 와이어(5)에 의하여 와이어 본딩된다.Thereafter, the bonding pads 10 and the plurality of leads 40 formed on the semiconductor chip 20 by wire bonders (not shown) are wire bonded by the conductive wires 5.

이어서, 도 3c에 도시된 바와 같이 몰드 수지(60)에 의하여 몰딩 공정이 진행되는데, 이때 몰딩 공정은 솔더 범프(47,48,49) 및 반도체 칩(20)을 모두 감싸도록 수행되거나 반도체 칩(20)의 상면만이 노출되도록 수행된다.Subsequently, as illustrated in FIG. 3C, a molding process is performed by the mold resin 60, in which the molding process is performed to cover all of the solder bumps 47, 48, and 49 and the semiconductor chip 20. Only the top surface of 20) is performed.

이후, 도 3d에 도시된 바와 같이 몰드 수지(60)에 의하여 감싸여진 솔더 범프(47,48,49)가 몰드 수지(60) 외부로 노출되도록 그라인더(grinder)에 의하여 그라인딩 공정이 수행된다.Thereafter, as illustrated in FIG. 3D, the grinding process is performed by a grinder such that the solder bumps 47, 48, and 49 surrounded by the mold resin 60 are exposed to the outside of the mold resin 60.

이와 같은 그라인딩 공정에 의하여 몰드 수지(60) 외부로 노출된 솔더 범프(47,48,49)의 상면에는 도 3e에 도시된 바와 같이 솔더 볼(70)이 안착된 후, 리플로우(reflow) 등의 방법에 의하여 솔더 범프(47,48,49)와 솔더 볼(70)이 어탯치 되도록 한다.After the solder balls 70 are seated on the upper surfaces of the solder bumps 47, 48, and 49 exposed to the outside of the mold resin 60 by the grinding process, reflow is performed. Solder bumps (47, 48, 49) and the solder ball 70 is attached by the method.

이후, 도 3f에 도시된 바와 같이 몰드 수지(60)의 외측으로 돌출된 리드(40)를 절단한 후, 신뢰성 테스트를 거쳐 도 4에 도시된 바와 같은 본 발명에 의한 칩 스케일 패키지(100)가 제작된다.Thereafter, after cutting the lead 40 protruding out of the mold resin 60 as shown in FIG. 3F, the chip scale package 100 according to the present invention as shown in FIG. 4 is subjected to a reliability test. Is produced.

이상에서 상세하게 설명한 바와 같이, 반도체 칩의 본딩 패드와 와이어에 의하여 전기적으로 연결된 리드의 상면에 솔더 범프를 형성하고 몰딩 후 솔더 범프가 외부에 대하여 노출되도록 한 후, 솔더 범프의 상면에 솔더 볼을 어탯치함으로써 반도체 칩의 상면에 리드의 일부가 안착되도록 하여 반도체 패키지의 전체 크기를 크게 감소시킴과 동시에 리드와 외부 기기의 연결은 볼 그리드 어레이 패키지 방식으로 하여 아웃터 리드가 필요 없게 되어 반도체 패키지의 취급이 매우 용이함은 물론 아웃터 리드로 인해 필요한 트리밍/포밍 공정 또한 필요없게 되어 반도체 패키지의 전체 크기는 더욱 감소됨은 물론 반도체 패키지의 신뢰성을 크게 향상시키는 효과가 있다.As described in detail above, after forming a solder bump on the upper surface of the lead electrically connected by the bonding pad and the wire of the semiconductor chip, after the molding to expose the solder bump to the outside, the solder ball on the upper surface of the solder bump By attaching a part of the lead to the upper surface of the semiconductor chip, the overall size of the semiconductor package is greatly reduced, and the connection between the lead and the external device is performed using a ball grid array package, which eliminates the need for an outer lead. This ease of use, as well as the trimming / forming process required by the outer lead, also eliminates the overall size of the semiconductor package and further increases the reliability of the semiconductor package.

Claims (3)

삭제delete 리드의 상부면에 솔더 범프를 형성하는 단계와;Forming a solder bump on the top surface of the lead; 비도전성 테이프를 매개로 하여 센터에 본딩 패드가 배열된 반도체 칩의 상면에 상기 리드의 하부면을 접착하는 단계와;Bonding a lower surface of the lead to an upper surface of a semiconductor chip in which bonding pads are arranged at a center through a non-conductive tape; 상기 반도체 칩과 상기 리드를 도전성 와이어로 와이어 본딩하는 단계와;Wire bonding the semiconductor chip and the lead with a conductive wire; 상기 솔더 범프, 상기 리드, 상기 반도체 칩을 몰드 수지로 몰딩하는 단계와;Molding the solder bumps, the leads, and the semiconductor chip with a mold resin; 상기 몰드 수지를 그라인딩(grinding)하여 상기 솔더 범프를 외부로 노출시키는 단계와;Grinding the mold resin to expose the solder bumps to the outside; 상기 솔더 범프에 솔더 볼을 어탯치하는 단계를 포함하는 것을 특징으로 하는 칩 스케일 패키지 제작 방법.And attaching solder balls to the solder bumps. 제 2 항에 있어서, 상기 리드에는 상기 솔더 범프가 형성되도록 솔더 범프 홈이 형성된 것을 특징으로 하는 칩 스케일 패키지 제작 방법.The method of claim 2, wherein the solder bump groove is formed in the lead to form the solder bump.
KR1019990036263A 1999-08-30 1999-08-30 Method for fabricating Chip scale package KR100629678B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990036263A KR100629678B1 (en) 1999-08-30 1999-08-30 Method for fabricating Chip scale package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990036263A KR100629678B1 (en) 1999-08-30 1999-08-30 Method for fabricating Chip scale package

Publications (2)

Publication Number Publication Date
KR20010019706A KR20010019706A (en) 2001-03-15
KR100629678B1 true KR100629678B1 (en) 2006-09-29

Family

ID=19609203

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990036263A KR100629678B1 (en) 1999-08-30 1999-08-30 Method for fabricating Chip scale package

Country Status (1)

Country Link
KR (1) KR100629678B1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980015059A (en) * 1996-08-19 1998-05-25 김광호 Method of manufacturing chip scale package using lead frame
JPH10275880A (en) * 1996-12-18 1998-10-13 Hyundai Electron Ind Co Ltd Chip-sized package semiconductor
KR19980078589A (en) * 1997-04-29 1998-11-16 김영환 Chip-sized package and its formation method
KR19990000382A (en) * 1997-06-05 1999-01-15 윤종용 Lead frame, chip scale package using same and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980015059A (en) * 1996-08-19 1998-05-25 김광호 Method of manufacturing chip scale package using lead frame
JPH10275880A (en) * 1996-12-18 1998-10-13 Hyundai Electron Ind Co Ltd Chip-sized package semiconductor
KR19980078589A (en) * 1997-04-29 1998-11-16 김영환 Chip-sized package and its formation method
KR19990000382A (en) * 1997-06-05 1999-01-15 윤종용 Lead frame, chip scale package using same and manufacturing method thereof

Also Published As

Publication number Publication date
KR20010019706A (en) 2001-03-15

Similar Documents

Publication Publication Date Title
US7125751B2 (en) Semiconductor device and method for the fabrication thereof grinding frame portion such that plural electrode constituent portions
US7193161B1 (en) SiP module with a single sided lid
US7615859B2 (en) Thin semiconductor package having stackable lead frame and method of manufacturing the same
US5923954A (en) Ball grid array package and fabrication method therefor
US20050104168A1 (en) Molded leadless package having improved reliability and high thermal transferability, and sawing type molded leadless package and method of manufacturing the same
US5708304A (en) Semiconductor device
US20080224283A1 (en) Leadframe-based semiconductor package and fabrication method thereof
US7781299B2 (en) Leadframe semiconductor package stand and method for making the same
US5951804A (en) Method for simultaneously manufacturing chip-scale package using lead frame strip with a plurality of lead frames
US5382546A (en) Semiconductor device and method of fabricating same, as well as lead frame used therein and method of fabricating same
US20150084171A1 (en) No-lead semiconductor package and method of manufacturing the same
KR100629678B1 (en) Method for fabricating Chip scale package
KR19990024255U (en) Stacked Ball Grid Array Package
US7183655B2 (en) Packaged semiconductor device
KR100391124B1 (en) Base of semiconductor package, semiconductor package using the same and method of manufacturing thereof
KR0185514B1 (en) Chip scale package and method of making the same
KR100508261B1 (en) Semiconductor package and method for manufacturing the same
KR200313831Y1 (en) Bottom Lead Package
KR20010004610A (en) transfer molded chip size package and method of fabricating the same
JP2504901B2 (en) Method for manufacturing multiple electronic component packages
KR19980048270A (en) Chip scale package with zigzag solder balls
KR20010066268A (en) stack-type semiconductor package and method for fabricating the same
KR19980082181A (en) Lead-on chip type chip scale semiconductor package structure and manufacturing method
KR19980059235A (en) Layout of Semiconductor Chip Pads for Lead-on Chip Packages
KR19990025703A (en) Chip scale package and its manufacturing method

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090914

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee