KR100242944B1 - Method for fabricating a semiconductor device - Google Patents

Abstract

In the method of manufacturing a semiconductor device according to the present invention, a process of forming a high temperature oxide film having a different thickness on a semiconductor substrate provided with a gate electrode, and etching the high temperature oxide film to cover the top of the gate electrode, the side of the gate electrode, and the top of the substrate The process consists of forming a spacer.

In the present invention, the high temperature oxide film, which is a precursor of the spacer, is formed to have a different thickness on the gate electrode and the substrate, thereby inducing a so-called ″ etch end point detection system ″ to be introduced into the spacer forming process, thereby finally forming the spacer. The etch rate shift phenomenon of the spacer can be prevented in advance.

In addition, in the present invention, the upper portion of the gate electrode is covered by the upper spacer of the gate electrode, thereby preventing counter doping and overlapping doping phenomena caused during ion implantation in advance.

Description

Method for fabricating a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of preventing counter doping and overlapping doping phenomena caused when manufacturing a semiconductor device having an LDD structure. It is about.

As the high integration of semiconductor devices proceeds, the minimum design line width decreases, so that the gate dimension is reduced, and thus the well drive-in is performed after the ion implantation process. As a result, the isolation spacers between the wells become smaller.

As such, when the isolation spacer between the wells becomes smaller, leakage current occurs between the gate and the gate-to-source / drain, resulting in deterioration of device characteristics.

As a method for preventing such a phenomenon, the proposed technique is to manufacture a transistor having an LDD structure. In order to form a transistor having an LDD structure, an oxide layer, for example, a spacer made of a high temperature oxide layer, is used. This will be described in detail with reference to the cross-sectional view shown in FIG. 1.

The transistor of the LDD structure which has been generally used conventionally is manufactured by the following process.

As a first process, polysilicon is deposited on the substrate 10, a photoresist pattern is formed thereon, and then the gate electrode 12 is formed by a photolithography process using the photoresist pattern as a mask, which is then used as a mask. Low concentrations of n-type or p-type impurities are implanted into the substrate 10 to form low-concentration n-type or p-type regions as impurity ion implantation regions in the left / right substrate 10 of the gate electrode 12. The low concentration n-type or p-type region is referred to as LDD region 14. Thereafter, the photoresist pattern on the gate electrode 12 is removed.

As a second process, an oxide film having a predetermined thickness is deposited on the substrate 10 and the gate electrode 12 on which the LDD region 14 is formed, and then etch-back the same by dry etching. Thus, spacers 16 made of an oxide film are formed on both sidewalls of the gate electrode 12. Subsequently, a high concentration of n-type or p-type impurities are ion-implanted into the substrate using the gate electrode 12 and the spacer 16 as a mask, and a high concentration of impurities is formed in the left / right substrates of the spacer 16. This step is completed by forming the n-type or p-type region 18 and removing the spacer 16. In this case, the high concentration n-type or p-type region 18 is used as a source / drain region.

That is, in the LDD transistor, the source / drain is formed through a high concentration of impurity ion implantation process using the spacer 16 to prevent leakage current between the gate electrode 12 and the source / drain.

At this time, the leakage current becomes larger as the length ″ L ″ of the spacer 16 becomes smaller, which acts as a factor that causes the deterioration of the characteristics of the semiconductor device. Therefore, much attention is paid to the etching process for forming the spacer.

However, in the conventional case, since the etching amount is controlled by the etching time when forming the spacer, an etch rate shift phenomenon occurs in which the etching amount changes in every process.

This phenomenon becomes worse when an etching process is performed using a substrate having a topology, and overetch or underetch occurs around the stepped portion.

In the case of over etching, the spacer length ″ L ″ becomes smaller, which leads to an increase in leakage current, which causes a problem in reliability of the device, and in the case of insufficient etching, the spacer is not formed properly. Since an oxide film having a thickness such that ion implantation is impossible is left on the substrate, a shielding phenomenon occurs during ion implantation, so that a well used as a high concentration n-type or p-type region, that is, a source / drain region, cannot be properly formed. Is raised.

In the case of manufacturing a transistor having an LDD structure using the above-described process, a part of the impurities are implanted when impurities are implanted from the gate electrode 12 toward the substrate to form the LDD region and the source / drain regions. Counter doping or excessive overlapping doping, which are doped together on the gate electrode surface, results in a sheet resistance shift phenomenon in which the resistance value of the gate electrode is changed. Here, the counter doping means that p-type impurities (eg, Br, etc.), which are Group III ions, are ion-implanted on the surface of the gate electrode made of POCl ₃ doped polycrystalline silicon. It means that the n-type impurity (for example, P, As, etc.) which is Group V ion is ion-implanted in the gate electrode surface of the gate electrode.

The sheet resistance shift phenomenon becomes more severe as a semiconductor device is highly integrated, which is a major factor in reducing the reliability of the device.

Accordingly, an object of the present invention is to provide a spacer on top of a gate electrode and a substrate so that a so-called "endpoint detection system" (hereinafter referred to as an "EPD system") can be flexibly applied to a spacer forming operation. By forming a high temperature oxide film, which is a precursor of, to a different thickness, the etch rate shift phenomenon of the finished spacer is prevented in advance.

Another object of the present invention is to form a spacer having a structure covering the top and sides of the gate electrode and the top of the substrate through the above-described EPD system, thereby preventing counter doping and overlapping doping phenomena caused during ion implantation in advance. It is.

1 is a cross-sectional view showing the structure of a semiconductor device according to the prior art;

2A and 2B are process flowcharts showing a method of manufacturing a semiconductor device according to the present invention;

A semiconductor device manufacturing method according to the present invention for achieving the above object comprises the steps of forming a gate electrode on a substrate using a photosensitive film pattern; Forming a lightly doped region in the substrate other than the gate electrode using the photoresist pattern as a mask; Forming a high temperature oxide film covering the gate electrode and the substrate with different thicknesses; By using the optical wavelength change caused by the difference in the thickness of the high temperature oxide film, the high temperature oxide film is etched back while controlling the etch rate of the high temperature oxide film to cover the top of the gate electrode, both sides and the top of the substrate. Forming; And forming a heavily doped source / drain region in the substrate, except for the lightly doped region, using the spacer as a mask.

As a result of the above process, it is possible to prevent the counter doping and the overlapping doping phenomenon caused during the manufacturing of the semiconductor device.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

First, as shown in FIG. 2A, in a production line, a focal doped polysilicon is deposited as a gate metal on a semiconductor substrate, for example, a single crystal silicon silicon substrate 100. A photoresist pattern (not shown) is formed on a predetermined portion of the gate metal, and the gate metal is etched by a photolithography process using the mask to form a gate electrode 102.

Subsequently, a low concentration of n-type or p-type dopant is ion-implanted into the substrate 100 except for the gate electrode 102 using the photoresist pattern as a mask to remove the photoresist pattern. As a result, an LDD region (not shown) is formed as a low concentration impurity ion implantation region in the left / right substrate 100 of the gate electrode 102.

Next, a high temperature oxide film 104 is formed on the entire surface of the substrate 100 including the gate electrode 102. At this time, since the thermal oxidation phenomenon of silicon occurs simultaneously with the deposition process of the high temperature oxide film 104, the high temperature formed on the gate electrode 102 polycrystalline compared to the high temperature oxide film 104a formed on the single crystal substrate 100 The oxide film 104b is formed relatively thicker. For example, when the high temperature oxide film 104a is formed to a thickness of 1500 kPa, the high temperature oxide film 104b is formed to a thickness of 1700 kPa to 1750 kPa, which is about 200 kPa to 250 kPa.

As such, the high temperature oxide film 104 may exhibit a difference in thickness at each position because the polycrystalline silicon constituting the gate electrode 102 is less dense than the single crystalline silicon constituting the substrate 100.

In other words, in the present invention, when the high temperature oxide film 104 is deposited, the thickness of the high temperature oxide film 104 is dualized by using the film quality characteristics of the single crystal silicon and the polycrystalline silicon.

Subsequently, as shown in FIG. 2B, in the production line, an EPD system using an optical wavelength change according to a thickness difference of each position of the high temperature oxide film 104 (the thickness difference of the high temperature oxide film deposited to be dualized) is used. The high temperature oxide film 104 is etched back while controlling the etching rate of the high temperature oxide film 104. In this case, since the etching rate of the high temperature oxide film 104 is precisely controlled by the optical wavelength change due to the thickness difference for each position, unlike the conventional method, the etching caused by the etching process of the conventional high temperature oxide film 104 in the production line is performed. The effect of blocking the rate shift phenomenon in advance can be obtained.

When this process is completed, as shown in the figure, a spacer 105 is formed on the substrate 100. In this case, the spacer 105 may include a gate electrode upper spacer 105a, a gate electrode side spacer 105b, The substrate upper spacers 105c are combined with each other.

As described above, in the present invention, the spacer 105 to be finally formed can be formed by a combination of the gate electrode upper spacer 105a, the gate electrode side spacer 105b, and the substrate upper spacer 105c. In the production line, the high temperature oxide film 104 forming the precursor of the spacer 105 may be formed relatively thicker on the gate electrode 102 having the polycrystalline material than the substrate 100 having the single crystal material. This is because the high temperature oxide film 104 can be precisely etched by precise etching rate control using a so-called "EPD system" while the thickness difference of the high temperature oxide film 104 is taken into consideration.

Of course, in the conventional case in which the "EPD system" was not applied to the etching of the high temperature oxide film, it was difficult to precisely control the etching rate of the high temperature oxide film, and thus, the spacer having the same shape as the present invention could not be formed.

At this time, the gate electrode upper spacer 105a of the finally completed spacer 105 maintains a thickness thicker than that of the substrate upper spacer 105c. In this case, the substrate upper spacer 105c maintains a thickness of, for example, 50 ns or less, whereas the gate electrode upper spacer 105a maintains a thickness of, for example, 200 ns to 250 ns.

In particular, when the above-described spacer 105 is formed, it is most important to keep the thickness of the substrate upper spacer 105c below 50 μs. This is because when the ion implantation process is performed, an ion shielding phenomenon may occur, which may cause a problem that the entire ion implantation process may not be performed smoothly.

In order to prevent such a problem in advance, in the present invention, the thickness of the substrate upper spacer 105c is maintained at 50 kPa or less.

Subsequently, in the production line, the gate electrode 102 and the spacer 105 are used as masks, and a high concentration of n-type or p-type impurities are ion-implanted into the substrate 100 to thereby source the left and right substrates of the spacer 105. Drain region is formed, and the present invention is completed.

In this case, as described above, since the gate electrode upper spacer 105c is disposed on the upper portion of the gate electrode 102 while maintaining the thickness of, for example, 200 μs to 250 μs, it may be caused in the above-described ion implantation process. It is possible not only to prevent counter doping and excessively redundant doping, but also to prevent a problem caused by this, for example, a change in resistance of the gate.

As described above, in the present invention, a high temperature oxide film, which is a precursor of a spacer, is formed on the gate electrode and the substrate at different thicknesses, thereby inducing a so-called ″ EPD system ″ to be introduced into the spacer forming process. The etch rate shift phenomenon of the spacer to be prevented can be prevented in advance.

In addition, in the present invention, the upper portion of the gate electrode is covered by the upper spacer of the gate electrode, thereby preventing counter doping and overlapping doping phenomena caused during ion implantation in advance.

Claims (3)

Forming a gate electrode of polycrystalline silicon on a substrate of monocrystalline silicon; Forming a lightly doped region in the substrate other than the gate electrode; Forming a high temperature oxide film covering the gate electrode and the substrate with different thicknesses; By using the optical wavelength change due to the positional thickness difference of the high temperature oxide film, the high temperature oxide film is etched back while controlling the etch rate of the high temperature oxide film to cover the top, both sides of the gate electrode, and the top of the substrate. Forming a spacer; And forming a heavily doped source / drain region in the substrate, except for the lightly doped region, using the spacer as a mask. The method of claim 1, wherein a thickness of the spacer covering the upper portion of the substrate is 50 μs or less. The method of claim 1, wherein the spacer covering the upper portion of the gate electrode has a thickness of about 200 μs to about 250 μs.