KR100186327B1 - Method of fabricating mosfet - Google Patents
Method of fabricating mosfet Download PDFInfo
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- KR100186327B1 KR100186327B1 KR1019960019640A KR19960019640A KR100186327B1 KR 100186327 B1 KR100186327 B1 KR 100186327B1 KR 1019960019640 A KR1019960019640 A KR 1019960019640A KR 19960019640 A KR19960019640 A KR 19960019640A KR 100186327 B1 KR100186327 B1 KR 100186327B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 76
- 150000002500 ions Chemical class 0.000 claims abstract description 43
- 229920005591 polysilicon Polymers 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 39
- 125000006850 spacer group Chemical group 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 27
- 238000000151 deposition Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 150000004767 nitrides Chemical class 0.000 claims description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 56
- 230000006866 deterioration Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
본 발명은 역-'T'자형 게이트(Inverse-'T' Gate)를 갖는 오프셋 엘디디 모스페트(offset LDD MOSFET)(이하, 'ITLDD 모스페트'라 한다)의 제조방법에 관한 것으로, 기판 위에 제1게이트산화막을 형성한 후, 그 위에 제1다결정실리콘층과 제1절연막 및 제2다결정실리콘층을 순차적으로 증착하는 제1공정과; 제2다결정실리콘층과 제1절연막을 패터닝하는 제2공정과; 제2절연막으로 제1측벽스페이서를 형성하는 제3공정과; 제2다결정실리콘층과 제1다결정실리콘층을 동시에 식각하는 제4공정과; 저농도 이온을 주입한 후, 제1측벽스페이서를 제거하는 제5공정과; 제1다결정실리콘층을 식각한 후, 그 위에 제2게이트산화막을 형성하는 제5공정과; 제3절연막으로 제2측벽스페이서를 형성하는 제6공정과; 고농도 이온을 주입한 후 어닐링하는 제7공정으로 이루어지는 것을 특징으로 한다. 따라서 상기와 같이 이루어지는 본 발명 ITLDD 모스페트의 제조방법은 LDD 구조의 소오스/드레인 영역이 역-'T'자 구조의 게이트와 겹치는 정도가 통상적인 모스페트의 경우 보다는 크고 종래 기술에 따른 ITLDD 모스페트의 경우 보다는 적게 되어, 통상적인 모스페트에 비해서는 핫 캐리어 특성이 개선될 뿐만 아니라 게이트의 전류구동능력이 향상되는 효과가 발생하고, 종래 ITLDD 모스페트에 비해서는 게이트와 소오스/드레인 사이의 오우버랩 캐패시턴스가 감소되는 효과가 발생한다.The present invention relates to a method of manufacturing an offset LDD MOSFET (hereinafter referred to as an 'ITLDD MOSFET') having an inverse-'T 'gate, on a substrate. Forming a first gate oxide film, and then sequentially depositing a first polycrystalline silicon layer, a first insulating film, and a second polycrystalline silicon layer thereon; A second step of patterning the second polysilicon layer and the first insulating film; A third step of forming a first side wall spacer with a second insulating film; A fourth step of simultaneously etching the second polycrystalline silicon layer and the first polycrystalline silicon layer; A fifth step of removing the first side wall spacer after implanting the low concentration ions; A fifth process of etching the first polycrystalline silicon layer and then forming a second gate oxide film thereon; A sixth step of forming a second side wall spacer with a third insulating film; It is characterized by comprising a seventh step of annealing after implanting high concentration ions. Therefore, in the method of manufacturing the present invention ITLDD MOSFET formed as described above, the degree to which the source / drain region of the LDD structure overlaps with the gate of the inverted-'T 'structure is larger than that of the conventional MOSFET and the ITLDD MOSFET according to the prior art. It is less than the case, not only improves the hot carrier characteristics compared to the conventional MOSFET, but also improves the current driving capability of the gate, and over wrap between the gate and the source / drain compared to the conventional ITLDD MOSFET. The effect is to reduce the capacitance.
Description
제1도는 종래 기술에 따른 역-'T'자형 게이트를 갖는 오프셋 엘디디 모스페트의 제조공정 수순도.1 is a flowchart of a process for manufacturing offset LEDs having an inverted-T gate according to the prior art.
제2도는 본 발명의 일실시예에 따른 역-'T'자형 게이트를 갖는 오프셋 엘디디 모스페트의 제조공정 수순도.2 is a flowchart of a manufacturing process of an offset LED MOSFET having an inverted-T gate according to an embodiment of the present invention.
제3도는 본 발명의 다른 실시예에 따른 역-'T'자형 게이트를 갖는 오프셋 엘디디 모스페트의 제조공정 수순도.3 is a flowchart of a manufacturing process of offset LEDs having an inverted-T gate according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
111, 211 : 기판 112, 212 : 제1게이트산화막111, 211: substrate 112, 212: first gate oxide film
113, 213 : 제1다결정실리콘층 114, 214 : 제1절연막113, 213: first polycrystalline silicon layer 114, 214: first insulating film
115, 215 : 제2다결정실리콘층 116, 216 : 포토레지스트115, 215: Second polycrystalline silicon layer 116, 216: Photoresist
117, 217 : 제1측벽스페이서 118, 119, 218, 219 : LDD 영역117, 217: first side wall spacer 118, 119, 218, 219: LDD region
120, 220 : 제2게이트산화막 121, 221 : 제2측벽스페이서120, 220: second gate oxide film 121, 221: second side wall spacer
122, 123, 222, 223 : 고농도 소오스/드레인 영역122, 123, 222, 223: high concentration source / drain regions
본 발명은 모스페트(MOSFET)의 제조방법에 관한 것으로, 특히 역-'T'자형 게이트(Inverse-'T' Gate)를 갖는 오프셋 엘디디 모스페트(offset LDD MOSFET)의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOSFET, and more particularly, to a method of manufacturing an offset LDD MOSFET having an inverse-'T 'gate.
게이트가 일정한 두께로 형성됨과 아울러 그 게이트가 소오스/드레인 영역과 적게 오우버랩되는 통상적인 모스페트는 게이트의 전류구동능력이 저하되는 문제점이 있었다.Conventional MOSFETs in which the gate is formed to a certain thickness and the gate is slightly overlaid with the source / drain regions have a problem in that the gate current driving capability is lowered.
상기와 같은 문제점을 개선하기 위하여 역-'T'자형 게이트(Inverse-'T' Gate)를 갖는 오프셋 LDD 모스페트(offset LDD MOSFET)가 제안되었는데, 그 역-'T'자형 게이트를 갖는 오프셋 LDD 모스페트는 게이트가 소오스/드레인의 LDD(Lightly Doped Drain)영역과 완전히 겹치도록 형성됨과 아울러 그 소오스/드레인의 LDD영역 위에서는 얇게 형성되고 그 사이의 채널 위에서는 두껍게 형성되는 모스페트로서, 핫 캐리어 특성이 향상됨과 아울러 게이트의 전류구동능력이 향상되는 장점이 있었다. 이하, 상기 역-'T'자형 게이트를 갖는 오프셋 LDD 모스페트의 종래 기술에 따른 제조방법에 대해서 첨부된 도면을 참조하여 설명하면 다음과 같다.In order to solve the above problem, an offset LDD MOSFET having an inverse-'T 'gate has been proposed, and an offset LDD having an inverse-'T' gate is proposed. Mosfet is a mosfet whose gate is formed so as to completely overlap with the lightly doped drain (LDD) region of the source / drain, and is thinly formed on the LDD region of the source / drain and thickly formed on the channel between them. In addition to the improved characteristics, the current driving capability of the gate was improved. Hereinafter, a manufacturing method according to the related art of the offset LDD MOSFET having the inverted-'T 'gate will be described with reference to the accompanying drawings.
제1도의 (a) 내지 (f)는 역-'T'자형 게이트를 갖는 오프셋 LDD 모스페트의 종래 기술에 따른 제조방법을 설명하기 위한 공정 수순도로서, (a)도는 기판(11) 위에 게이트산화막(12)을 형성한 후, 그 위에 다결정실리콘(13)과 캡산화막(14)을 순차로 증착한 다음, 그 캡산화막(14) 위에 게이트를 형성하기 위한 레지스트 패턴(15)을 형성하는 공정을 나타내고, (b)도는 레지스트 패턴(15)을 이용하여 제1산화막(14)을 에칭한 후, 다결정실리콘층(13)을 일정한 시간 동안 에칭하여 그 레지스트 패턴(15)의 양쪽에 얇은 다결정실리콘층(13)을 형성하고 나서, 그 레지스트 패턴(15)을 제거하는 공정을 나타내며, (c)도는 저농도 이온(N-)을 주입하여 LDD영역(16a, 16b)을 형성하는 공정을 나타내며, (d)도는 그 위에 산화막을 증착한 후 에치백하여 측벽스페이서(17)를 형성하는 공정을 나타내고, (e)도는 그 측벽스페이서(17)와 캡산화막(14)을 마스크로 하여 다결정실리콘층(13)을 에칭하는 공정을 나타내며, (f)도는 고농도 이온(N+)을 주입하여 고농도 소오스/드레인 영역(18a, 18b)을 형성하는 공정을 나타낸다.(A) to (f) in FIG. 1 are process steps for explaining a conventional manufacturing method of an offset LDD MOSFET having an inverted-'T 'gate, and (a) is a gate on the substrate 11. After the oxide film 12 is formed, the polycrystalline silicon 13 and the cap oxide film 14 are sequentially deposited thereon, and then a resist pattern 15 for forming a gate on the cap oxide film 14 is formed. (B) shows that the first oxide film 14 is etched using the resist pattern 15, and then the polysilicon layer 13 is etched for a predetermined time to thin polysilicon on both sides of the resist pattern 15. After forming the layer 13, the process of removing the resist pattern 15 is shown, (c) shows the process of forming the LDD regions 16a and 16b by implanting low concentration ions (N − ), ( d) shows a step of forming a sidewall spacer 17 by depositing an oxide film thereon and then etching it back. Out, (e) turn represents the step of etching the polycrystalline silicon layer 13 and the sidewall spacers 17 and cap oxide films 14 as a mask, (f) turning high concentration by injecting a high concentration of ions (N +) source The process of forming / drain regions 18a and 18b is shown.
그러나 상기에서 설명한 역-'T'자형 게이트를 갖는 오프셋 LDD 모스페트의 종래 기술에 따른 제조방법은 1) 저농도 이온이 통과한 얇은 다결정실리콘층과 그 아래의 게이트산화막이 각각 얇은 게이트 영역과 게이트산화막으로 사용되기 때문에 발생되는, 게이트산화막의 특성이 열화되는 문제점과, 2) 얇은 게이트 영역과 소오스/드레인의 LDD영역이 완전히 겹치도록 구성되기 때문에 발생되는, 게이트와 소오스/드레인 사이의 캐패시턴스가 너무 크게 되는 문제점과, 3) 얇은 게이트 영역을 형성하기 위하여 다결정실리콘을 일정한 시간 동안 에칭하는 공정으로는 그 다결정실리콘층의 두께를 정확히 컨트롤할 수 없다는 문제점이 있었다.However, the conventional manufacturing method of the offset LDD MOSFET having the inverted-'T 'gate described above is a method of manufacturing a thin polysilicon layer through which low concentration ions pass and a gate oxide film below the thin gate region and the gate oxide film, respectively. 2) the capacitance between the gate and the source / drain caused by the thin gate region and the LDD region of the source / drain are completely overlapped. And 3) a process of etching polycrystalline silicon for a predetermined time to form a thin gate region, which does not allow precise control of the thickness of the polysilicon layer.
이에 본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 첫째 게이트와 소오스/드레인이 겹치는 오우버랩 정도가 통상적인 모스페트 보다는 크지만 제1도에 도시된 종래 ITLDD 모스페트 보다는 적도록 하여 통상적인 모스페트에 비해서는 핫 캐리어 현상이 개선될 뿐만 아니라 게이트의 전류구동능력이 향상되도록 하고 종래 ITLDD 모스페트에 비해서는 게이트와 소오스/드레인 사이의 캐패시턴스가 감소되도록 하며, 둘째 제2다결정실리콘층의 식각 종료점을 감지하는 방법을 통해 제1다결정실리콘층의 식각량을 조절함으로써, 그 제1다결정실리콘층의 식각량을 정확히 조절할 수 있을 뿐만 아니라 저농도 소오스/드레인 영역의 윤곽을 정확히 조절할 수 있도록 하고, 셋째 LDD 영역을 형성하기 위해 주입되는 이온이 게이트의 얇은 층이 형성될 제1다결정실리콘층과 그 아래의 게이트산화막을 통과하지 않도록 하여 그 게이트산화막의 특성 열화를 방지하도록 한 역-'T'자형 게이트를 갖는 오프셋 LDD 모스페트의 제조방법을 제공함에 그 목적이 있다.Therefore, the present invention has been devised to solve the above-described conventional problems, and the first, the degree of overlap overlapping the gate and the source / drain is larger than that of the conventional MOSFET, but less than that of the conventional ITLDD MOSFET shown in FIG. In addition to improving the hot carrier phenomenon compared to the conventional MOSFET, the gate current driving capability is improved, and the capacitance between the gate and the source / drain is reduced as compared to the conventional ITLDD MOSFET, and the second polycrystalline silicon By adjusting the etching amount of the first polysilicon layer by detecting the etching end point of the layer, not only the etching amount of the first polysilicon layer can be precisely adjusted but also the contour of the low concentration source / drain region can be precisely adjusted. And the ions implanted to form the third LDD region are thin To provide a method for producing an offset LDD MOSFET having an inverted-'T 'gate so as not to pass through the first polysilicon layer to be formed and the gate oxide film thereunder to prevent deterioration of the gate oxide film's characteristics. There is this.
상기와 같은 목적을 달성하기 위한 본 발명(Ⅰ)은 기판 위에 제1게이트산화막을 형성한 후, 그 위에 제1다결정실리콘층과 제1절연막 및 제2다결정실리콘층을 순차적으로 증착하는 제1공정과; 제2다결정실리콘층과 제1절연막을 패터닝하는 제2공정과; 제2절연막으로 제1측벽스페이서를 형성하는 제3공정과; 제2다결정실리콘층과 제1다결정실리콘층을 동시에 식각하는 제4공정과; 저농도 이온을 주입한 후, 제1측벽스페이서를 제거하는 제5공정과; 제1다결정실리콘층을 식각한 후, 그 위에 제2게이트산화막을 형성하는 제5공정과; 제3절연막으로 제2측벽스페이서를 형성하는 제6공정과; 고농도 이온을 주입한 후 어닐링하는 제7공정으로 이루어지는 것을 특징으로 한다.The present invention (I) for achieving the above object is a first step of forming a first gate oxide film on a substrate, and then sequentially depositing a first polycrystalline silicon layer, a first insulating film and a second polycrystalline silicon layer thereon and; A second step of patterning the second polysilicon layer and the first insulating film; A third step of forming a first side wall spacer with a second insulating film; A fourth step of simultaneously etching the second polycrystalline silicon layer and the first polycrystalline silicon layer; A fifth step of removing the first side wall spacer after implanting the low concentration ions; A fifth process of etching the first polycrystalline silicon layer and then forming a second gate oxide film thereon; A sixth step of forming a second side wall spacer with a third insulating film; It is characterized by comprising a seventh step of annealing after implanting high concentration ions.
그리고 상기 목적을 달성하기 위한 본 발명(Ⅱ)은 기판 위에 제1게이트산화막을 형성한 후, 그 위에 제1다결정실리콘층과 제1절연막 및 제2다결정실리콘층을 순차적으로 증착하는 제1공정과; 제2다결정실리콘층과 제1절연막을 패터닝하는 제2공정과; 제2다결정실리콘층과 제1다결정실리콘층을 동시에 식각하는 제3공정과; 제2절연막으로 제1측벽스페이서를 형성하는 제4공정과; 저농도 이온을 주입한 후, 제1다결정실리콘층을 식각하는 제5공정과; 그 위에 제2게이트산화막을 형성한 후, 제3절연막으로 제2측벽스페이서를 형성하는 제6공정과; 고농도 이온을 주입한 후 어닐링하는 제7공정으로 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a first process of forming a first gate oxide film on a substrate, and then sequentially depositing a first polycrystalline silicon layer, a first insulating film, and a second polycrystalline silicon layer thereon. ; A second step of patterning the second polysilicon layer and the first insulating film; A third step of simultaneously etching the second polycrystalline silicon layer and the first polycrystalline silicon layer; A fourth step of forming a first side wall spacer with a second insulating film; A fifth step of etching the first polycrystalline silicon layer after implanting low concentration ions; A sixth step of forming a second gate oxide film thereon and then forming a second side wall spacer with a third insulating film; It is characterized by comprising a seventh step of annealing after implanting high concentration ions.
이하, 첨부된 도면 제2도와 제3도를 참조하여 상기와 같이 구성되는 본 발명(Ⅰ,Ⅱ)의 바람직한 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings 2 and 3 will be described a preferred embodiment of the present invention (I, II) configured as described above.
제2도의 (a) 내지 (g)는 본 발명(Ⅰ) 역-'T'자형 게이트를 갖는 오프셋 엘디디 모스페트의 제조방법에 대한 일실시예를 도시한 공정수순도로서, 이를 참조하여 상세히 설명하면 다음과 같다.(A) to (g) of FIG. 2 are process flowcharts showing an embodiment of a method for manufacturing an offset LED mold having an inverted-'T 'gate in accordance with the present invention. The explanation is as follows.
제2(a)도는 기판(111) 위에 제1게이트산화막(112)을 형성한 후, 제1다결정실리콘층(113)과 제1절연막(114) 및 제2다결정실리콘층(115)을 순차적으로 증착하는 공정과, 그 위에 레지스트 패턴(116)을 형성하는 공정을 나타낸다. 이때 제1다결정실리콘층(113)은 제2다결정실리콘층(115) 보다 두껍게 형성하고, 제1절연막(114)은 산화막 또는 질화막을 CVD방식으로 증착하여 형성한다.In FIG. 2A, after the first gate oxide layer 112 is formed on the substrate 111, the first polysilicon layer 113, the first insulating layer 114, and the second polysilicon layer 115 are sequentially formed. The process of vapor deposition and the process of forming the resist pattern 116 on it are shown. At this time, the first polysilicon layer 113 is formed thicker than the second polysilicon layer 115, and the first insulating layer 114 is formed by depositing an oxide film or a nitride film by CVD.
그리고 제2(b)도는 레지스트 패턴(116)을 마스크로 하여 제2다결정실리콘층(115)과 제1절연막(114)을 순차적으로 식각하는 공정과, 레지스트 패턴(116)을 제거한 후, 그 위에 제2절연막을 증착/에치백하여 제2다결정실리콘층과 제1절연막 패턴(115, 116)의 측면에 제1측벽스페이서(117)를 형성하는 공정을 나타낸다. 이때 제2절연막(117)은 질화막(제1절연막이 산화막으로 형성되는 경우) 또는 산화막(제1절연막이 질화막으로 형성되는 경우)으로 선택될 수 있다.FIG. 2 (b) shows a step of sequentially etching the second polysilicon layer 115 and the first insulating film 114 using the resist pattern 116 as a mask, and removing the resist pattern 116 thereon. A process of forming the first side wall spacers 117 on the side surfaces of the second polysilicon layer and the first insulating film patterns 115 and 116 by depositing / etching back the second insulating film is shown. In this case, the second insulating film 117 may be selected as a nitride film (when the first insulating film is formed of an oxide film) or an oxide film (when the first insulating film is formed of a nitride film).
제2(c)도는 제2다결정실리콘층(114)과 제1다결정실리콘층(113)을 동시에 식각하여, 제2다결정실리콘층(114)은 완전히 제거되고 제1다결정실리콘층(113)은 제1절연막(114)과 제1측벽스페이서(117)가 있는 영역을 제외한 바깥쪽에 얇은 층(113a)이 형성되는 공정을 나타내고, 제2(d)도는 그 결과물에 대하여 고에너지 저농도 이온(N-)을 주입하여 LDD영역을 형성하는 공정을 나타내며, 제2(e)도는 제1측벽스페이서(117)를 제거한 후, 제1다결정실리콘층(113)을 식각하여 최초의 얇은 층(113a)은 완전히 제거되고, 제1측벽스페이서(117)가 있었던 영역의 두꺼운 층은 상기 최초의 얇은 층(113a) 만큼 식각되어 두 번째 얇은 층(113b)으로 형성되는 공정을 나타낸다. 위에서 nMOSFET를 제조하는 경우에는 고에너지 저농도 인(P)이온이나 아르곤(Ar)이온을 주입하고, pMOSFET를 제조하는 경우에는 고에너지 저농도 BF2이온이나 붕소(B)이온을 주입하여 LDD 영역(118, 119)을 형성한다. 따라서 고에너지 저농도 이온(N-)이 최초의 얇은 층(113a)을 관통하여 형성되는 LDD 영역(118, 119)이 제1측벽스페이서(117) 아래의 두꺼운 제1다결정실리콘층(113)과 충분히 겹치게 된다. 그리고 제2다결정실리콘층(115)과 제1다결정실리콘층(113)을 동시에 식각하여 최초의 얇은 층(113a)을 형성하는 공정과 두꺼운 제1다결정실리콘층(113)과 상기 최초의 얇은 층(113a)을 동시에 식각하여 두 번째 얇은 층(113b)을 형성하는 공정은 각각 제2다결정실리콘층(115)과 최초의 얇은 층(113a)이 완전히 식각될 때까지 식각하기 때문에, 최초의 얇은 층(113a)과 두 번째 얇은 층(113b)이 이상적인 두께로 식각된다.In FIG. 2C, the second polysilicon layer 114 and the first polysilicon layer 113 are simultaneously etched, so that the second polysilicon layer 114 is completely removed and the first polysilicon layer 113 is removed. 1 shows a process of forming a thin layer 113a on the outside except for the region where the insulating film 114 and the first side wall spacer 117 are located, and FIG. 2 (d) shows high energy and low concentration ions (N − ) with respect to the resultant. Shows the process of forming the LDD region, and in FIG. 2 (e), after removing the first side wall spacer 117, the first polysilicon layer 113 is etched to completely remove the first thin layer 113a. The thick layer in the region where the first side wall spacer 117 was located is etched by the first thin layer 113a to form the second thin layer 113b. In the case of manufacturing the nMOSFET, a high energy low concentration phosphorus (P) ion or an argon (Ar) ion is implanted. In the manufacture of a pMOSFET, a high energy low concentration BF 2 ion or boron (B) ion is implanted into the LDD region 118 , 119). Therefore, the LDD regions 118 and 119 where the high energy low concentration ions N − are formed through the first thin layer 113a are sufficiently formed with the thick first polysilicon layer 113 under the first side wall spacer 117. Overlap. And simultaneously etching the second polysilicon layer 115 and the first polysilicon layer 113 to form the first thin layer 113a, and the thick first polysilicon layer 113 and the first thin layer ( The process of simultaneously etching 113a) to form the second thin layer 113b is performed by etching the second polycrystalline silicon layer 115 and the first thin layer 113a until the first thin layer 113a is completely etched. 113a) and the second thin layer 113b are etched to the ideal thickness.
그리고 제2(f)도는 기판(111) 위와 제1다결정실리콘층(113) 및 제1절연막(114) 위에 제2게이트산화막(120)을 형성한 후, 그 위에 제3절연막을 증착하고 에치백하여 제2측벽스페이서(121)를 형성하는 공정을 나타내고, 제2(g)도는 고농도 이온(N+)을 주입함으로써 고농도 소오스/드레인 영역(122, 123)을 형성한 후, 어닐링하는 공정을 나타낸다. 위에서 제2측벽스페이서(121)는 산화막 또는 질화막을 CVD방식으로 증착한 후 그를 에치백하여 형성하고, 고농도 소오스/드레인 영역(122, 123)은 LDD 영역(118, 119)에 주입된 이온과 같은 종류의 이온을 주입하여 형성한다.After forming the second gate oxide film 120 on the substrate 111, the first polysilicon layer 113, and the first insulating film 114, the second insulating film 120 is deposited and etched back. FIG. 2 (g) shows a process of forming a high concentration source / drain regions 122 and 123 by implanting high concentration ions (N + ), followed by annealing. . The second side wall spacer 121 is formed by depositing an oxide film or a nitride film by CVD and then etching it back, and the high concentration source / drain regions 122 and 123 are formed such as ions implanted into the LDD regions 118 and 119. It is formed by implanting kinds of ions.
한편, 제3(a) 내지 제3(g)도는 본 발명(Ⅱ) 역-'T'자형 게이트를 갖는 오프셋 엘디디 모스페트의 제조방법의 다른 실시예를 도시한 공정수순도로서, 이를 참조하여 상세히 설명하면 다음과 같다.Meanwhile, FIGS. 3 (a) to 3 (g) are process flowcharts showing another embodiment of the method for manufacturing offset LED molds having the inverse-'T'-shaped gate of the present invention. When described in detail as follows.
제3(a)도는 기판(211) 위에 제1게이트산화막(212)을 형성한 후, 제1다결정실리콘층(213)과 제1절연막(214) 및 제2다결정실리콘층(215)을 순차적으로 증착하는 공정과, 그 위에 레지스트 패턴(216)을 형성하는 공정을 나타낸다. 이때 상기 제1다결정실리콘층(213)은 제2다결정실리콘층(215) 보다 두껍게 형성하고, 제1절연막(214)은 산화막 또는 질화막을 CVD방식으로 증착하여 형성한다.In FIG. 3A, after the first gate oxide film 212 is formed on the substrate 211, the first polysilicon layer 213, the first insulating layer 214, and the second polysilicon layer 215 are sequentially formed. The process of vapor deposition and the process of forming the resist pattern 216 on it are shown. In this case, the first polysilicon layer 213 is formed thicker than the second polysilicon layer 215, and the first insulating layer 214 is formed by depositing an oxide film or a nitride film by CVD.
그리고 제3(b)도는 레지스트 패턴(216)을 마스크로 하여 제2다결정실리콘층(215)과 제1절연막(214)을 순차적으로 식각하는 공정을 나타내며, 제3(c)도는 레지스트 패턴(216)을 제거한 후, 제1,2다결정실리콘층(213, 215)을 동시에 식각하여 제2다결정실리콘층(215)은 완전히 제거하고 제1다결정실리콘층(213)은 제1절연막 패턴(214)이 있는 영역을 제외한 바깥 쪽에 얇은 층(213a)을 형성하는 공정을 나타낸다.FIG. 3B illustrates a process of sequentially etching the second polysilicon layer 215 and the first insulating layer 214 using the resist pattern 216 as a mask. FIG. 3C illustrates the resist pattern 216. FIG. ), The first and second polysilicon layers 213 and 215 are simultaneously etched to completely remove the second polysilicon layer 215 and the first polysilicon layer 213 is formed by the first insulating film pattern 214. A process of forming the thin layer 213a on the outer side except for the region where there is is shown.
제3(d)도는 제1다결정실리콘층(213)과 제1절연막(214) 위에 제2절연막을 증착하고 에치백하여 제1절연막(214)과 두꺼운 제1다결정실리콘층(213)의 측면에 제1측벽스페이서(217)를 형성하는 공정과, 고에너지 저농도 이온(N-)을 주입하여 LDD 영역(218, 219)을 형성하는 공정을 나타낸다. 위에서 제2절연막(217)은 산화막 또는 질화막을 CVD방식으로 증착하여 형성하고, nMOSFET를 제조하는 경우에는 고에너지 인(P)이온 또는 아르곤(Ar)이온을 주입하고, pMOSFET를 제조하는 경우에는 고에너지 BF2또는 붕소(B)이온을 주입하여 LDD 영역(218, 219)을 형성한다. 따라서 고에너지 저농도 이온(N-)이 얇은 층(213a)을 관통하여 형성되는 LDD 영역(218, 219)이 제1측벽스페이서(217) 아래의 두꺼운 제1다결정실리콘층(213)과 충분히 겹치게 된다.In FIG. 3D, a second insulating layer is deposited on the first polysilicon layer 213 and the first insulating layer 214 and etched back to the side surfaces of the first insulating layer 214 and the thick first polysilicon layer 213. A step of forming the first side wall spacer 217 and a step of forming the LDD regions 218 and 219 by implanting high energy low concentration ions (N − ) are shown. The second insulating film 217 is formed by depositing an oxide film or a nitride film by a CVD method, implanting high energy phosphorus (P) ions or argon (Ar) ions in the manufacture of an nMOSFET, and high in the case of manufacturing a pMOSFET. Energy BF 2 or boron (B) ions are implanted to form LDD regions 218 and 219. Therefore, the LDD regions 218 and 219 formed by the high energy low concentration ions N − through the thin layer 213a sufficiently overlap with the thick first polysilicon layer 213 under the first side wall spacer 217. .
그리고 제3(e)도는 제1다결정실리콘층(213)을 식각함으로써 제1절연막(214) 아래의 두꺼운 층과 제1측벽스페이서(217)가 있는 얇은 층(213a) 영역을 제외한 바깥 쪽의 얇은 층(213a)을 완전히 제거하는 공정을 나타내고, 제3(f)도는 그 위에 제2게이트산화막(220)을 형성한 후, 제3절연막을 증착/에치백하여 제2측벽스페이서(221)를 형성하는 공정을 나타낸다. 이때 상기 제2측벽스페이서(221)는 산화막 또는 질화막을 CVD방식으로 증착한 후 에치백하여 형성한다. 한편 상기 제2측벽스페이서(221)와 제2게이트산화막(220)은 선택적으로 하나 또는 두 절연막 모두가 생략될 수 있다.In FIG. 3 (e), the first polycrystalline silicon layer 213 is etched so that the outer thin layer except for the thick layer under the first insulating layer 214 and the thin layer 213a region having the first side wall spacer 217 is formed. A step of completely removing the layer 213a is shown, and after forming the second gate oxide film 220 thereon, the third insulating film is deposited / etched back to form the second side wall spacer 221. The process to make is shown. In this case, the second side wall spacer 221 is formed by depositing an oxide film or a nitride film by CVD and then etching back. Meanwhile, one or both insulating layers may be omitted in the second side wall spacer 221 and the second gate oxide layer 220.
제3(g)도는 고농도 이온(N+)을 주입하여 고농도 소오스/드레인 영역(222, 223)을 형성한 후 어닐링하는 공정을 나타낸다. 이때 고농도 소오스/드레인 영역(222, 223)은 상기 LDD 영역(218, 219)에 주입된 이온과 같은 종류의 이온이 주입되어 형성된다.FIG. 3 (g) shows a process of implanting high concentration ions (N + ) to form high concentration source / drain regions 222 and 223 and then annealing. In this case, the high concentration source / drain regions 222 and 223 are formed by implanting the same kind of ions implanted into the LDD regions 218 and 219.
이상에서 설명한 바와 같이 제2(a)도 내지 제2(g)도의 공정으로 구성된 본 발명(Ⅰ) 역-'T'자형 게이트를 갖는 오프셋 엘디디 모스페트의 제조방법과 제3(a)도 내지 제3(g)도의 공정으로 구성된 본 발명(Ⅱ) 역-'T'자형 게이트를 갖는 오프셋 엘디디 모스페트의 제조방법은 첫째, LDD 구조의 소오스/드레인 영역이 역-'T'자 구조의 게이트와 겹치는 정도가 통상적인 모스페트의 경우 보다는 크고 상기 제1도에 도시된 종래 ITLDD 모스페트의 경우 보다는 작게 되어, 통상적인 모스페트에 비해서는 핫 캐리어 특성이 개선될 뿐만 아니라 게이트의 전륙동능력이 향상되는 효과가 발생하고, 종래 ITLDD 모스페트에 비해서는 게이트와 소오스/드레인 사이의 오우버랩 캐패시턴스가 감소되는 효과가 발생하며, 둘째 제2다결정실리콘층의 식각 종료점을 감지하는 방법을 통해 제1다결정실리콘층의 식각량을 조절함으로써, 그 제1다결정실리콘층의 식각량을 정확히 조절할 수 있는 효과와 함께 저농도 소오스/드레인 영역의 윤곽을 정확히 조절할 수 있는 효과가 발생하고, 셋째 게이트로 형성되는 얇은 제1다결정실리콘층과 그 아래의 게이트산화막이 각각 저농도 이온이 통과하지 않은 박막으로 형성됨으로써, 이온주입공정으로 인한 게이트산화막의 특성 열화를 방지하는 효과가 발생한다.As described above, the manufacturing method and the third (a) of the offset LED display having the inverse ('T) -shaped gate of the present invention (I) composed of the processes of FIGS. 2 (a) to 2 (g) In the method of manufacturing the offset LED structure having the inverted-'T 'gate of the present invention (II) composed of the processes of FIGS. 3 to 3 (g), first, the source / drain region of the LDD structure is inverted-'T' structure. The degree of overlap with the gate is larger than that of the conventional MOSFET and smaller than that of the conventional ITLDD MOSFET shown in FIG. 1, which not only improves the hot carrier characteristics but also improves the gate movement of the gate. The ability to improve the performance occurs, compared to the conventional ITLDD MOSFET, the effect of the overlap capacitance between the gate and the source / drain is reduced, and secondly through the method of detecting the etching end point of the second polycrystalline silicon layer By controlling the etching amount of the first polysilicon layer, the etching amount of the first polysilicon layer can be precisely adjusted, and the contour of the low concentration source / drain region can be precisely formed, and the third gate is formed. The thin first polysilicon layer and the gate oxide film under the thin film are formed as thin films in which low concentration ions do not pass, thereby preventing the deterioration of characteristics of the gate oxide film due to the ion implantation process.
Claims (12)
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