KR0166800B1 - Process of fabricating cmos - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a CMOS device, wherein the ion implantation process is performed to prevent threshold voltages, punch-through and latch-up characteristics, and to perform field channel stops to improve insulation between devices. By doing this at once, the ion implantation process is simplified to be suitable for CMOS fabrication.

CMOS device manufacturing method according to the invention comprises the steps of preparing a substrate; Forming a first insulating film and a second insulating film on the substrate; Selectively removing the second insulating film so that a portion of the first insulating film is exposed; Forming a first conductivity type well by ion implanting a first conductivity type impurity into the substrate under the exposed first insulating layer; Forming a first field oxide film on the exposed first insulating film; Removing the second insulating film to implant a second conductive impurity ion to form a second conductive well on a substrate under the first insulating film; Removing the first field oxide film and the first insulating film, and forming a second field oxide film to protrude on the substrate between the boundary of the first conductive well and the second conductive well; Forming a gate oxide film on the first conductive well and the second conductive well including the protruding second field oxide film; Forming a first conductive layer on the gate insulating film on the second conductive well, and forming a second conductive layer on the gate insulating film on the first conductive well; Ion implanting a second conductivity type impurity into the second conductivity type well using the second field oxide film formed on the first conductivity layer and the second conductivity type well as a mask; Implanting a first conductivity type impurity into the first conductivity type well using the second conductivity layer and the second field oxide film formed on the first conductivity type well as a mask; Implanting a first conductivity type impurity into the second conductivity type well using the first conductive layer as a mask; And ion implanting a second conductivity type impurity into the first conductivity type well using the second conductivity layer as a mask.

Description

Manufacturing method of CMOS device

1 is a schematic diagram illustrating a punchthrough phenomenon in a typical MOSFET.

2a to 2p are process cross-sectional views of a conventional CMOS device.

3A to 3M are cross-sectional views of a CMOS device according to the present invention.

4 is a cross-sectional view of a CMOS device according to the present invention.

5a to 5c are doping profiles of major cross-sections of the CMOS device of FIG.

* Explanation of symbols for main parts of the drawings

41: silicon substrate 42: first silicon oxide film

43: first silicon nitride film 44: first photosensitive film

45,45a: n-type well 46: temporary field oxide film

47,47a: P type well 48: second silicon oxide film

49: second silicon nitride film 50: second field oxide film

51 gate oxide film 52a second conductivity type gate electrode

53a: second capgate insulating film 54a: first conductivity type gate electrode

55a: first capgate insulating film 56: second photosensitive film

57: second channel stop layer 58: third photosensitive film

59: first channel stop layer 60: fourth photosensitive film

61: first conductivity type LDD region 62: first sidewall

63: first conductivity type impurity region 64: fifth photosensitive film

65: second conductivity type LDD region 66: second side wall

67: second conductivity type impurity region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a CMOS device, which simplifies an ion implantation process.

In general, in manufacturing a semiconductor device, various problems arise as the semiconductor CMOS device is scaled down.

Representative problems include punch-through between source / drain in short channel MOSFETs, latch-up in CMOS circuits, and punch-through between devices. ), An insulation deterioration phenomenon due to

In particular, among these problems, the punch-through phenomenon in the conventional MOSFET is, when the voltage is gradually increased after applying the voltage between the source 4 and the drain 5, as shown in FIG. ), The area of the depletion regions 6 and 7 on the well side increases in the junction between the drain 5 and the well.

In particular, the delay without voltage effect from the gate 3 to the substrate 1 and the increase in depletion at the corner of the source / drain junction where the electric field is concentrated are maximized.

If the depletion regions of the source 4 and the drain 5 meet each other, the carrier moves rapidly from the source 4 toward the drain 5 through the depletion layer 6, 7. Done.

At this time, the punch-through phenomenon of the MOSFET occurs within the operating voltage, so that the MOSFET does not operate normally.

Only the above-mentioned problems, including the punch-through phenomenon, must be solved in order to successfully achieve high scale down of the semiconductor device. In order to solve the above problems, in order to improve the punch through characteristics of the short channel MOSFET, the punch through stop ion injection into the semiconductor substrate before the gate electrode is formed. Retrograde well doping by high energy ion implantation is performed in order to perform ion implantation or to improve the problem of latch-up in CMOS circuits.

In addition, field channel stop doping is performed before field oxide is formed to improve insulation characteristics.

These techniques require a lot of tread-off in manufacturing CMOS integrated circuits.

In other words, complicated process steps and many ion implantation processes are required, and the process cost increases due to these processes, and the characteristics of the MOSFET due to the increase in the channel region concentration due to punch through doping, The field transistor channel stop doping is carried out before the formation of the field oxide layer to reduce the mobility of the carrier, decrease the operating speed due to the increase of the junction capacitance, and improve the insulation characteristics. As a result, problems such as a decrease in the driving current of the transistor and an increase in the threshold voltage of the transistor may occur, including a decrease in the width of the active region due to dopant encroachment from the field region to the active region.

Therefore, a lot of effort is required to solve the problem of the increase in the process cost due to the scale-down of the semiconductor device and the degradation of the above-mentioned device characteristics.

Referring to the accompanying drawings, a conventional CMOS device manufacturing method in this respect is as follows.

In the conventional method of manufacturing a CMOS device, first, as shown in FIG. 2A, a silicon substrate 11 is prepared, and SiO ₂ is deposited on the silicon substrate 11 by chemical vapor deposition (CVD), sputtering, and plasma CVD. The silicon oxide film 12 is formed by depositing to a thickness of about 100 GPa using one of the methods described above.

Subsequently, Si ₃ N ₄ is deposited on the silicon oxide film 12 by LPCVD to form a silicon nitride film 13, and a first photosensitive film (not shown) 14 is coated on the silicon nitride film 13. .

Subsequently, as shown in FIG. 2B, the first photosensitive film 14 is selectively removed by an exposure and developing process to define an n-type well forming portion.

Then, the silicon nitride film 13 is selectively removed by photolithography and etching with the first photoresist film 14a remaining after the removal.

Subsequently, any one of P and As is ion-implanted on the exposed surface of the silicon oxide film 12, that is, the n-type well forming portion, using the first photosensitive film 14a as a mask to form the n-type well 15.

Then, as shown in FIG. 2C, the first photosensitive film 14a is removed, and the exposed surface of the silicon oxide film 12 is heat-treated for about 3 hours in an H ₂ / O ₂ atmosphere at a temperature of about 1000 ° C. Thus, the temporary field oxide film 16a is grown on the exposed surface of the silicon oxide film 12.

Subsequently, the silicon nitride film 13a is removed, and B ⁺ ions are implanted into the exposed surface of the field oxide film 16 except for the n-type well 15a to form the P-type well 17.

Next, as shown in FIG. 2D, the silicon nitride film 12a except for the field oxide film 16 is drive-in for about 4 hours in a nitrogen (N2) atmosphere at a temperature of about 1000 ° C. To grow the P-type well 17.

Subsequently, the field oxide film 16 is etched back so that only the thickness of the silicon oxide film 12a is left to form an oxide film 18, and a photosensitive film 19 is applied on the oxide film 18.

Next, as shown in FIG. 2E, a portion of the second photoresist film 19 positioned above the P-type well 17a is selectively removed by an exposure and development process to define a field channel stop ion implantation region.

Subsequently, B ⁺ impurities are implanted into the P-type well to form the first channel stop ion layer 20 using the selectively removed and remaining second photoresist film 19a as a mask to perform field channel stop ion implantation 17a. do.

Then, as shown in FIG. 2F, the second photosensitive film 19a is removed, and a third photosensitive film 21 is applied on the exposed surface of the gate insulating film 18, although not shown in the drawing. A field channel stop ion implantation region is defined by selectively removing a portion of the third photoresist film 21 disposed above the n-type well 15a by an exposure and development process.

Subsequently, the second channel stop ion layer 22 is formed by ion-implanting phosphorus (P) impurities into the n-type well 17a using the second photoresist film 21a that is selectively removed.

In this case, the second channel stop ion layer 22 is in contact with the first channel stop ion layer 20.

In this case, the second channel stop ion layer 22 is in contact with the first channel stop ion layer 20.

Then, as shown in FIG. 2G, the third photoresist film 21a is removed, a fourth photoresist film 23 (not shown) is applied on the gate oxide film 18, and the exposure and development processes are performed. The fourth photosensitive film 23 (not shown) is selectively removed to define a field oxide film forming portion.

Subsequently, the field oxide film forming portion is heat-treated in an H ₂ / O ₂ atmosphere at a temperature of about 1000 ° C. for about 3 hours to form a field oxide film 24 on the gate oxide film 18a in a thickness of about 5000 ° C.

Then, as shown in FIG. 2h, the fourth photosensitive film 23 is removed, and then the fifth photosensitive film 25 is applied on the exposed surfaces of the field oxide film 24 and the gate oxide film 18a, and the exposure and Only a portion of the fifth photosensitive film 25 positioned above the P-type well 17a is selectively removed by the developing process.

Subsequently, BF ₂ is ion-implanted into the P-type well 17a using the selectively removed and remaining fifth photoresist film 25a as a mask to adjust a threshold voltage.

Then, as shown in FIG. 2i, the fifth photosensitive film 25 is removed, and then the sixth photosensitive film 26 is applied on the exposed surfaces of the field oxide film 24 and the gate oxide film 18a, and then exposed and developed. By the process, a portion of the sixth photosensitive film 26 located above the n-type well 15a is selectively removed.

Subsequently, BF ₂ is ion-implanted into the n-type well 15a using the remaining sixth photosensitive film 26a as a mask to adjust the threshold voltage.

Then claim 2j also the, the sixth removing the photoresist layer (26a) and then the field oxide film 24 and the and on the exposed surface of n ⁺ polycrystalline silicon layer 27 of the silicon oxide film (18a) as shown in n ⁺ An oxide film 28 is deposited on the polycrystalline silicon layer 27, respectively.

Subsequently, as illustrated in FIG. 2K, the n ⁺ polycrystalline silicon layer 27 and the first oxide layer 28 are selectively removed by photolithography and etching to form the first conductivity type gate electrode 27a. ) And a first cap gate oxide film 28a are formed.

Next, as shown in FIG. 2L, a field oxide film on the P-type well 17a except for the n-type well 15a where the first conductive gate electrode 27a and the cap gate oxide film 28a are formed. A second oxide film 30 is deposited on the P ⁺ polycrystalline silicon layer 29 and the P ⁺ polycrystalline silicon layer 29 on the exposed surface of the 24 and the gate oxide film 18.

Subsequently, as shown in FIG. 2M, the P polycrystalline silicon layer 29 and the second oxide film 30 are selectively removed by photolithography and etching to remove the second conductive gate electrode 29a and the second conductive gate electrode 29a. The two capgate oxide film 30a is formed.

Next, as shown in FIG. 2n, the upper second capgate oxide layer 30a and the second conductivity type gate electrode 29a and the field oxide layer 24 and the gate oxide layer positioned on the P-type well 17a are shown in FIG. The seventh photosensitive film 31 is applied on the exposed surface of the part (18a).

Subsequently, the seventh photosensitive film 31 ion-implants boron into the n-type well 15a in the silicon substrate 11 on both sides of the capgate oxide film 28a using the first capgate oxide film 28a as a mask. Second conductivity type impurity regions 32a and 32b are formed, respectively.

Next, as shown in FIG. 2O, after the seventh photoresist layer 31 is removed, the first cap gate oxide layer 28a, the first gate electrode 27, and the field oxide layer positioned on the n-type well 15a are removed. An eighth photosensitive film 33 is applied on the exposed surface of the 24 and the gate oxide film 18a.

Subsequently, P ⁺ ions are implanted into the P-type well 17a into the silicon substrate 11 by using the eighth photosensitive film 33 and the second capgate oxide film 28a as a mask to form the first conductivity type impurity region 34a ( 34b).

Then, as shown in FIG. 2p, by removing the eighth photosensitive film 33, the production of the C-type morph transistor composed of the n-type morph transistor and the P-type morph transistor is completed.

As described above, the conventional method of manufacturing a CMOS device has the following problems.

First, in the conventional method of manufacturing a semiconductor device, a punch through stop ion for preventing an increase in the well concentration or a punch-through phenomenon for improving the punch-through phenomenon of the device due to scale down. Implantation Increasing the concentration of the MOSFET channel region during the doping process lowers the MOSFET operation speed, mobility, and junction capacitance.

Second, in the conventional method of manufacturing a semiconductor device, the active region area is reduced during the channel stop doping process performed before the formation of the field oxide layer 15 between the active region and the active region of the MOSFET. Is reduced.

Third, in the conventional method of manufacturing a semiconductor device, a punch through stop ion implantation process, a field channel stop implantation process, and a MOSFET threshold voltage of an active device The cost of the product is increased because complex ion implantation processes such as control ion implantation processes and retrograde implantation processes to improve latch up are required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and includes an ion for improving punch through of a CMOS device, a latch voltage control latch characteristic, and field channel stop doping. It is an object of the present invention to provide a CMOS device manufacturing method that simplifies the implantation process.

The present invention for achieving the above object comprises the steps of preparing a substrate; Forming a first insulating film and a second insulating film on the substrate; Selectively removing the second insulating film so that a portion of the first insulating film is exposed; Forming a first conductivity type well by ion implanting a first conductivity type impurity into the substrate under the exposed first insulating layer; Forming a first field oxide film on the exposed first insulating film; Removing the second insulating film to implant a second conductive impurity ion to form a second conductive well on a substrate under the first insulating film; Removing the first field oxide film and the first insulating film, and forming a second field oxide film to protrude on the substrate between the boundary of the first conductive well and the second conductive well; Forming a gate oxide film on the first conductive well and the second conductive well including the protruding second field oxide film; Forming a first conductive layer on the gate insulating film on the second conductive well, and forming a second conductive layer on the gate insulating film on the first conductive well; Ion implanting a second conductivity type impurity into the second conductivity type well using the second field oxide film formed on the first conductivity layer and the second conductivity type well as a mask; Implanting a first conductivity type impurity into the first conductivity type well using the second conductivity layer and the second field oxide film formed on the first conductivity type well as a mask; Implanting a first conductivity type impurity into the second conductivity type well using the first conductive layer as a mask; And ion implanting a second conductivity type impurity into the first conductivity type well using the second conductivity layer as a mask.

A method of manufacturing a CMOS device according to the present invention will be described in detail with reference to the accompanying drawings.

3a to 3m are manufacturing process diagrams of the CMOS device according to the present invention.

In the method of manufacturing a CMOS device according to the present invention, first, as shown in FIG. 3A, a silicon substrate 41 is prepared, and SiO ₂ is deposited on the silicon substrate 41 by chemical vapor deposition (CVD) or sputtering. , By using any one of plasma CVD, to form a first silicon oxide film 42 by deposition to a thickness of about 100 kHz.

Next, Si ₃ N ₄ is deposited on the first silicon oxide film 42 by about 500 kV by LPCVD to form a first silicon nitride film 43, and the first photoresist film 44 is deposited on the silicon nitride film 43. Apply.

Subsequently, as shown in FIG. 3B, the first photosensitive film 44 is selectively removed by an exposure and development process to define an n-type well forming portion.

Thereafter, the first silicon nitride layer 43 is selectively removed by photolithography and etching using the first photoresist layer 44a remaining after the selectively removal.

Subsequently, any one of P and As is implanted on the exposed surface of the first silicon oxide film 42, that is, the n-type well forming portion, using the first photosensitive film 44a as a mask, and ion implantation energy of about 120 KeV and about 1.0 × 10. N-type wells 45 are formed by ion implantation with ¹³ / cm 2 dose.

Next, as shown in FIG. 3C, the first photoresist film 44 is removed and the exposed surface of the first silicon oxide film 42 is exposed for about 3 hours in an H ₂ / O ₂ atmosphere at a temperature of about 1000 ° C. The heat treatment is performed to form a temporary field oxide film 46 on the exposed surface of the first silicon oxide film 42.

In addition, the n-type well 45a is grown in the silicon substrate 41 under the field oxide film 46 together with the formation of the temporary field oxide film 46 during the heat treatment process.

Subsequently, the silicon nitride film 43a is removed and B ⁺ ions are implanted into the exposed surface of the first silicon oxide film 42 except for the temporary field oxide film 46, and the ion implantation energy of about 50 KeV and 50 x 10 P-type wells 47 are formed by ion implantation with ¹² / cm 2 dose.

Then, as shown in FIG. 3D, the portion of the first silicon oxide layer 42 except for the portion of the temporary field oxide layer 46 is driven in for about 4 hours in an atmosphere of nitrogen (N ₂ ) at a temperature of about 1000 ° C. drive-in to grow the P-type well 47a into the silicon substrate 41.

Subsequently, although not shown in the drawing, the first silicon oxide film 42 and the temporary field oxide film 46 are immersed in an HF solution to completely remove them, and the first silicon oxide film 42 and the temporary field oxide film 46 are removed. The second silicon oxide film 48 is grown to a thickness of about 100 microseconds in the silicon substrate 41 of the n-type well 45a and P-type well 47a exposed by the removal of.

Then, a silicon nitride film 49 is deposited to a thickness of about 1400 Å on the silicon oxide film 48 by LPCVD, and a field oxide film in the second silicon nitride film 49 is formed by photolithography and etching. Optionally remove the part.

Subsequently, the exposed surface of the second silicon oxide film 48, that is, the portion where the field oxide film is to be formed, is heat-treated under an H ₂ / O ₂ atmosphere at a temperature of about 1000 ° C., and then on the exposed surface of the second silicon oxide film 48. The second field oxide film 50 is grown to about 500 mm thick.

Then, as shown in FIG. 3f, the second silicon nitride film 49 is removed by dipping in phosphate solution (H ₃ PO ₄ ), and the second silicon oxide film 48 underneath is fluorinated. Remove by dipping in hydrogen (HF) solution.

Subsequently, as shown in FIG. 3G, the gate oxide film 51 is grown to a thickness of about 100 kHz by a thermal oxidation process on the exposed surface of the silicon substrate 41 including the second field oxide film 50.

Next, although not shown in the figure, a photoresist (not shown) is applied over the P-type well 47a, and then a polycrystal doped with P-type impurities is formed on the gate oxide film 51 above the n-type well 45a. Silicon layer (not shown) 52 and oxide film (not shown) 53 are deposited, and the polycrystalline silicon layer 52 and oxide film 53 are selectively removed by photolithography and etching. The conductive gate electrode 52a and the second cap gate insulating film 53a are formed, respectively.

Subsequently, although not shown in the drawing, the photoresist film is removed, and then a photoresist film (not shown) is applied on the n-type well 45a, and an n-type impurity is formed on the gate oxide film 51 on the P-type well 47a. A doped polycrystalline silicon layer (not shown) 54 and an oxide film (not shown) 55 are deposited on the polycrystalline silicon layer 54, respectively, and the polycrystalline silicon layer 54 is formed by photolithography and etching. And the oxide film 55 are selectively removed to form a first conductive gate electrode 54a and a first cap gate insulating film 55a, respectively.

In this case, one of the metal materials aluminum (Al), chromium (Cr), and tungsten (W) other than the polycrystalline silicon may be selectively used as the first and second conductivity type gate electrodes 52a and 54a. .

Subsequently, as shown in FIG. 3h, the n-type well 45a on the exposed surface of the gate oxide film 51, the second conductive gate electrode 52a, and the second capgate insulating film 53a and the n A second photosensitive film 56 is coated on the second field oxide film 50 formed on the well 45a, and the first capgate insulating film 55a is formed on the P-type well 47a together with the second photosensitive film 56. Is used to implant the boron (B ⁺ ) impurity at about 150 KeV and about 3.5 × 10 ¹² / cm 2 dose to the silicon substrate 41 on both sides of the first capgate insulating layer 55a. Second channel stop layers 57 are formed in the mold well 47a.

Next, as shown in FIG. 3I, the second photoresist layer 56 is removed, and the gate oxide layer 51, the first conductivity type gate electrode 54a, and the first cap on the P-type well 47a are removed. A third photosensitive film 58 is coated on the exposed surface of the gate insulating film 55a and on the second field oxide film 50 formed on the p-type well 47a.

Subsequently, an n-type impurity is formed on the silicon substrate 41 on both sides of the second capgate insulating layer 53a using the second capgate insulating layer 53a on the n-type well 45a together with the third photoresist layer 58. Is implanted with an ion implantation energy of about 170 KeV and a dose of about 3.0 × 10 ¹² cm 2 to form first channel stop layers 59 in the n-type well 45a.

At this time, the ion implantation process for adjusting the threshold voltage of the device, the ion implantation process for improving the punch-through and latch-up characteristics of the device, and the field channel for improving the insulation between the device and the device The stop ion implantation process is performed by one ion implantation process.

Subsequently, as shown in FIG. 3j, the third photosensitive film 58 is removed, and as shown in FIG. 3k, the gate oxide film 51 and the second conductive gate on the n-type well 45a are shown. A fourth photosensitive film 60 is coated on the exposed surface of the electrode 52a and the second capgate insulating film 53a and a portion of the second field oxide film 50, and on both sides of the first capgate insulating film 55a. An n-type impurity is ion-implanted into the silicon substrate 41 on the P-type well 47a to form the first conductivity type LDD region 61.

Next, first sidewalls (side spacers) 62 are formed on both sides of the first capgate insulating layer 55a and the first conductive gate electrode 54a, and the fourth photoresist layer together with the first sidewall 62. The first conductivity type impurity region 63 is formed by ion implanting n ⁺ type impurities into the n type well 45a on both sides of the first sidewall 62 using the mask 60 as the mask.

Subsequently, as shown in FIG. 3L, the fourth photoresist layer 60 is removed, and the gate oxide layer 51, the first conductive gate electrode 54a, and the first cap gate insulating layer are formed on the P-type well 47a. A fifth photosensitive film 64 is coated on the exposed surface of 55a and a portion of the second field oxide film 50, and the second capgate insulating film 53a including the fifth photosensitive film 64 is used as a mask. P-type impurities are ion-implanted into the silicon substrate 41 on the n-type well 45a on both sides of the second capgate insulating film 53a to form the second conductivity type LDD region 65.

Next, second sidewalls 66 are formed on both sides of the second capgate insulating layer 53a and the second conductive gate electrode 52a, and the fifth photoresist layer 64 is formed together with the second sidewall 66. The second conductivity type impurity region 67 is formed by implanting P-type impurities into the n-type well 45a on both sides of the second sidewall 66 using a mask.

Subsequently, as shown in FIG. 3M, the manufacturing of the CMOS device is completed by removing the fifth photosensitive film 64.

4 shows the doping profiles of the major cross-sections of a PMOS device in the CMOS device of the present invention.

FIG. 5A is a doping profile diagram along the IVa-IVa line of FIG. 4, showing punch-through prevention by high doping.

FIG. 5B is a doping profile diagram along the IVb-IVb line of FIG. 4, and it can be seen that the threshold voltage can be controlled by high doping of the surface.

FIG. 5C is a doping profile diagram along the IVc-IVc line of FIG. 4, and it can be seen that the field transistor channel stop can be easily performed.

On the other hand, in the n-channel MOSFET region, only the impurity form is changed from the P-type to the N-type, and the doping profiles of the main cross-sections have a dopant profile that is aborted with the P-type MOSFET as shown in FIGS. 5A to 5C.

As described above, the method of manufacturing a CMOS device according to the present invention has the following effects.

First, in the method of manufacturing a CMOS device according to the present invention, the ion implantation process can be reduced by performing the threshold voltage, punch through stop, and field channel stop ion implantation in a single process during the ion implantation process.

Second, in the method of manufacturing a CMOS device according to the present invention, since ion implantation for punch-through stop of the active device is performed only in the source and drain regions, not in the step of increasing the well concentration or forming the entire surface, the channel region of the CMOS is highly concentrated. As a result, problems such as reduced operation speed, reduced mobility, and increased junction capacitance can be solved.

Third, in the method of manufacturing a CMOS device according to the present invention, in the case of the surface channel PMOS of a P ⁺ polysilicon gate, CMOS generated by passing through the gate oxide of boron from the gate and automatically doping to the channel. Since the threshold voltage can be controlled by controlling the threshold voltage by implanting phosphoric acid through the gate electrode after the gate electrode is formed, the threshold voltage of the CMOS can be prevented.

Meanwhile, the high energy retrograde doping of the conventional well region improves the latch up characteristics of the CMOS.

In addition, since the characteristics of the device can be improved by selectively doping unnecessary parts without increasing the concentration of the entire well, it is possible to solve the body effect problem due to the increase of the well concentration.

Claims (2)

Preparing a substrate; Forming a first insulating film and a second insulating film on the substrate; Selectively removing the second insulating film so that a portion of the first insulating film is exposed; Forming a first conductivity type well by ion implanting a first conductivity type impurity into the substrate under the exposed first insulating layer; Forming a first field oxide film on the exposed first insulating film; Removing the second insulating film to implant a second conductive impurity ion to form a second conductive well on a substrate under the first insulating film; Removing the first field oxide film and the first insulating film, and forming a second field oxide film to protrude on the substrate between the boundary of the first conductive well and the second conductive well; Forming a gate oxide film on the first conductive well and the second conductive well including the protruding second field oxide film; Forming a first conductive layer on the gate insulating film on the second conductive well, and forming a second conductive layer on the gate insulating film on the first conductive well; Ion implanting a second conductivity type impurity into the second conductivity type well using the second field oxide film formed on the first conductivity layer and the second conductivity type well as a mask; Implanting a first conductivity type impurity into the first conductivity type well using the second conductivity layer and the second field oxide film formed on the first conductivity type well as a mask; Implanting a first conductivity type impurity into the second conductivity type well using the first conductive layer as a mask; And implanting a second conductive impurity into the first conductive well using the second conductive layer as a mask. Preparing a substrate; Forming a first insulating film and a second insulating film on the substrate; Selectively removing the second insulating film so that a portion of the first insulating film is exposed; Implanting first impurity ions into the silicon substrate under the exposed first insulating film to form a first conductivity type well; Forming a first field oxide film on the exposed first insulating film; Removing the second insulating film to implant a second conductive impurity ion to form a second conductive well on a silicon substrate under the first insulating film; Removing the first field oxide film and the first insulating film, and forming a second field oxide film to protrude on the substrate between the boundary of the first conductive well and the second conductive well; Forming a gate oxide film on the first conductive well and the second conductive well including the protruding second field oxide film; Forming a first conductive layer on the gate insulating film on the second conductive well, and forming a second conductive layer on the gate insulating film on the first conductive well; Ion implanting a second conductivity type impurity into the second conductivity type well using the second field oxide film formed on the first conductivity layer and the second conductivity type well as a mask; Implanting a first conductivity type impurity into the first conductivity type well using the second field oxide film formed on the second conductivity layer and the first conductivity type well as a mask; Forming first sidewalls on both sides of the first conductive layer and implanting first conductive impurities into the second conductive well; Forming second sidewalls on both sides of the second conductive layer, and ion implanting a second conductivity type impurity into the first conductivity type well.