KR100238861B1 - Semiconductor memory device reduced power consumption - Google Patents

Abstract

1. Technical field to which the invention described in the claims belongs:

2. Technical problem to be solved by the invention: Provides a semiconductor memory device for power reduction.

3. Summary of Solution of the Invention: Having a plurality of memory cell arrays each controlled by a plurality of external byte control pins, the data stored in the memory cells in each memory cell array are provided to the output buffer through an input / output sense amplifier at read time. The semiconductor memory device may include an operation controller configured to generate control signals for activating or deactivating operations of an input / output sense amplifier and an output buffer corresponding to each of the memory cell arrays in response to control data applied to the external byte control pin. As a result, unnecessary consumption of current is suppressed.

4. Important use of invention: It is used as a semiconductor memory device for graphics.

Description

Semiconductor memory device to reduce power consumption

1 is a block diagram of a semiconductor memory device according to the prior art.

2 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

3 is a block diagram of a practical application of a semiconductor memory device having reduced power consumption while interleaving according to an embodiment of the present invention.

4 is an operational timing diagram associated with the apparatus of FIG. 3 performing an interleaved operation.

5A, 5B, and 5C are detailed circuit diagrams of the byte control buffer 150 and a comparison concrete diagram of an input / output sense amplifier enable signal generator.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a synchronous DRAM (SRAM) and the like, and more particularly, to a technology for reducing power consumption in a semiconductor memory device having a structure for controlling a memory cell in bytes.

BACKGROUND ART A semiconductor memory device that can be used as a graphic buffer memory generally uses an internal memory cell divided by a data output unit, and an external DQ can be controlled in units of bytes. Such a control method may be regarded as a structure necessary to actually perform a function as a graphic buffer.

FIG. 1 is a block diagram of a semiconductor memory device according to the prior art, and only a scheme related to a read operation in which data stored in the memory cell array 10 is output through the output buffer 13 is shown. In FIG. 1, in order to read data stored in a specific memory cell in the memory cell array 10, a row address is provided while a row address strobe bar (hereinafter referred to as "RASB") signal is activated. Should be done. By the above operation, a memory cell in a row direction is selected among a plurality of cells located in the memory cell array 10. In addition, when a column address is provided while a column address strobe (CASB) signal is activated, the memory cells in the column direction are selected through the corresponding column select line (CSL). do.

When one memory cell is selected by providing the row address and column address, a charge sharing operation occurs between an I / O line (input / output line) and a storage capacitor that stores cell data. Accordingly, the data stored in the selected memory cell is amplified by the bit line sense amplifier in the memory cell array 10 and then transferred to the I / O line. The I / O S / A (Input / Output Sens Amplifier) 12 amplifies the level of data provided to the I / O line again and provides it to the output buffer 13. The output buffer 13 converts the data output from the I / O S / A 12 to a level suitable for an external environment and outputs it to the outside. Through the above process, the cell data stored in the selected memory cell in the memory cell array 10 is output to the outside. Here, the I / OS / A 12 of FIG. 1 performs sensing and amplification operations under the control of the ATD circuit 14 generating an address transition signal ATS in response to the column address detection. Is performed. Further, the operation of the output buffer 13 for outputting data is initiated by the output signal PIBE of the byte control buffer 15. Since the byte control buffer 15 depends on the byte enable signal BE, the output buffer 13 is in the same way as being enabled by the byte enable signal BE.

Accordingly, even if the byte enable signal BE, that is, the byte pin data is deactivated, the I / O S / A 12 is enabled by the ATS signal, regardless of this, and starts its own operation. As such, it is not desirable to start the operation of the I / O S / A 12 under an unnecessary state other than the actual read operation. That is, activation of unnecessary operation of the I / O S / A 12 involves current consumption, which leads to an increase in power consumption. It is known that the current consumption of the input / output sense amplifier in the memory device occupies a greater proportion than the current consumed by other circuits in the semiconductor memory device. In addition, the current consumption of the I / O S / A 12 also acts as a noise source (Noise Source) to interfere with the stable operation of the memory device.

Accordingly, an object of the present invention is to provide a semiconductor memory device that can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a semiconductor memory device for reducing power consumption.

It is still another object of the present invention to provide a semiconductor memory device capable of eliminating waste of power by blocking an operation of an input / output sense amplifier when a semiconductor memory device does not perform an actual read operation.

According to the present invention for achieving the above object, has a plurality of memory cell arrays each controlled by a plurality of external byte control pin in a block unit structure capable of interleaving operation, the data stored in the memory cells in each memory cell array A semiconductor memory device which is provided to an output buffer via an input / output sense amplifier in read in an interleaved manner; And a byte control buffer for generating control signals for simultaneously activating or deactivating operations of an input / output sense amplifier and an output buffer corresponding to each memory cell array in response to control data applied through the external byte control pin. It is done.

Hereinafter, a structure of a semiconductor memory device and a driving control method thereof according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings. Like reference numerals in the accompanying drawings indicate elements having the same configuration and function as much as possible. In the following description, the detailed items for such configurations are described in detail in order to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In addition, features and functions of well-known semiconductor basic devices are not described in detail in order not to obscure the present invention.

First, the basic technical idea of the present invention is to reduce power consumption in a semiconductor memory device having a structure in which a memory cell is controlled in units of bytes, that is, a block unit structure capable of interleaving operation among semiconductor memory devices such as a synchronous DRAM. To this end, the operation of the input / output sense amplifier and the output buffer corresponding to each memory cell array is simultaneously activated or deactivated, thereby eliminating the current consumption of the sense amplifier when the semiconductor memory device does not perform an actual read operation. An operation control unit for generating control signals for activating or deactivating operations of an input / output sense amplifier and an output buffer corresponding to each memory cell array at about the same time is shown as a byte control buffer 150 in FIG.

Referring to FIG. 2, the control data BE received through the external byte control pin is applied to the byte control buffer 150. The byte control buffer 150 outputs the data output buffer control signal PIBE_DO activated on line L2 in response to the input of the control data BE and simultaneously outputs the sense amplifier control signal PIBE_IOSA activated on line L3. More precisely, the sense amplifier control signal PIBE_IOSA output to the line L3 is output a little faster than the data output buffer control signal PIBE_DO output to the line L2.

Accordingly, since the I / O S / A 120 and the output buffer 13 are simultaneously activated or deactivated by the activated signals, current consumption due to unnecessary operation of the sense amplifier is not generated.

5A is a detailed circuit diagram of an example of the byte control buffer 150. Referring to FIG. 5A, the byte control buffer 150 includes a plurality of PMOS transistors P1 to P3, a plurality of N-type transistors N1 to N3, a plurality of inverters I1 to I10, and a plurality of transfer gates PG1 to PG3. It can be seen.

FIG. 3 is a block diagram of a semiconductor memory device of practical application having intermittent operation and reduced power consumption according to an embodiment of the present invention. Also shown in FIG. 4 is an operation timing diagram associated with the apparatus of FIG. 3 performing an interleaving operation.

Referring to FIG. 3, when the semiconductor memory device is operated by being divided into memory cell array units, such as the first and second blocks BL1 and BL2, control data received through an external byte control pin for byte-by-byte control. BE is provided in an interleave manner. Here, the interleaving method is preferable in the case where data is read by alternately enabling or disabling two memory block groups. The application of the interleaving method is that the semiconductor memory device is capable of responding to two bytes, and each memory cell array is connected to a data path (I / OS / A to data output buffer) controlled by each byte pin. Applies to In FIG. 3, the A-byte memory cell arrays 10A and 10C in different block groups are activated or deactivated together by the signal BE-A.

Referring to the timing diagram of FIG. 4, in the section T1, the sense amplifiers 150A and 150C corresponding to the A-byte memory cell array are enabled together with the output buffers corresponding thereto, and the sense amplifiers 150B and 150D corresponding to the B-byte memory cell array. Is disabled with the corresponding output buffer. In the period T2, sense amplifiers 150A and 150C corresponding to the A-byte memory cell array are disabled, and sense amplifiers 150B and 150D corresponding to the B-byte memory cell array are enabled. In the case of the semiconductor memory device using the interleaving method as illustrated in FIG. 3, the byte control buffer 150 may be configured to output an input / output sense amplifier and an output buffer corresponding to each memory cell array in response to control data applied to the external byte control pin. By simultaneously activating or deactivating the operation, unnecessary sense amplifiers are not operated. In this case, the power saving effect is doubled.

Meanwhile, the byte control signal BE provided in the semiconductor memory device uses a method of allowing external pin data to be transferred to the inside when a column address strobe bar (CASB) is activated. The reason is to use EDO mode (Extended Data Output mode) for the high speed operation of the memory device.In order to prevent the data output from transitioning to the "high impedance" state when CASB is disabled, byte pin data is stored in the CASB disabled area. Because it should be blocked from passing to.

In implementing the present invention, the byte control signal BE for controlling the data output cannot be used in the I / O sense amplifier as it is, so that block 155 of FIG. 5a is required. Referring to the timing diagram of FIG. 4, the data output buffer control signal PIBE_DO_j (where j is A or B) is changed to the address because the activation or deactivation is determined by the CASB signal after the column address transitions and the ATS pulse signal is generated. It can be seen that the speed by the byte signal is slower than the speed by. Therefore, in order to prevent a decrease in speed, the byte pin data is transferred from the inactivation region of the CASB to the inside, and the I / O sense amplifier is controlled by generating an internal byte signal that latches when the CASB is activated. Therefore, it is possible to prevent a decrease in speed due to an external byte control signal.

In FIG. 5A, the sense amplifier control signal PIBE_IOSA output from the inverter I10 is provided as an input of one side of the NAND gate C1 of FIG. 5C to enable the I / O S / A 120. This is distinguished from the conventional logic shown in FIG. 5B, that is, the difference between the conventional logic and the logic of the embodiment of the present invention is the sense amplifier control signal PIBE_IOSA. The signal PIYED is a signal excited by the RASB. More specifically, the signal PIYED is a signal for operating the I / O S / A 120 after the row address is determined by the RASB.

The embodiments of the present invention described above have been described and limited by way of example with reference to the drawings, but the same may be variously changed and modified without departing from the technical spirit of the present invention for those skilled in the art. Will be obvious. For example, it will be apparent that the structure of the logic of FIG. 5 can be changed or changed as far as the matter allows.

According to the present invention described above, when the semiconductor memory device does not perform the actual read operation, the unnecessary operation of the input / output sense amplifier is blocked, thereby eliminating unnecessary waste of power.

Claims (3)

A semiconductor memory device having a plurality of memory blocks each having a plurality of byte memory cell arrays each controlled in an interleaved mode by a byte control signal input to a plurality of external byte control pins, thereby reducing power consumption. An input / output sense amplifier corresponding to the array and sensing and amplifying data output from the memory cell array in the memory block in response to activation of the sense amplifier control signal, and corresponding to the memory cell array, respectively. Each memory cell according to a data output buffer for buffering and outputting data output from the input / output sense amplifier in response to activation, a byte control signal input through the external byte control pin, and a column address strobe signal input from the outside; Array And a byte control buffer which simultaneously activates or deactivates a sense amplifier control signal and a data output buffer control signal supplied to the input / output sense amplifier and the data output buffer corresponding to the semiconductor memory device. The semiconductor memory device of claim 1, wherein the data output buffer control signal is generated only when the column address strobe signal is activated. The semiconductor memory device of claim 1, wherein the sense amplifier control signal is generated when the column address strobe signal is inactive.