KR0157291B1 - Current sensing circuit of semiconductor memory device that has current sense amplifier - Google Patents

Abstract

[Technical field to which the invention described in the claims belongs]

The present invention relates to a current sensing circuit of a semiconductor memory device.

[Technical Challenges to Invent]

The present invention provides a current sensing circuit capable of selecting an optimal load transistor according to various operation modes by arranging a plurality of load transistors of different sizes in different positions in an input / output line pair when using a current sense amplifier.

[Summary of the solution of the invention]

A current of a semiconductor memory device having a plurality of memory arrays, a plurality of input / output line pairs carrying read data, and a sensing structure for detecting the loaded data and changing the current difference between the input / output line pairs. In the sensing method, when sensing the data read from the memory array and loaded on the input / output line pairs, current sensing is provided by supplying a reference current required for sensing with three or more current sources to each of the selected input / output line pairs. It includes.

[Important Uses of the Invention]

The present invention is suitably used for a semiconductor memory device.

Description

Current Sensing Circuit of Semiconductor Memory Device with Current Sense Amplifier

1 is a block diagram showing the configuration of a current sensing circuit according to the prior art.

2 is a circuit diagram of various signal generation circuits according to the prior art.

3 is an operation timing diagram of a sensing operation through a current sense amplifier according to the prior art.

4 is a block diagram showing a configuration of a current sensing circuit according to the present invention.

5 is an embodiment of the configuration of the current sensing circuit according to the present invention.

6 is another embodiment in the configuration of the current sensing circuit according to the present invention.

7 is a detailed circuit diagram of a control signal generating circuit for selecting a load transistor according to a normal mode and a PBT mode for implementing the embodiments of the present invention of FIG.

8 is a specific circuit diagram of a signal generation circuit for driving the circuit of FIG.

9 is an operation timing diagram of FIG.

10 is an operation timing diagram of FIG.

The present invention relates to a semiconductor memory device, and more particularly, to a current sensing circuit for a current source arrangement in a current sense amplifier.

In general, as the degree of integration of semiconductor memory devices increases and the area of the chip increases, the bussing line loading length becomes longer in the semiconductor memory devices of ultra large scale intergration (ULSI) and RC. Loading is increased. Recently, in the field of memory devices, a method of using a difference in current instead of using a voltage difference of the prior art as a sense amplifier of an input / output line IO in order to solve a decrease in the sensing speed of a data line by loading a busing line. use. In case of using current sense amplifier, it is not necessary to precharge the I / O line IO whenever the column address is changed under condition tAA. Therefore, the speed can be increased, and the layout can be simplified since the input / output line IO can be merged and used. However, when using a current sense amplifier as an input / output line sense amplifier, related variables should be optimized in consideration of speed and stability. On the other hand, when using a current sense amplifier, speed and stability are greatly influenced by the size of a load transistor that supplies current to the input / output line IO. The larger the load transistor is, the faster the speed is and the better the stability is. However, in the parallel bit test PBT (Parallel Bit Test) which operates many input / output line sense amplifiers at the same time, the total current consumed becomes too large. For example, if one current sense amplifier is used and one milliampere (1 mA) is consumed, and 64 current sense amplifiers are operated in the parallel bit test PBT, a total of 64 mA is consumed. On the other hand, if the load transistor is small, the current consumption can be reduced, but the sensing speed is slow and stability is lowered. If the size of the load is moderate, the speed and stability can be satisfactorily satisfied.However, when the column select line CSL is enabled during the low address time tRAC, the I / O line IOs that are already opened are bit. When charge sharing with the bit line BL occurs, the data of the bit line BL may be inverted. 1 is a block diagram showing the configuration of a current sensing circuit according to the prior art. Referring to FIG. 1, the configuration is a low array signal DRA 4 precoded by combining a array array 8 including a plurality of memory cells, an external address signal Ai and a complementary low address strobe signal RASB, and the external address signal. A sense amplifier control circuit for controlling to enable a sense amplifier by inputting the pre-decoded column address signal DCA 5 and the low address signal DRA and the column address signal DCA by combining Ai and the complementary column address strobe signal CASB. 6, a column select enable circuit 7 for generating a column select enable signal for selecting a corresponding column by inputting the low address signal DRA and the column address signal DCA; I / O line pair consisting of I / O line IO and complementary I / O line IOB for inputting and outputting data of A drain is connected to the input / output line IO and a signal PNO is input to the gate to connect the channel-channel MOS transistor 12 for transmitting data of the input / output line IO to an external supply voltage VCC level, and a drain is connected to the complementary input / output line IOB. And a side connected to the P-channel MOS transistor 13 for inputting the signal PNO to the gate, the current sense amplifier 9 for sensing and amplifying current by connecting one side to the input / output line pair, and one side to the current sense amplifier 9 And a data output buffer 11 for outputting the amplified data from the sense amplifier 10 by connecting an input terminal to an output terminal of the sense amplifier 10 for sensing and amplifying the signal.

2 is a circuit diagram of various signal generation circuits according to the prior art. In parallel-bit test PBT mode or normal mode, signal PYE 15 is received and signal PNO 18 goes logic low. Here, the error address signal DRA 14 is a decoded low address signal and generates a signal PYE 15.

3 is an operation timing diagram of a sensing operation through a current sense amplifier according to the prior art. This is a known fact and will not be described. In the prior art, when the current sense amplifier is used as shown in FIG. 1, a pair of load transistors 12 and 13 are used, and their positions and sizes are fixed, thus making it difficult to use them in various operation modes.

Accordingly, an object of the present invention is to provide a current sensing circuit that can select an optimal load transistor according to various operation modes by placing a plurality of load transistors of different sizes in different positions in the input and output line pairs when using a current sense amplifier. Is in.

The technical idea of the present invention for achieving the above objects is a current of the input and output line pairs in a plurality of memory arrays, a plurality of input and output line pairs carrying the read data, and a sensing structure for sensing the loaded data. In a current sensing circuit of a semiconductor memory device having a sensing structure that changes to a difference, when sensing the data read from the memory array and loaded on the input / output line pairs, the current sensing circuits are connected to the selected input / output line pairs respectively and are required for sensing. Three or more current sources for current sensing by supplying a reference current is characterized in that it is provided.

4 is a block diagram showing the configuration of the current sensing circuit according to the present invention. Referring to FIG. 4, unlike the case of FIG. 1, the first rod 19 and the second rod 20 are located in the input / output line pairs IO and IOB, and the appropriate load is applied by the sense amplifier control circuit 6 according to the operation mode. The transistor is selected.

5 is an embodiment of the configuration of the current sensing circuit according to the present invention. Referring to FIG. 5, three pairs of transistors 21, 22, 23, 24, 25, and 26 having different sizes are positioned at two points far from and near the current sense amplifier 9 on the input / output line IO and the complementary input / output line IOB. In terms of the size of the load transistors, the sizes of the transistors 21, 23, and 25 are 5, 20, and 40 mu m, respectively. It is selected by the control clocks PPO_1 27 and PNO_1 28 according to the operation mode for each load transition. In normal mode, the control clock PNO_1 goes logic low and the load transistors 25 and 26 are turned on because the large transistors supply a large amount of current to the input / output line IO so that the column select line CSL transfers to the transfer transistor 40. , When turning on 41, the gap of the input / output line IO is reduced to increase the speed of tAA. In parallel bit test PBT mode, control clock PPO_1 goes logic low to turn on load transistors 21, 22, 23, and 24. Instead of supplying current to smaller transistors 23 and 24, transistors 21 and 22 are near the column select line CSL. It is located at, which prevents I / O line IO from spreading and prevents the speed from slowing down, and reduces the current supplied to the normal mode. The ratio of the current supplied to the load transistor in each mode depends on the size ratio of the load transistor selected in each mode.

6 is another embodiment of the configuration of the current sensing circuit according to the present invention. Referring to FIG. 6, the configuration is largely the same as that of FIG. 5, and only signals for controlling the load transistors are different. When bit line BL and I / O line IO are connected during tRAC, the small load transistors 30 and 31 are disconnected to prevent the I / O line pair, which has a voltage level as a result of charge sharing, from overturning the data of bit line BL. Is to choose. Therefore, in normal operation and parallel bit test mode, the control clock PMO_2 goes logic low to supply current to the I / O line IO and the I / O line IOB. The operations of the control clocks PPO_2 and PNO_2 are the same as the operations of the signals PPO_1 and PNO_1 of FIG. 5, respectively.

FIG. 7 is a detailed circuit diagram of a control signal generation circuit for selecting a load transistor according to a PBT mode in which a normal mode for implementing the embodiments of the present invention of FIG. 5 is implemented. The signal PFTE 42 becomes logic high when the PBT mode is selected. At this time, the control clock PPO_1 44 becomes logic low, the control clock PNO_1 43 becomes logic high, and the signals have the opposite phase in normal operation.

8 is a specific circuit diagram of a signal generation circuit for driving the circuit of FIG. In normal operation, the control clock PMO_2 46 becomes logic low in the PBT mode and the normal mode by receiving the signal PYE as an input for selecting the transistors 30 and 31.

9 is an operation timing diagram of FIG. Referring to FIG. 9, when the complementary low address strobe signal RASB is enabled as a logic low, the column address strobe signal CASB is enabled as a logic low after a predetermined time delay, and is freed by the column address CA among the external address Ai. The decoded column address DCA is output at logic high, and the low address signal DRA pre-decoded by the low address RA among the external addresses Ai is output at logic high, and then the signal PYE is logic high by the low address RA. Controlled by the pre-decoded low address DRA and column address DCA at about the same time, the column select line enable signal CSL goes logic high to select the corresponding column.

FIG. 10 is an operation timing diagram of FIG. 10 is easily understood with reference to FIG. 8 described above.

Therefore, in the present invention, when the current sense amplifier is used, a plurality of load transistors having different sizes are arranged at different positions on the input / output line pairs to select an optimal load transistor according to various operation modes, thereby using the current sense amplifier. There are effects that can be used for various modes of operation.

Although the present invention described above is limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the present invention.

Claims (17)

Current sensing of a semiconductor memory device having a plurality of memory arrays, a plurality of input / output line pairs carrying read data, and a sensing structure for changing the current difference of the input / output line pairs as a sensing structure for sensing the loaded data. In the circuit, when sensing the data read from the memory array array and loaded on the input and output line pairs, three or more plurality for the current sensing by supplying a reference current required for sensing to be connected to the selected input and output line pairs, respectively A current sensing circuit of a semiconductor memory device, characterized by comprising two current sources. 2. The current sensing circuit of a semiconductor memory device according to claim 1, wherein the current source comprises at least one generation of channel-channel transistors for supplying a reference current to the input / output line pairs. It has a plurality of memory arrays and a plurality of input / output line pairs carrying read data, and a sensing structure for sensing the data carried therein and a sensing structure for changing the current difference of the input / output line pairs into a voltage difference. In a current sensing circuit of a semiconductor memory device, each parallel input / output line pair is selected for a parallel bit test to reduce a test time of the memory V data in sensing the data read from the memory V array and loaded on the I / O line. A first means positioned as a current source and positioned at the furthest part of the current sensing structure on the layout to supply current for sensing; and a current located at the closest portion of the current sensing structure on the layout to provide current Second means as the current source for supplying And a third means as the current source for supplying a current for the sensing operation of the data during a normal test. 4. The current sensing circuit of a semiconductor memory device according to claim 3, wherein the current source comprises at least three PMOS transistors for supplying a reference current to the pair of input / output lines. 4. The current sensing circuit of a semiconductor memory device according to claim 3, wherein said first means comprises a channel-channel transistor. 4. The current sensing circuit of a semiconductor memory device according to claim 3, wherein said second means comprises a channel-channel transistor. 4. The current sensing circuit of a semiconductor memory device according to claim 3, wherein said third means comprises a channel-channel transistor. 4. The input / output line of claim 3, wherein the first means is formed of a transistor having a smaller size than the third means and is synchronized with a decoded low address after the complementary low address strobe signal is activated. A current sensing circuit of a semiconductor memory device, characterized in that it is activated by a signal of said parallel bit test used as an input of a circuit for synchronizing a column select line used for loading in a circuit. 4. The method of claim 3, wherein the second means is formed of a transistor having a smaller size than the third means, and after the complementary low address strobe signal is activated, the second means is synchronized with the decoded low address to input and output data of the memory array. A current sensing circuit of a semiconductor memory device, which is activated by a signal used as an input of a circuit for synchronizing a column selection line used for a line and a signal of a parallel bit test to turn on a channel channel transistor. 4. The method of claim 3, wherein the third means is formed of a transistor having a size larger than that of the first means, and the data of the cell array is loaded on a specific input / output line in synchronization with the decoded low address after the low address strobe signal is activated. A current sensing circuit of a semiconductor memory device, which is activated by a signal used as an input of a circuit for synchronizing a column selection line and a signal of a multi-bit test to turn on a PMOS transistor. A semiconductor memory having a plurality of memory arrays and a plurality of input / output line pairs carrying read data thereon, and a sensing structure for sensing the loaded data and a sensing structure for changing a current difference of the input / output line pairs into a voltage difference. In the current sensing circuit of the device, in the parallel bit test for reducing the test time of the data in the memory pin in sensing the data read from the memory array and loaded on the pair of input and output lines, Located as a current source, the first current supply means for supplying a current for sensing the data in the furthest portion of the current sensing structure on the layout, and the closest to the current sensing structure on the layout Second field for supplying current for sensing data The sensing of the data at the time of the supply means, and a normal test current sensing circuit of a semiconductor memory device, characterized in that the sensing operation through the first current supply means and a third current supply means. 12. The current sensing circuit of a semiconductor memory device according to claim 11, wherein said first current supply means comprises a channel-channel transistor. 12. The current sensing circuit of a semiconductor memory device according to claim 11, wherein said second current supply means is designated as a channel channel transistor. 12. The current sensing circuit of the semiconductor memory device according to claim 11, wherein the third current supply means is composed of a channel channel transistor. 12. The method of claim 11, wherein the first current supply means is formed of a transistor having a smaller size than the third current supply means, and after the complementary low address strobe signal is activated, the decoded P-channel transistor is turned on. Current sensing circuit of semiconductor memory device. 12. The memory array of claim 11, wherein the second current supply means is formed of a transistor having a smaller size than the first current supply means, and is synchronized with the decoded low address after the complementary low address strobe signal is activated. A current sensing circuit of a semiconductor memory device, characterized in that it is activated by a signal used as an input of a circuit for synchronizing a column selection line used to load data into a specific input / output line to turn on a channel channel transistor. 12. The data array of claim 11, wherein the third current supply means is formed of a transistor having a larger size than the second current supply means, and is synchronized with the decoded low address after the complementary low address strobe signal is activated. A current sensing circuit of a semiconductor memory device, characterized in that the signal used as an input of a circuit for synchronizing a column selection line used to carry a specific input / output line and a signal of a parallel bit test are turned on to turn on a channel channel transistor.