KR0172427B1 - Quad column address strobe width extended data out memory device - Google Patents

Abstract

The present invention relates to a quad-cas EDO mode control circuit of a semiconductor memory device improved to have an output mode of an EDO by improving a quad-cas mode control circuit for inputting / outputting 4-bit data by four CASBs. The quadcas EDO mode control circuit includes a write control clock generator for generating a write control clock in response to activation of a column address strobe signal and a write control signal for accessing data of the memory cell, the column address strobe signal and a row; A read control clock generator for generating a read control clock in response to the input of the address strobe signal and for interrupting the output of the read control clock by activating the write control signal; a data transfer clock in response to the activation of the column address strobe signal; A read driver data switch for generating a signal; a write driver for transmitting data on a data input / output path to the memory cell in response to an input of the write control clock; and maintaining an activation level of the read control clock by the data transfer clock.And at least four circuits comprising read drivers for transmitting read data on a data input / output path to an output pad and blocking data output in response to the blocking of the read control clock.

Description

Quad Cascade Mode Control Circuit with Extended Data Output of Semiconductor Memory Devices

1 is a quad cas mode control circuit diagram of a conventional semiconductor memory device.

FIG. 2 is an operation timing diagram of the semiconductor memory device shown in FIG.

3 is an extended data output mode control circuit diagram of a conventional semiconductor memory device.

4 is an operation timing diagram of the semiconductor memory device shown in FIG.

5 is a quad-cas EDO mode control circuit of a semiconductor memory device according to the present invention.

6 is an operation timing diagram of the semiconductor memory device shown in FIG.

The present invention relates to a semiconductor memory device of the present invention, and more particularly, to a quad-cas address control circuit having an extended data output of a semiconductor memory device.

Various methods are used for reading data stored in memory cells in the semiconductor memory device and outputting the data to the outside. The data output modes currently used in semiconductor memory devices are fast page mode, static column mode, nibble mode, quad cas mode, and extended data output. Fast page mode with extended data out mode (hereinafter referred to as EDO mode), and the like. Here, the EDO mode refers to an operation mode in which data is continuously output without a high impedance zone within the data and the data output period when data is output. In this field, hyper-page is used. Also called a mode.

For example, in dynamic RAM, the quad cascade mode uses four column addresses and strobe signals (hereinafter referred to as CASBs on one chip) and four bits using a number to distinguish four CASBs. Is an operation mode for writing data into a memory cell or reading 4-bit data from the memory cell. That is, this mode is an operation mode in which 4-bit data can be read or written to a desired data input buffer or data output buffer independently by controlling the data input buffer or data output buffer independently when the data is written or read into the memory cell. It is used as a parity bit generator to generate parity bits in a module.

1 is a quad cas mode control circuit diagram of a conventional semiconductor memory device. This configuration can input and output four bits of data by inputting four CASB1, CASB2, CASB3, CASB4, and write control signals WEB (Write Enable bar) and Row Address Strobe signal RASB inputted from outside the chip. Circuit to control the operation.

1 is a read control clock generator 14 which generates a write control clock Φ DTCP in response to activation of a single CASBi (where i is a natural number) and the write control signal WEB and read control in response to input of the CASBi and row address strobe signals RASB. A read control clock generator 16 for generating a clock? RCC and a data line DB / DBB (Data B) in which B outputs a complementary signal having a logic opposite to that of a normal signal in response to an input of the write control clock? A read driver 18 for driving write data input through the input / output line I0 / IOB, and a read driver transferring output pad DOUTi for read data read from a memory cell and input to the data line DB / DBB. There are at least four read and write control circuits of twenty.

Here, the write control signal WEB and the row address strobe signal RASB input to the respective read and write control circuits 12 shown in FIG. 1 are all the same signals, and only four CASB1, CASB2, CASB3, and CASB4 are external to the chip. Are column address strobe signals supplied independently from. The write driver 18 corresponds to a buffer for inputting data on a chip, and the read driver 20 corresponds to an output buffer for driving data output from the chip to an output pad.

FIG. 2 is an operation timing diagram of the semiconductor memory device shown in FIG.

First, the operation of the quad casing mode illustrated in FIG. 1 will be described with reference to the operation waveform diagram of FIG. 2.

When the row address strobe signals RASB and CASBi (where i is a natural number) are activated low and the write control signal WEB is high as shown in FIG. 2 to read data stored in the memory cell, the read and write control circuit 12 All write control clock generators 14 in the are disabled and only read control clock generators 16 are enabled. The read control clock generator 16 enabled as described above activates the read control clock Φ RCC to a high state in response to the low address strobe signals RASB and CASBi being activated low while the write control signal WEB is high. Supply 20. The read driver 20 transmits read data loaded on the data line DB / DBB to the data output pad DOUTi in response to the read control clock .phi.RCC. In this case, the data line DB / DBB is a line on which data to be read or written is carried.

If the row address strobe signals RASB and CASBi are activated low and the write control signal WEB is low in order to write data carried in the data line DB / DBB to the memory cells, all write control in the read and write control circuit 12 is performed. Clock generator 14 is enabled and read control clock generators 16 are all disabled. The write control clock generator 14 activates the write control clock .phi.DTCP in a high state in response to the CASBi transitioning from the precharge state, that is, from the high state to the low state while the write control signal WEB is low. By activating the write control clock .phi.DTCP, the write driver 18 envelopes the data input to the data line DB / DBB and buffers the input / output lines IOi / IOBi. In this case, the input / output line IOi / IOBi is connected to the memory cell through a transfer gate or a column select gate as is well known in the art.

Therefore, when the column address storobe signals such as CASB0, CASB1, CASB2, and CASB3, the write control signal WEB, and the row address strobe signal RASB are input to the circuit as shown in FIG. 1 as shown in FIG. 2, the data output pads DOUT0 to DOUT3. It can be seen that the output data and the data transmission to the input / output lines IOO / IOBO to IO3 / IOB3 are the same as those in FIG. As described above, in the quad cascade mode, logic of a write driver and a read driver that receives CASBi information is divided to enable independent control of 4-bit data through an input / output buffer.

However, the quad cascade mode as shown in FIG. 1 has a problem in that it is not suitable for high frequency operation of outputting data at high speed due to the presence of a high-impedance zone as shown in FIG. That is, such a circuit has a disadvantage in that the activation time of the CASB must be long to ensure the data development and data fetch time of the output data line when data is read.

In order to solve the problem that the high-speed operation cannot be performed due to the high impedance zone caused by the level transition of CASBi as described above, the data development time is maintained at a high speed even while the CASB is precharged. An EDO mode control circuit has been introduced to perform the extended data output, as shown in FIG.

FIG. 3 is an EDO mode control circuit diagram for outputting extended data of a conventional semiconductor memory device. The read control clock? RCC is generated in response to the activation of the row address strobe signals RASB and CASB, and the precharge level CASB and the activated write. A plurality of read drivers 20 which are disabled by input of the control signal WEB, and a plurality of read drivers 20 which develp data input to the data lines DBi / DBBi and output them to the output pad DOUTi in response to the activation of the read control clock .phi.RCC. And a data path control switch which is enabled by activation of the CASB and selects read data on at least one read data line among a plurality of read data lines DOi / DOBi by input of an address and connects the read data to a corresponding read driver 20. It consists of 22. At this time, each of the data lines DB0 / DBB0, DB1 / DBB1, DB2 / DBB2, and DB3 / DBB3 of the data path control switch 22 is connected to inputs of the read drivers 20 connected to the output pads DOUT0, DOUT1, DOUT2, and DOUT3, respectively. do.

FIG. 4 is an operation timing diagram of the semiconductor memory device shown in FIG. 3, which illustrates an operation relationship of controlling a plurality of read drivers 20 as one read driver controller 21. The operation of the EDO control circuit as shown in FIG. 3 is as follows.

Now, when the row address strobe signals RASB and CASB are activated low as shown in FIG. 4 and the write control signal WEB is high, the read driver controller 21 is activated high as shown in FIG. ΦRCC is supplied to each read driver 20. Each of the read drivers 20 develops a signal on the data line DBi / DBBi connected to the input node as shown in FIG. 4 and outputs the signal to each output pad DOUTi.

At this time, the data path control switch 22 performs data supply to the input node of the read driver 20. That is, the data path control switch 22 selects one data line from among a plurality of read data lines DOi / DOBi in response to input of a CASB and an address and switches the supplied data line to the corresponding read driver 20.

However, the EDO mode control circuit operated as described above operates at high speed by maintaining and expanding the developed data until both the row address strobe signals RASB and CASB transition to the precharge state, that is, the high state. Although there is an advantage, it is not possible to input and output four bits of data using four column address strobe signals CASBi like the quad cas mode.

Accordingly, an object of the present invention is to provide a quad card EDO mode control circuit that can operate at a high frequency and easily generates parity.

Another object of the present invention is to provide a quad-cas EDO mode control circuit capable of simultaneously reading and writing 4-bit data at high speed.

The above object of the present invention is a semiconductor memory device having at least one memory cell and a data input / output path for reading or writing data stored in the memory cell, the column address strobe signal for accessing data of the memory cell. And a write control clock generator for generating a write control clock in response to the activation of the write control signal, a read control clock in response to the input of the column address strobe signal and the row address strobe signal, and by the activation of the write control signal. A read control clock generator for blocking output of the read control clock, a read driver data switch for generating a data transfer clock in response to activation of the column address strobe signal, and a data input / output path in response to an input of the write control clock; A write driver for transmitting the data of the data to the memory cell, and a read driver on the data input / output path to transmit read data on the data input / output path to an output pad by maintaining an activation level of the read control clock by the data transfer clock. And at least two read and write controllers configured to read data to block data output, wherein each of the read and write controllers latches data on a data path to an output pad by activating the column address strobe signal to control the write. It is characterized in that the output is maintained until the signal is activated.

Hereinafter, the operation of the preferred embodiment according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings of the embodiments of the present invention, those having substantially the same configuration and function as those in the above-described drawings will use the same reference numerals.

FIG. 5 is a quad cascade EDO mode control circuit of a semiconductor memory device according to the present invention, and inputs four CASB0, CASB1, CASB2, CASB3 and write control signals WEB and a row address strobe signal RASB inputted from outside the chip, This circuit controls the operation of data input / output so that data can be input / output in EDO mode. This configuration comprises a write control clock generator 14 which generates a write control clock Φ DTCP in response to activation of a single CASBi (where i is a natural number) and the write control signal WEB, and in response to activation of the row address strobe signal RASB and the CASBi. A read control clock generator 16 for generating a read control clock? RCC and blocking the output of the read control clock? RCC in response to the activation of the write control signal WEB; a read driver for generating a data transfer clock? Ci in response to the activation of the CASB; Activation of the read control clock? RCC by a data switch 24, a write driver 18 for transferring data on the data line DBi / DBBi to the input / output line IOi / IOBi in response to an input of the write control clock? DTCP; The latched level is used to read data on the data line DBi / DBBi by the CASB. Transmitted to the data delivery clock Development rope to the output pad DOUTi by the ΦC and consists of the write control signal WEB to read driver 20 to terminate the read operation in response to the activation consisting of the data read and write control circuit 12.

At this time, the write control signal WEB and the row address strobe signal RASB input to the respective read and write control circuits 12 shown in FIG. 5 are the same signals, and only CASB0, CASB1, CASB2, and CASB3 are independent from the outside of the chip. Column address strobe signals supplied to

FIG. 6 is an operation timing diagram of the semiconductor memory device shown in FIG.

Hereinafter, the operation of the preferred embodiment configured as shown in FIG. 5 according to the present invention will be described in detail with reference to the operation timing diagram of FIG.

Now, row address strobe signal RASB and column address strobe signal CASBi (I in the description of the present invention) are activated low as shown in FIG. 6 to read data stored in a memory cell (not shown). When the write control signal WEB becomes high, all the write control clock generators 14 in the read and write control circuit 12 are disabled, and only the read control clock generator 16 is enabled.

At this time, the read driver data switch 24 generates a data transfer clock .phi.Ci that transitions high on the falling edge of CASBi and goes low on the rising edge of CASBi in response to the activation of CASBi. The data transfer clock? Ci generated in this way is input to the read driver 20. The enabled read control clock generator 16 activates the read control clock ΦRCC as shown in FIG. 6 in a high state in response to the low address strobe signals RASB and CASBI being low when the write control signal WEB is high. Supply to driver 20. Accordingly, the read driver 20 inputs the data transfer clock? Ci and the read control clock? RCCi as shown in FIG.

In such a state, the read data is transmitted to the data line DBi / DBBi of FIG. 5 by a multiplexer which selects read data accessed from the memory cell by an address input in the precharge period of CASBi. The read driver 20 develps the read data input through the data lines DBi / DBBi and outputs the output data to the output pad DUOTi as shown in FIG. 6 when both the data transfer clock .phi.Ci and the read control clock .phi.RCCi are high.

That is, the read driver 20 buffers the read data to the output pad DUOTi at the initial rising edge of the read control clock .phi.RCCi in the first cycle of the CASBi. In this case, the read control clock? RCCi is input to the read driver 20 and is latched as shown in FIG. 6 at the rising edge of the data transfer clock? Ci.

Thereafter, from the second cycle of CASBi, the read driver 20 is operated in the quad cas mode by the data transfer clock .phi.Ci. That is, since the read control clock ΦRCCi is latched and held high from the second CASBi cycle, the next read data is inputted to the data lines DBi / DBBi from the multiplexer, and the read controller 20 reads the data transfer clock ΦCi. The read data inputted in response to the rising edge of is devel- oped and outputs the data to the output pad DOUTi as shown in FIG. Therefore, in the quad cascade EDO mode according to the present invention, the output of valid data is continuously maintained even at the lead time, i.e., even during the precharging when CASBi transitions to high while the write control signal WEB is in a high state.

If the write control signal WEB transitions from high to low to change to the write mode, the read control clock generator 16 releases the read control clock? RCCi latched high to output low in response to the activation of the write control signal WEB. . At this time, when the read control clock .phi.RCCi goes low as described above, the read driver 20 blocks the output of the data (high impedance output state). When the write control signal WEB is activated low as described above, the write control clock generator 14 is enabled.

The write control clock generator 14 enabled by the input of the write control signal WEB generates the write control clock .phi.DTCPi according to the toggle of CASBi. This write control clock .phi.DTCPi is activated when CASBi is activated low and is deactivated when CASBi is precharged high. The write driver 18 connected to the output node of the write control clock generation circuit 12 transmits the write data input to the data line DBi / DBBi to the input / output line IOi / IOBi in response to the activation of the write control clock .phi.DTCPi. .

Accordingly, CASB0, CASB1, and CASB2 having an exclusive period in a state in which the row address strobe signal RASB and the write control signal WEB are input to each of the read and write control circuits 12 of the quadcas EDO mode control circuit having the configuration as shown in FIG. When the CASB3s are input, the read driver 20 and the write driver 18 output the output of the expanded data in the EDO mode as shown in FIG. In addition, when the write control signal WEB is activated as a write, it can be seen that data is written by transferring data input in quad cas mode to a memory cell.

As described above, the present invention can access 4-bit data at high speed by applying a quad casing mode to the control circuit of the extended data output mode.

Claims (1)

A semiconductor memory device having at least one memory cell and a data input / output path for reading data stored in the memory cell or writing data input from the outside into the memory cell, the semiconductor memory device comprising: accessing data of the memory cell; A write control clock generator for generating a write control clock in response to activation of a column address strobe signal and a write control signal, a read control clock in response to input of the column address strobe signal and a row address strobe signal, and generating the write control clock; A read control clock generator for blocking output of the read control clock by activation of a read driver, a read driver data switch for generating a data transfer clock in response to activation of the column address strobe signal, and an input of the write control clock; In response to a write driver for transferring data on a data input / output path to the memory cell, and maintaining the activation level of the read control clock by the data transfer clock to transfer read data on the data input / output path to an output pad, And at least two read and write controls comprising a read driver to block data output in response to the cutoff, wherein each of the read and write controls outputs data on a data path by activating the column address strobe signal. And a latched by a pad to maintain and output the write control signal until the write control signal is activated.