KR100735604B1 - sense amplifier driving method in semiconductor memory device - Google Patents

Abstract

The present invention is a method for obtaining the correct amplified signal for the last valid address for the skew input of the external address signal when the latch type is used as the ATD method and the data sense amplifier during the read operation in the asynchronous semiconductor memory. The word line enable signal for designating the memory cell corresponding to the input address is configured using the rising edge of the ATD pulse mentioned above. The sense amplifier enable signal is configured using the rising edge of the mentioned ATD pulses, and the sense amplifier sync signal uses the polling edge of the ATD pulses. Such a configuration ensures that the skew-independent operation is assured by speeding up the read operation in the asynchronous memory with low voltage operation.

Asynchronous Semiconductor Memory, Latched Sense Amplifiers, Rising Edges, Polling Edges

Description

Sense amplifier driving method in semiconductor memory device             

1 to 3 are operation timing diagrams of a sense amplifier driving according to the prior art

4 is an operation timing diagram of driving a sense amplifier according to an embodiment of the present invention.

5 is a circuit diagram of a latch type sense amplifier applied to the present invention;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor memories, and more particularly, to a method of driving a sense amplifier in a volatile semiconductor memory device such as a static random access memory.

In recent years, with the rapid spread of information media such as computers, semiconductor devices such as semiconductor memories have been rapidly developed. In particular, when such a semiconductor device is a memory for storing information, high speed operation and large capacity storage capability are increasingly required. In order to meet such demands, semiconductor manufacturing makers are continuously researching to improve the density, reliability, and response speed of semiconductor memory devices.

Control signals required for a read operation in a conventional asynchronous semiconductor memory device are generated by using an address transition detect (ATD) pulse for low power operation. That is, a word line enable signal (W / L enable signal) for activating a word line of a corresponding memory cell to access a specific memory cell is in response to a rising edge or a falling edge of the ATD pulse. The S / A enable signal and the S / A equalizer signal of a sense amplifier which are generated and sense and amplify a signal of a developed memory cell in a selected bit line are It is generated by receiving a rising edge or a falling edge of the ATD pulse and delaying it by a predetermined time.

As described above, in the case of using the sense amplifier as a current mirror type differential amplifier, a conventional control signal generation method which has been commonly used until now is using only one of a rising edge or a falling edge. When the word line activation signal generation time, the activation time of the sense amplifier, and the synchronization signal signal generation time are determined using only one rising edge or the falling edge of the ATD pulse, the reliability of the read operation may be deteriorated.

In recent years, in order to meet the demand of low power consumption and high speed memory products, the sense amplifier has been adopted as a latch type sense amplifier. The latch type sense amplifier 10 having the configuration shown in FIG. 5 operates sensitively in response to a change in the input level, and the amplified result does not change in an operating cycle unlike the current mirror differential amplifier. Has

Determining when to activate the sense amplifier and to apply the synchronization signal to the difference between the input signals of the sense amplifiers is a very important factor in terms of the reliability of the read operation and the fast response. In particular, there is an urgent need for a technique that can reliably provide a sense amplification output even for skew input of address and control signals in an asynchronous memory device using ATD pulses.

An object of the present invention is to provide a sense amplifier driving method that can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a semiconductor memory device capable of performing a read operation at a higher speed.

It is still another object of the present invention to provide a method for reliably providing a sense amplification output even for a skew input of an address and a control signal in an asynchronous memory device using an ATD pulse.

It is still another object of the present invention to provide a sense amplifier driving method suitable for driving a latch type sense amplifier.

According to an aspect of the present invention for achieving the above object, a rising edge and a falling edge of an ATD pulse in an operation control method in a semiconductor memory device employing an address transition detection method and using a latch type sense amplifier. The operation of the semiconductor memory device may be controlled by generating a word line activation signal, a sense amplifier activation, and a synchronization signal using both.

According to the above method, the sense amplification output can be reliably provided even for the skew input of the address and control signal in the asynchronous memory device using the ATD pulse, thereby ensuring the reliability of the read operation. As a result, a skew-independent operation is obtained while speeding up the read operation.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, a conventional control signal generation method will be described with reference to the drawings without any intention other than to provide a thorough understanding of the embodiments of the present invention described below. First, an operation timing diagram of FIG. 1 shows a relationship between generation of control signals, for example, word line activation signal and sense amplifier activation and synchronization signal PSAEQb when a current mirror type differential amplifier is used in a semiconductor memory device. In the figure, it can be seen that in response to the rising edge of the ATD pulse, a word line activation signal and an activation / synchronization signal (PSAEQb) of the differential amplifier are generated. 1 also shows a case where an address is normally input without skew.

When the address input changes, such as waveform 1A, ATD pulses and BL / DL (data line) precharge pulses, such as waveforms 1B and 1C, are generated. Next, the rising edge of the ATD pulse of 1B is generated to generate the wordline activation signal of 1D and the sense amplifier activation signal of 1E. At the same time, a 1C sense amplifier synchronization signal is generated, and data of the selected memory cell is supplied to the input of the sense amplifier.

The operation timing diagram of FIG. 2 is the same as the circuit configuration applied to the operation timing of FIG. 1, but illustrates an example in which an input address is input with skew. The matter distinguished from FIG. 1 in FIG. 2 is a BL / BLb signal of 2G. That is, the BL / BLb signal of 2G is different from FIG. 1 when the BL / DL precharge signal of waveform 2C is disabled. In this case, the output of the sense amplifier becomes invalid according to ambient noise and mismatch of the sense amplifier. This is because the waveform BL / BLb is still at the precharge level when the 2F sense amplifier synchronization signal, which receives the rising edge of the ATD pulse, is deactivated. After the BL / DL precharge is deactivated, the waveforms BL / BLb are different from each other, and a valid sense amplifier output comes out.

3 illustrates the activation and synchronization of a word line activation signal and a latch type sense amplifier using a rising edge of an ATD pulse when an input address is input with skew and the sense amplifier is adopted as a latch type sense amplifier as in FIG. It shows the signal being generated. Here, when the waveforms 3A, 3B, 3C, 3D, 3E, 3F, and 3G are the same as the corresponding waveforms in FIG. 2, the output waveform 3H of the latched sense amplifier is not valid, unlike 2H in FIG. . As a result, the latch is latched in the section 3-⑨ of FIG. 3, and thus, even though the BL / BLb shows a difference, it does not form a valid output.                     

As a result, as described with reference to FIGS. 1 to 3, there has been a problem in that a sensing amplification output cannot be reliably provided when there is a skew input of an address and a control signal.

Accordingly, the present invention solves such a conventional problem by generating control signals as shown in FIG. Referring to FIG. 4, a word line activation signal is generated using a rising edge of an ATD pulse, and a synchronization signal of a latch type sense amplifier is generated using a falling edge of an ATD pulse. In the figures, waveforms 4A, 4B, 4C, 4D, and 4E are the same as the corresponding waveforms in FIG. However, since waveform 4F uses the falling edge of the ATD pulse as described above, the sense amplifier synchronization signal is disabled when the BL / DL precharge is disabled. Therefore, the waveform BL / BLb operates as in the case where the level of the sense amplifier is in the normal operating range, and the output is different from showing an invalid output result when the rising edge of the ATD pulse is used as shown in FIG. Will be provided.

Referring to FIG. 5, it is shown that the word line driver 8 generating the word line activation signal is provided with an ATD pulse output from the pulse controller 6. In this case, the word line driver 8 operates according to the operation timing of FIG. 4 to generate a word line activation signal in response to the rising edge of the ATD pulse. Meanwhile, the sense amplifier synchronization signal PSAEQb is generated in response to the falling edge of the ATD pulse. The sense amplifier synchronization signal is a signal for precharging the output nodes N1 and N2 of the sense amplifier 10 to the operating power supply voltage before starting operation of the sense amplifier.

As a result, when an ATD pulse having a constant pulse width is generated in response to the transition of the address signal as described above, the rising edge of the ATD pulse is sensed to generate a word line activation signal, and the falling edge is detected to detect the falling edge of the sense amplifier. Generating an activation signal solves the above-mentioned conventional problem.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can. For example, the response time of the pulse can be appropriately delayed or reversed, and the configuration of the circuit can be appropriately changed according to the case.

According to the present invention as described above, since the sense amplification output can be reliably provided to the skew input of the address and control signals in the asynchronous memory device using the ATD pulse, the reliability of the read operation is guaranteed. As a result, an operation that is independent of skew can be obtained while speeding up the read operation, thereby improving the operation reliability of the semiconductor memory device.

Claims (5)

In a method for generating a word line enable signal and a sense amplifier enable signal in an asynchronous semiconductor memory, When an ATD pulse having a constant pulse width is generated in response to the transition of the address signal, generating a word line activation signal by sensing a rising edge of the ATD pulse and generating an activation signal of the sense amplifier by detecting a falling edge. How to feature. In a method for generating a word line enable signal and a sense amplifier enable signal in an asynchronous semiconductor memory, When there is no change in address, when a transition pulse is generated which transitions to the second state when the address changes and returns to the first state after a certain time, the transition pulse to the second state is generated. Generating a word line activation signal in response to a transition time and generating at least one of an activation signal and a synchronization signal of a sense amplifier in response to a return time of the transition pulse to a first state. delete The method of claim 2, wherein the sense amplifier is a current mirror type differential amplifier. A method of generating a word line activation signal, a sense amplifier activation signal, and a synchronization signal in an asynchronous semiconductor memory: And the word line activation signal and the activation signal of the sense amplifier are generated using a rising edge of an ATD pulse, and the synchronization signal of the sense amplifier is generated using a falling edge of the ATD pulse.

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