KR100227188B1 - Method of forming an element isolation region in a semiconductor device - Google Patents

Method of forming an element isolation region in a semiconductor device Download PDF

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KR100227188B1
KR100227188B1 KR1019970033828A KR19970033828A KR100227188B1 KR 100227188 B1 KR100227188 B1 KR 100227188B1 KR 1019970033828 A KR1019970033828 A KR 1019970033828A KR 19970033828 A KR19970033828 A KR 19970033828A KR 100227188 B1 KR100227188 B1 KR 100227188B1
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mask pattern
forming
layer
polysilicon layer
oxide layer
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KR19990010942A (en
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김현병
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Abstract

본 발명은 반도체 소자의 격리방법에 관한 것으로, 소자형성영역과 소자격리영역을 갖는 반도체기판 상의 소자격리영역에 다결정실리콘층을 형성하고, 반도체기판 상에 다결정실리콘층을 덮도록 산화층을 형성하는 단계와, 산화층의 다결정실리콘층과 대응하는 부분을 노출시키는 마스크패턴을 형성하는 단계와, 마스크패턴을 마스크로 다결정실리콘층 및 반도체기판을 선택산화하여 필드산화층을 형성하는 단계와, 마스크패턴을 제거하는 단계를 구비한다.The present invention relates to a method for isolating a semiconductor device, comprising: forming a polysilicon layer in an isolation region on a semiconductor substrate having an element formation region and an isolation region, and forming an oxide layer to cover the polysilicon layer on the semiconductor substrate And forming a mask pattern exposing a portion corresponding to the polysilicon layer of the oxide layer, and forming a field oxide layer by selectively oxidizing the polysilicon layer and the semiconductor substrate using the mask pattern as a mask, and removing the mask pattern. With steps.

따라서, 븐 발명에서는 소자격리를 의한 필드산화층이 측면으로 성장하여 발생되는 버즈빅을 최소화할 수 있어서 소자형성영역이 축소되는 것을 방지가능한 잇점이 있다.Therefore, in the invention of the present invention, the field oxide layer due to isolation of the device can be minimized, thereby minimizing buzz big, which can prevent the device formation region from shrinking.

Description

반도체 소자의 격리방법Isolation Method of Semiconductor Devices

본 발명은 반도체 소자의 격리방법에 관한 것으로, 특히 반도체 소자를 집적하여 제작하는 데 있어서, 인접한 반도체 소자간의 간격을 줄는데 적당하도록 한 반도체 소자의 격리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for isolating semiconductor devices, and more particularly, to a method for isolating semiconductor devices suitable for reducing the distance between adjacent semiconductor devices in fabricating integrated semiconductor devices.

반도체 장치가 고집적화되면서 소자격리영역의 크기 축소가 필요하게 되었다.따라서, 단위소자와 단위소자를 분리하여 격리하는 소자격리영역을 최소화하기 위한 격리기술이 반도체 디바이스의 집적도를 향상시키는데 중요한 관건이 되어왔다.As semiconductor devices have been highly integrated, it is necessary to reduce the size of device isolation regions. Therefore, isolation technology for minimizing device isolation regions that separate and isolate unit devices from each other has become an important factor in improving the integration of semiconductor devices. .

도1a 내지 1d 는 로코스(LOCOS : Local Oxiddation of Semiconductor)를 이용한 종래의 통상적인 소자의 격리를 위한 공정도이다.1A-1D are process diagrams for isolation of a conventional conventional device using LOCOS (Local Oxidation of Semiconductor).

도1a 를 참조하면, 반도체기판(100) 상에 열산화 방법 등에 의해 완충산화층(102)을 형성하고, 완충산화층(102) 상에 화학기상증착(Chemical Vapor Deposition:이하, CVD 라 칭함) 방법에 의해 질화실리콘층(104)을 형성한다.Referring to FIG. 1A, a buffer oxidation layer 102 is formed on a semiconductor substrate 100 by a thermal oxidation method or the like, and a chemical vapor deposition (hereinafter referred to as CVD) method is performed on a buffer oxide layer 102. The silicon nitride layer 104 is formed by this.

도면에서 A 부위는 소자격리영역을, 그리고 B는 소자형성영역을 지칭한 것이다. 이어서, 질화실리콘층(104) 상에 감광막(photoresist)을 도포한 후, 노광 및 현상하여 질화실리콘층(104)을 노출시키는 마스크패턴(mask pattern)(106)을 형성한다.In the drawing, the portion A refers to the device isolation region and the portion B refers to the element formation region. Subsequently, a photoresist is applied on the silicon nitride layer 104, and then exposed and developed to form a mask pattern 106 that exposes the silicon nitride layer 104.

도1b 를 참조하면, 마스크패턴(106)을 마스크로 질화실리콘층(104) 및 완충산화충(102)을 제거하여 반도체기판(100)의 소자격리영역(A)을 노출시킨다. 이 때,마스크패턴(106)이 형성되어 반도체기판(100)이 노출되지 않은 부분을 소자형성영역(B)이 된다. 그리고, 마스크패턴(106)을 제거한다.Referring to FIG. 1B, the silicon nitride layer 104 and the buffer oxide 102 are removed using the mask pattern 106 as a mask to expose the device isolation region A of the semiconductor substrate 100. At this time, the mask pattern 106 is formed so that the portion where the semiconductor substrate 100 is not exposed becomes the element formation region B. Then, the mask pattern 106 is removed.

도1c 를 참조하면, 반도체기판(100)의 노출된 소자격리영역(A)을 선택산화시킴으로써 소자격리를 위한 필드산화층(110)을 형성한다. 이 때, 반도체기판(100)의 질화실리콘층(104) 및 완충산화층(102)에 의해 덮혀진 소자형성영역(B)은 산화되지 않는다.Referring to FIG. 1C, the field oxide layer 110 for device isolation is formed by selectively oxidizing the exposed device isolation region A of the semiconductor substrate 100. At this time, the element formation region B covered by the silicon nitride layer 104 and the buffer oxidation layer 102 of the semiconductor substrate 100 is not oxidized.

도1d 를 참조하면, 소자형성영역(B)에 잔류된 질화실리콘층(104) 및 완충산화층(102)을 제거한다.Referring to FIG. 1D, the silicon nitride layer 104 and the buffer oxide layer 102 remaining in the device forming region B are removed.

그러나, 종래의 반도체 소자 격리방법에서는 필드산화층을 소자형성영역으로 수평 확장시키는 버즈빅(bird`s beak)이 크게 형성되어 결과적으로, 소자형성영역을 축소시키는 문제점이 발생되었다.However, in the conventional semiconductor device isolation method, a large bird's beak is formed to horizontally expand the field oxide layer to the device formation region, resulting in a problem of reducing the device formation region.

본 발명의 목적은 소자격리를 선택산화 시, 버즈빅으로 인한 소자형성영역의 축소를 방지하여 고집적화에 대처가능한 반도체 소자의 격리방법을 제공하려는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for isolating semiconductor devices capable of coping with high integration by preventing reduction of device formation regions due to Buzzvik upon selective oxidation of device isolation.

따라서, 상기의 목적을 달성하고자, 본 발명의 반도체 소자의 격리방법은 소자형성영역과 소자격리영역을 갖는 반도체기판 상의 소자격리영역에 다결정실리콘층을 형성하고, 반도체기판 상에 다결정실리콘층을 덮도록 산화층을 형성하는 단계와, 산화충의 다결정실리콘층과 대응하는 부분을 노출시키는 마스크패턴을 형성하는 단계와, 마스크패턴을 마스크로 다결정실리콘층 및 반도체기판을 선택산화하여 필드산화층을 형성하는 단계와, 마스크패턴을 제거하는 단계를 구비하는 것을 특징으로 한다.Therefore, in order to achieve the above object, in the isolation method of a semiconductor device of the present invention, a polysilicon layer is formed on an element isolation region on a semiconductor substrate having an element formation region and an element isolation region, and covers the polysilicon layer on the semiconductor substrate. Forming an oxide layer to form an oxide layer, forming a mask pattern exposing a portion corresponding to the polysilicon layer of the oxide, and selectively oxidizing the polysilicon layer and the semiconductor substrate using the mask pattern as a mask to form a field oxide layer; And removing the mask pattern.

이하, 첨부된 도면을 참조하여 본 발명을 설명하겠다.Hereinafter, the present invention will be described with reference to the accompanying drawings.

도1a 내지 도1d 는 통상적인 종래의 로코스 방법에 의한 반도체 소자의 소자격리를 위한 공정도이고,1A to 1D are process charts for device isolation of a semiconductor device by a conventional conventional LOCOS method,

도2a 내지 도2e 는 본 발명에 따른 반도체 소자의 소자격리 공정도이다.2A to 2E are device isolation process diagrams of a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

100, 200 : 반도체 기판 102, 206 : 산화층100, 200: semiconductor substrate 102, 206: oxide layer

104 : 질화실리콘층 106, 204, 208 : 마스크패턴104 silicon nitride layer 106, 204, 208 mask pattern

110, 210 : 필드산화층 202 : 다결정실리콘층110, 210: field oxide layer 202: polysilicon layer

A, A' : 소자격리영역 B, B' : 소자형성영역A, A ': device isolation region B, B': device formation region

도2a를 참조하면, 반도체기판(200)에 다결정실리콘을 CVD 방법에 의해 증착하여 다결정실리콘층(202)을 형성한다.Referring to FIG. 2A, polysilicon is deposited on the semiconductor substrate 200 by CVD to form a polysilicon layer 202.

이때, 다결정실리콘층(202)은 이 후 선택산화를 하기 위한 것으로, 산화될 수 있는 적절한 두께인 1000 ∼ 2000 Å 정도로 한다.At this time, the polysilicon layer 202 is for the selective oxidation after that, it is about 1000 ~ 2000 GPa which is an appropriate thickness that can be oxidized.

이어서, 다결정실리콘층(202) 상에 감광막을 도포한 후, 노광 및 현상하여 소자형성영역(B')의 다결정실리콘층(202)을, 노출시키는 제 1마스크패턴(204)를 형성한다.Subsequently, after the photosensitive film is coated on the polysilicon layer 202, the photomask is exposed and developed to form a first mask pattern 204 for exposing the polysilicon layer 202 of the element formation region B '.

도2b 를 참조하면, 제 1 마스크패턴(204)을 마스크로 다결정실리콘층(202)을 소자격리영역(A')에만 잔류하도록 식각한다.Referring to FIG. 2B, the polysilicon layer 202 is etched using only the first mask pattern 204 as a mask so as to remain only in the device isolation region A '.

다음에, 제 1 마스크패턴(204)을 제거한후, 노출된 반도체기판(200)에 소자격리 영역(A')에 잔류되는 다결정실리콘층(202)을 덮도록 산화실리콘을 증착하여 산화층(206)을 형성한다.Next, after the first mask pattern 204 is removed, silicon oxide is deposited on the exposed semiconductor substrate 200 so as to cover the polysilicon layer 202 remaining in the device isolation region A '. To form.

도2c 를 참조하면, 산화층(206)상에 질화실리콘을 도포한 후, 포토리쏘그래피방법으로 패터닝하여 소자격리영역(A`)의 산화층(206)을 노출시키는 제 2마스크패턴(208)를 형성한다. 이 때 제2 마스크패턴(208)은 다결정실리콘층(202)의 측면과 대응되는 산화층(206)을 덮도록 형성한다. 즉, 제2 마스크패턴(208)이 소자격리영역(A')의 소정부위를 덮도록 한다.Referring to FIG. 2C, after the silicon nitride is coated on the oxide layer 206, a second mask pattern 208 is formed to expose the oxide layer 206 of the device isolation region A ′ by patterning the photoresist layer. do. In this case, the second mask pattern 208 is formed to cover the oxide layer 206 corresponding to the side surface of the polysilicon layer 202. That is, the second mask pattern 208 covers a predetermined portion of the device isolation region A '.

도2d를 참조하면, 제 2마스크패턴(208)을 마스크로 사용하여 다결정실리콘층(208) 및 반도체기판(200)을 선택적으로 산화시켜 필드산화층(210)을 형성한다. 상기예서 필드산화층(210)을 형성할 때 산화층(206) 하부의 다결정실리콘층(202)이 산화된 후 점차적으로 반도체기판(200)도 산화되어 형성된다.Referring to FIG. 2D, the field oxide layer 210 is formed by selectively oxidizing the polysilicon layer 208 and the semiconductor substrate 200 using the second mask pattern 208 as a mask. In the above example, when the field oxide layer 210 is formed, the polysilicon layer 202 under the oxide layer 206 is oxidized, and then the semiconductor substrate 200 is gradually oxidized.

이 때, 다결정실리콘층(208)이 먼저 산화되고 반도체기판(200)이 산화되므로 소자격리영역(A`)을 덮은 제 2마스크패턴(208)에 의해 소자형성영역(B`)으로 산화되는 것을 방지하여 버즈빅의 형성을 억제한다.At this time, since the polysilicon layer 208 is first oxidized and the semiconductor substrate 200 is oxidized, the polysilicon layer 208 is oxidized to the device formation region B` by the second mask pattern 208 covering the device isolation region A`. Prevents the formation of buzz big.

도2e를 참조하면, 소자형성영역(B`)에 잔류된 제 2마스크패턴(208)과 완충산화막(205)을 제거한다.Referring to FIG. 2E, the second mask pattern 208 and the buffer oxide film 205 remaining in the device formation region B` are removed.

상술한 바와 같이, 본 발명의 소자격리방법에서는 소자격리를 위한 필드산화층이 측면으로 성장하여 발생되는 버즈빅을 최소화할 수 있어서 소자형성영역이 축소되는 것을 방지가능하다.As described above, in the device isolation method of the present invention, the field oxide layer for device isolation can be minimized, thereby minimizing buzz big, which can prevent the device formation region from shrinking.

또한, 소자형성영역이 축소되는 것을 방지가능함에 따라, 고집적화에 유리하여초미세가공이 가능한 잇점이 있다.In addition, as the device forming region can be prevented from being reduced, there is an advantage in that ultrafine processing is possible in favor of high integration.

Claims (4)

소자형성영역과 소자격리영역을 갖는 반도체기판 상의 상기 소자격리영역에 다결정실리콘층을 형성하고, 상기 반도체기판 상에 상기 다결정실리콘층을 덮도록 산화층을 형성하는 단계와, 상기 산화층의 다결정실리콘층과 대응하는 부분을 노출시키는 마스크패턴을 형성하는 단계와, 상기 마스크패턴을 마스크로 다결정실리콘층 및 반도체기판을 선택산화하여 필드산화층을 형성하는 단계와, 상기 마스크패턴을 제거하는 단계를 구비한 반도체 소자의 격리방법.Forming a polysilicon layer on the device isolation region on the semiconductor substrate having an element formation region and an element isolation region, and forming an oxide layer on the semiconductor substrate to cover the polycrystalline silicon layer, and a polysilicon layer of the oxide layer; Forming a mask pattern exposing a corresponding portion, forming a field oxide layer by selectively oxidizing a polysilicon layer and a semiconductor substrate using the mask pattern as a mask, and removing the mask pattern; Quarantine Method 청구항 1에 있어서, 상기 다결정실리콘층은 1000 ∼ 2000Å 두께로 형성한 것이 특징인 반도체 소자의 격리방법.The method of claim 1, wherein the polysilicon layer is formed to a thickness of 1000 to 2000 GPa. 청구항 1에 있어서, 상기 마스크패턴으로는 질화실리콘을 사용한 것이 특징인 반도체 소자의 격리방법.The method of claim 1, wherein silicon nitride is used as the mask pattern. 청구항 1에 있어서, 상기 마스크패턴은 상기 산화층의 다결정실리콘층의 측면과 대응되는 부위를 덮도록 형성된 것이 특징인 반도체 소자의 격리방법.The method of claim 1, wherein the mask pattern is formed to cover a portion corresponding to a side surface of the polysilicon layer of the oxide layer.
KR1019970033828A 1997-07-19 1997-07-19 Method of forming an element isolation region in a semiconductor device KR100227188B1 (en)

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