KR100391081B1 - Method for forming field oxide layer of semiconductor device - Google Patents
Method for forming field oxide layer of semiconductor device Download PDFInfo
- Publication number
- KR100391081B1 KR100391081B1 KR1019960049505A KR19960049505A KR100391081B1 KR 100391081 B1 KR100391081 B1 KR 100391081B1 KR 1019960049505 A KR1019960049505 A KR 1019960049505A KR 19960049505 A KR19960049505 A KR 19960049505A KR 100391081 B1 KR100391081 B1 KR 100391081B1
- Authority
- KR
- South Korea
- Prior art keywords
- field oxide
- oxide film
- semiconductor device
- film
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000003647 oxidation Effects 0.000 claims abstract description 4
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 4
- 241000293849 Cordylanthus Species 0.000 abstract description 2
- 230000000452 restraining effect Effects 0.000 abstract 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 필드산화막 형성방법에 관한 것으로, 특히 버즈빅(Bird's Beak)의 발생을 방지할 수 있는 반도체 소자의 필드산화막 형성방법에 관한 것이다.Field of the Invention [0002] The present invention relates to a field oxide film forming method, and more particularly, to a field oxide film forming method of a semiconductor device capable of preventing occurrence of Bird's Beak.
일반적으로 반도체 소자의 제조 공정에서 소자와 소자를 전기적 및 구조적으로 분리시키기 위하여 필드산화막을 형성한다. 이는 각 소자가 인접한 소자로부터간섭을 받지 않고 독립적으로 기능을 수행할 수 있도록 하기 위한 것이다. 그런데 반도체 소자가 고집적화 됨에 따라 필드영역의 크기가 감소되기 때문에 버즈빅의 발생을 최소화하기 위한 새로운 기술이 요구된다.Generally, a field oxide film is formed in order to electrically and structurally separate elements and elements in a semiconductor device manufacturing process. This is so that each device can function independently without interference from adjacent devices. However, since the size of the field region is reduced as the semiconductor device is highly integrated, a new technique for minimizing the occurrence of buzzbig is required.
종래 반도체 소자의 필드산화막 형성방법을 첨부도면을 참조하여 상세히 설명하면 다음과 같다.A conventional field oxide film forming method of a semiconductor device will be described in detail with reference to the accompanying drawings.
도 1A 내지 도 1C는 반도체 소자의 필드산화막 형성방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of a device for explaining a field oxide film forming method of a semiconductor device.
도 1A는 실리콘기판상(1)에 패드산화막(2) 및 질화막(3)을 순차적으로 형성한 상태를 도시한다.1A shows a state in which a pad oxide film 2 and a nitride film 3 are sequentially formed on a silicon substrate 1.
도 1B는 질화막(3) 및 패드산화막(2)의 선택된 영역을 순차적으로 식각하여 필드산화막이 형성될 부분에 홈을 형성한 상태를 도시한다.1B shows a state in which a selected region of the nitride film 3 and the pad oxide film 2 is sequentially etched to form a groove in a portion where a field oxide film is to be formed.
도 1C는 산화공정을 실시하여 필드산화막(4)을 형성한 상태를 도시한다.1C shows a state in which the field oxide film 4 is formed by performing the oxidation process.
상기 종래 LOCUS 방식에 의해 형성된 필드산화막(4)은 도 1C의 A에 도시한 바와 같이 버즈빅이 발생된다. 그러나 최근에 소자의 집적도가 증가하면서 버즈빅이 소자의 액티브영역을 감소시키고, 이로 인해 접합 누설전류를 증가시키는 문제가 발생한다.The field oxide film 4 formed by the conventional LOCUS method generates buzz big as shown in A of FIG. 1C. However, recently, as the degree of integration of the device increases, Buzzbig reduces the active area of the device, thereby increasing the junction leakage current.
따라서 본 발명은 질화막을 이용하여 버즈빅의 발생을 억제 함으로써 상기한 문제를 해소할 수 있는 반도체 소자의 필드산화막 형성방법을 제공하는데 목적이 있다.SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a field oxide film forming method of a semiconductor device which can solve the above-described problem by suppressing the occurrence of burrs by using a nitride film.
상기한 목적을 달성하기 위한 본 발명에 따른 필드 산화막 형성방법은 실리콘기판상에 패드산화막과 폴리실리콘막 및 제 1 질화막을 순차적으로 형성한 후, 상기 제 1 질화막 및 폴리실리콘막의 일부를 순차적으로 식각하여 필드산화막이 형성될 부분에 홈을 형성하는 단계와, 상기 단계로부터 전체 상부면에 제 2 질화막을 형성한 후 상기 홈 저부의 상기 제 2 질화막을 식각하는 단계와, 상기 단계로부터 산화공정에 의해 필드산화막을 형성하는 단계로 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a field oxide film, comprising: sequentially forming a pad oxide film, a polysilicon film, and a first nitride film on a silicon substrate, sequentially etching a part of the first nitride film and a polysilicon film, Forming a groove in a portion where a field oxide film is to be formed; etching the second nitride film in the groove bottom after forming a second nitride film on the entire upper surface from the step; And forming a field oxide film.
도 1A 내지 도 1C는 종래 반도체 소자의 필드산화막 형성방법을 설명하기 위한 소자의 단면도.1A to 1C are sectional views of a device for explaining a field oxide film forming method of a conventional semiconductor device.
도 2A 내지 도 2D는 본 발명에 따른 반도체 소자의 필드산화막 형성방법을 설명하기 위한 소자의 단면도.2A to 2D are sectional views of a device for explaining a field oxide film forming method of a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호의 설명>Description of the Related Art
1 및 11 : 실리콘기판 2 및 12 : 패드산화막1 and 11: silicon substrates 2 and 12: pad oxide film
3 : 질화막 13 : 폴리실리콘막3: nitride film 13: polysilicon film
14 : 제 1 질화막 15 : 제 2 질화막14: first nitride film 15: second nitride film
4 및 16 : 필드산화막4 and 16: field oxide film
이하, 첨부된 도면을 참조하여 본 발명에 따른 필드산화막 형성방법을 설명하면 다음과 같다.Hereinafter, a method of forming a field oxide film according to the present invention will be described with reference to the accompanying drawings.
도 2A 내지 도 2D는 반도체 소자의 필드산화막 형성방법을 설명하기 위한 소자의 단면도이다.2A to 2D are cross-sectional views of a device for explaining a field oxide film forming method of a semiconductor device.
도 2A는 실리콘기판(11)상에 패드 산화막(12)과 폴리실리콘막(13) 및 제 1 질화막(14)을 순차적으로 형성한 후, 제 1 질화막(14) 및 폴리실리콘막(13)의 선택된 영역을 순차적으로 식각하되 폴리실리콘막(13)의 일부분이 잔류되도록 하여 홈 (B)을 형성한 상태를 도시한다.2A shows a state in which the pad oxide film 12, the polysilicon film 13 and the first nitride film 14 are sequentially formed on the silicon substrate 11 and then the first nitride film 14 and the polysilicon film 13 And the grooves B are formed by sequentially etching the selected regions and leaving a part of the polysilicon film 13 remaining.
도 2B는 실리콘기판(11)의 전체 상부면에 제 2 질화막(15)을 400Å 내지 6008Å의 두께로 형성한 상태를 도시한다.2B shows a state in which the second nitride film 15 is formed on the entire upper surface of the silicon substrate 11 to a thickness of 400 to 6008 Å.
도 2C는 홈(B)저부에 형성된 제 2 질화막(15)만 플라즈마로 식각한 상태를 도시한다.2C shows a state in which only the second nitride film 15 formed on the bottom of the groove B is etched by plasma.
도 2D는 산화공정으로 필드산화막(16)이 형성된 상태를 도시한다. 이때 필드산화막(16)과 제 2 질화막(15)은 서로 결합되지 않는 성질 때문에 필드산화막(16)이 제 2 질화막(15)을 침투하지 못하게 된다.2D shows a state in which the field oxide film 16 is formed by the oxidation process. At this time, the field oxide film 16 and the second nitride film 15 are not bonded to each other, so that the field oxide film 16 can not penetrate the second nitride film 15.
상술한 바와 같이 본 발명에 의하면 필드산화막 형성시 필드산화막이 액티브영역에 침투하지 못하도록 함으로써, 버즈빅의 발생을 억제할 수 있다. 따라서 소자간에 누설전류가 감소되어 소자의 신뢰성을 향상시킬 수 있다.As described above, according to the present invention, it is possible to prevent the field oxide film from penetrating into the active region when the field oxide film is formed, thereby suppressing occurrence of buzz vignetting. Therefore, the leakage current between the devices can be reduced and the reliability of the device can be improved.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960049505A KR100391081B1 (en) | 1996-10-29 | 1996-10-29 | Method for forming field oxide layer of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960049505A KR100391081B1 (en) | 1996-10-29 | 1996-10-29 | Method for forming field oxide layer of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980030131A KR19980030131A (en) | 1998-07-25 |
| KR100391081B1 true KR100391081B1 (en) | 2003-10-04 |
Family
ID=37421890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960049505A KR100391081B1 (en) | 1996-10-29 | 1996-10-29 | Method for forming field oxide layer of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100391081B1 (en) |
-
1996
- 1996-10-29 KR KR1019960049505A patent/KR100391081B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980030131A (en) | 1998-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6274444B1 (en) | Method for forming mosfet | |
| US6642125B2 (en) | Integrated circuits having adjacent P-type doped regions having shallow trench isolation structures without liner layers therein therebetween and methods of forming same | |
| US6001709A (en) | Modified LOCOS isolation process for semiconductor devices | |
| US4981813A (en) | Pad oxide protect sealed interface isolation process | |
| US5985725A (en) | Method for manufacturing dual gate oxide layer | |
| KR100391081B1 (en) | Method for forming field oxide layer of semiconductor device | |
| KR0170897B1 (en) | Method of manufacturing element-segregation insulating film of semiconductor device | |
| KR100422960B1 (en) | Method for forming isolation layer of semiconductor device | |
| KR19980070435A (en) | Semiconductor device manufacturing method | |
| KR0166835B1 (en) | Method for forming isolation on a semiconductor device | |
| KR19990006000A (en) | Device Separation Method of Semiconductor Device | |
| KR100205339B1 (en) | Method for forming isolation region of semiconductor device | |
| KR0172760B1 (en) | Method of manufacturing element-isolating insulation film of semiconductor device | |
| KR100190364B1 (en) | Method of forming an element isolation film in a semiconductor device | |
| KR100237013B1 (en) | Method of forming an element field oxide film in a semiconductor device | |
| KR0148611B1 (en) | Formation method of element isolation layer for semiconductor devices | |
| KR100220236B1 (en) | Method of forming a field oxide film of semiconductor device | |
| KR970005703B1 (en) | Semiconductor device and manufacturing method for the same | |
| KR20030001965A (en) | Method for fabricating semiconductor device | |
| KR20000041419A (en) | Method of forming device isolation region | |
| KR19990000376A (en) | Semiconductor device manufacturing method | |
| KR19990004607A (en) | Device isolation insulating film formation method of semiconductor device | |
| KR20030055997A (en) | Semiconductor device having shallow trench isolation(STI) structure and method for forming the same | |
| KR19990055761A (en) | Device Separating Method of Semiconductor Device | |
| KR19990006069A (en) | Device Separating Method of Semiconductor Device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110526 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |