KR0172302B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR0172302B1 KR0172302B1 KR1019950031978A KR19950031978A KR0172302B1 KR 0172302 B1 KR0172302 B1 KR 0172302B1 KR 1019950031978 A KR1019950031978 A KR 1019950031978A KR 19950031978 A KR19950031978 A KR 19950031978A KR 0172302 B1 KR0172302 B1 KR 0172302B1
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- film
- photoresist film
- oxide film
- positive photoresist
- trench
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 2
- 238000000926 separation method Methods 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 4
- 241000293849 Cordylanthus Species 0.000 description 1
- 238000010009 beating Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
본 발명은 반도체 기판 상에 포지티브 감광막, 상기 포지티브 감광막 보다 상대적으로 포토 바이어스가 적은 네가티브 감광막을 차례로 도포하는 단계, 동일한 레트클을 사용하여 상기 네가티브 감광막 및 포지티브 감광막의 소정 부위를 노광 및 현상하는 단계, 상기 노광 및 현상에 의해 잔류하고 있는 감광막들을 식각마스크로 하여 반도체 기판을 소정 깊이 식각하여 트렌치를 형성하는 단계, 상기 잔류 감광막들을 제거하는 단계, 상기 트렌치 내부에 산화막을 메우는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자 분리 방법에 관한 것으로, LOCOS 공정 보다 공정이 간단하고 제조 비용이 많이 절감될뿐만 아니라 최소한의 면적으로 소자분리가 가능하고, 또한 산화막 형성에 의해 발생하는 단차를 완전히 제거함으로써, 후속 공정을 용이하게 하고, 산화막 팽창에 의해 야기되는 중첩 오차가 없어지는 효과를 가져온다.According to the present invention, a method of sequentially applying a positive photoresist film and a negative photoresist film having a relatively smaller photo bias than the positive photoresist film, exposing and developing a predetermined portion of the negative photoresist film and the positive photoresist film using the same reticle, Forming a trench by etching the semiconductor substrate a predetermined depth using the remaining photoresist as an etch mask, removing the residual photoresist, and filling an oxide film in the trench. The present invention relates to a method for separating semiconductor elements, which is simpler than a LOCOS process, reduces manufacturing costs, and enables device separation with a minimum area and further eliminates steps generated by oxide film formation. For This brings about the effect that the overlap error caused by oxide film expansion is eliminated.
Description
제1a도 내지 제1g도는 본 발명의 일실시예에 따른 소자 분리 공정도.1A to 1G are device isolation process diagrams according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 포지티브 감광막1 silicon substrate 2 positive photosensitive film
3 : 네가티브 감광막 4 : 레티클3: negative photoresist 4: reticle
5 : 노광된 포지티브 감광막 6 : 노광된 네가티브 감광막5: exposed positive photosensitive film 6: exposed negative photosensitive film
7 : 산화막7: oxide film
본 발명은 반도체 소자 제조 공정중 소자간의 격리를 위한 소자 분리 방법에 관한 것으로, 바이어스가 서로 다른 감광막을 사용하여 소자 분리를 이루는 방법에 관한 것이다.The present invention relates to a device isolation method for isolation between devices in a semiconductor device manufacturing process, and to a method for device isolation using photosensitive films having different biases.
반도체 소자의 제조공정에서 소자간의 전기적인 절연을 위하여 종래에는 질화막을 산화마스크층으로 사용하여 실리콘 기판의 소자분리 지역을 국부산화시키는 LOCOS(Local Oxidation of Silicon: 이하 LOCOS라 칭함) 방법을 사용하고 있다.In order to electrically insulate between devices in a semiconductor device manufacturing process, a LOCOS (Local Oxidation of Silicon: LOCOS) method is conventionally used to locally localize an isolation region of a silicon substrate by using a nitride film as an oxide mask layer. .
LOCOS에 의한 소자분리방법은 실리콘기판상에 패드산화막을 형성하고 그 위에 질화막을 증착하여 마스크 공정과 식각공정을 소자분리막이 형성될 지역의 실리콘 기판을 노출시킨 다음, 열산화공정으로 노출된 실리콘기판을 산화시키는 방법이다. 이때 질화막은 기판의 산화방지를 위한 산화마스크 역할을 하며, 패드산화막은 질화막에 의한 스트레스를 완화시켜주는 역할을 한다.In the device isolation method using LOCOS, a pad oxide film is formed on a silicon substrate, and a nitride film is deposited on the silicon substrate to expose the silicon substrate in the region where the device isolation film is to be formed, and then the silicon substrate is exposed by thermal oxidation. It is a method of oxidizing. In this case, the nitride film serves as an oxide mask to prevent oxidation of the substrate, and the pad oxide film serves to relieve stress caused by the nitride film.
그러나, 종래의 LOCOS 공정은 버즈비크(Bird's Beak)가 발생하여 소자의 활성영역을 감소시키는 문제점이 있어, 종래에는 LOCOS 방법을 변형한 PBL(Polysilicon Buffered LOCOS)등 새로운 소자분리 방법들이 제안되었으나, 반도체 소자의 집적도가 64M, 256M등 고집적화됨에 따라 소자가 형성되는 소자형성지역을 확보하기 위한 근본적인 해결책은 되지못하고 있으며, 그 밖의 다른 변형된 LOCOS 공정은 그 공정이 너무 복잡하여 공정상 해결해야 될 문제점들을 안고 있다.However, the conventional LOCOS process has a problem of reducing the active area of the device due to the occurrence of a bird's beak, so conventionally, new device separation methods such as PBL (Polysilicon Buffered LOCOS) modified from the LOCOS method have been proposed. As the integration of devices is highly integrated such as 64M, 256M, it is not a fundamental solution to secure the device formation area where devices are formed.Other modified LOCOS processes are too complicated to solve the problems that need to be solved. Holding it.
또한, LOCOS 및 LOCOS를 변형한 소자분리 방법을 사용할 경우 소자분리막의 두께 때문에 소자분리영역과 활성영역간의 단차가 크게 발생하여 금속배선등의 후속공정 진행시 문제점이 발생하게 되며, 고집적화로 인해 좁은 지역에서 열산화로 소자분리막을 형성해야 하므로 스트레스 증가로 소자분리막의 두께는 제한될 수밖에 없어 소자간의 전기적 분리에 결함이 생긴다.In addition, when the device isolation method using the LOCOS and the modified LOCOS is used, a step difference between the device isolation region and the active region is large due to the thickness of the device isolation layer, which causes problems in the subsequent process such as metal wiring. Since the device isolation film must be formed by thermal oxidation at, the thickness of the device isolation film must be limited due to the increase in stress, which causes a defect in electrical separation between devices.
따라서, 본 발명은 국부산화 공정을 사용하지 않은 단순한 공정으로 미세한 영역의 소자 분리를 이루며 기판의 단차 발생 방지 및 버즈비크 발생을 방지하여 소자의 활성영역 증대를 이루는 반도체 소자 분리 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a semiconductor device separation method that achieves a device separation in a fine region by a simple process without using a local oxidation process and prevents stepped generation of the substrate and prevents the occurrence of buzz beating to increase the active area of the device. There is this.
상기 목적을 달성하기 위하여 본 발명은 반도체 기판 상에 포지티브 감광막, 상기 포지티브 감광막 보다 상대적으로 포토 바이어스가 적은 네가티브 감광막을 차례로 도포하는 단계, 동일한 레트클을 사용하여 상기 네가티브 감광막 및 포지티브 감광막의 소정 부위를 노광 및 현상하는 단계, 상기 노광 및 현상에 의해 잔류하고 있는 감광막들을 식각마스크로 하여 반도체 기판을 소정 깊이 식각하여 트렌치를 형성하는 단계, 상기 잔류 감광막들을 제거하는 단계, 상기 트렌치 내부에 산화막을 메우는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention sequentially applies a positive photoresist film and a negative photoresist film having a relatively smaller photo bias than the positive photoresist film on a semiconductor substrate, and using a same reticle, a predetermined portion of the negative photoresist film and the Exposing and developing, etching the semiconductor substrate to a predetermined depth using the photoresist films remaining by the exposure and development as an etch mask, removing the residual photoresist films, and filling an oxide film inside the trench. Characterized in that comprises a.
이하, 첨부된 도면 제1a도 내지 제1g도를 참조하여 본 발명의 일실시예를 상세히 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1G.
먼저, 제1a도와 같이 실리콘 기판(1) 상에 포지티브(positive) 감광막(2)을 도포하고, 상기 포지티브 감광막(2) 상에 네가티브(negaive) 감광막(3)을 도포한다. 이때, 포지티브 감광막(2)은 네가티브 감광막(3) 보다 포토 바이어스가 큰 감광막을 사용하며, 포지티브 감광막(2) 보다 네가티브 감광막(3)을 두껍게 도포한다.First, as shown in FIG. 1A, a positive photoresist film 2 is applied onto the silicon substrate 1, and a negative photoresist film 3 is applied onto the positive photoresist film 2. At this time, the positive photosensitive film 2 uses a photosensitive film having a larger photo bias than the negative photosensitive film 3, and the negative photosensitive film 3 is thicker than the positive photosensitive film 2.
이어서, 제1b도와 같이 광투과부(4a) 및 광차단부(4b)를 갖는 레티클(4)을 사용하여 노광 공정을 실시하는데, 도면에 도시된 바와같이 포지티브 감광막(2)은 네가티브 감광막(3) 보다 포토 바이어스가 크기 때문에, 포지티브 감광막(2)은 네가티브 감광막(3) 보다 넓은 지역(도면의 A, B 비교)이 노광된다. 도면부호 5는 노광된 포지티브 감광막, 6은 노광된 네가티브 감광막을 각각 나타낸다.Subsequently, an exposure process is performed using the reticle 4 having the light transmitting portion 4a and the light blocking portion 4b as shown in FIG. 1B. As shown in the drawing, the positive photosensitive film 2 is a negative photosensitive film 3. Since the photo bias is larger, the area (compared to A and B in the drawing) of the positive photosensitive film 2 is exposed to the negative photosensitive film 3. Reference numeral 5 denotes an exposed positive photosensitive film, and 6 denotes an exposed negative photosensitive film.
이어서, 제1c도는 현상을 실시한 상태의 단면도로서, 네가티브 감광막은 노광된 부위(6) 이외의 부분이 제거되고, 포지티브 감광막은 노광된 부위(5)가 제거되게 되는 데, 포지티브 감광막의 노광된 부위(5)는 네가티브 감광막의 노광 부위(6)에 덮혀져 있기 때문에 노출되는 표면부터 제거되기 시작하여 도면에 도시된 바와 같이 노광된 네가티브 감광막(6) 하부에서 언더컷 모양을 형성한다.Subsequently, FIG. 1C is a cross-sectional view of the developed state, in which a portion other than the exposed portion 6 is removed from the negative photoresist film, and the exposed portion 5 is removed from the positive photoresist film. Since 5 is covered by the exposed portion 6 of the negative photosensitive film, it begins to be removed from the exposed surface to form an undercut shape under the exposed negative photosensitive film 6 as shown in the figure.
이어서, 제1d도와 같이 잔류하고 있는 감광막(2, 5, 6)들을 식각마스크로 하여 실리콘 기판을 식각하고 감광막(2, 5, 6)들을 제거하면, 기판에 미세한 소자분리영역의 트렌치가 형성한다.Subsequently, when the silicon substrate is etched and the photoresist layers 2, 5, and 6 are removed by using the remaining photoresist layers 2, 5, and 6 as etching masks as illustrated in FIG. .
이어서, 제1e도에 도시된 바와같이 열 산화(Oxidation) 공정, 또는 TEOS, HTO, SOG, BPSG, PSG와 같은 산화막을 증착하여 전체 구조 상부에 산화막(7)을 형성하고, 제1f도와 같이 전면 식각을 통해 트렌치 내부에만 산화막(7a)을 형성하여 소자분리를 완성한다.Subsequently, as shown in FIG. 1e, a thermal oxidation process or an oxide film such as TEOS, HTO, SOG, BPSG, and PSG is deposited to form an oxide film 7 over the entire structure. Through etching, an oxide film 7a is formed only in the trench to complete device isolation.
제1g도는 제1f도의 기판 상부 표면을 나타낸다.Figure 1g shows the substrate top surface of Figure 1f.
이상, 상기 설명한 바와 같이 이루어지는 본 발명은 LOCOS 공정보다 공정이 간단하고 제조 비용이 많이 절감될뿐만 아니라 최소한의 면적으로 소자분리가 가능하고, 또한 산화막 형성에 의해 발생하는 단차를 완전히 제거함으로써, 후속 공정을 용이하게 하고, 산화막 팽창에 의해 야기되는 중첩 오차가 없어지는 효과를 가져온다.As described above, the present invention made as described above is simpler than the LOCOS process, not only reduces manufacturing costs, but also enables device separation with a minimum area, and also completely eliminates steps generated by oxide film formation. And the effect of eliminating the overlapping error caused by oxide film expansion.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950031978A KR0172302B1 (en) | 1995-09-26 | 1995-09-26 | Method of manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950031978A KR0172302B1 (en) | 1995-09-26 | 1995-09-26 | Method of manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970018381A KR970018381A (en) | 1997-04-30 |
| KR0172302B1 true KR0172302B1 (en) | 1999-03-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950031978A KR0172302B1 (en) | 1995-09-26 | 1995-09-26 | Method of manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0172302B1 (en) |
-
1995
- 1995-09-26 KR KR1019950031978A patent/KR0172302B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970018381A (en) | 1997-04-30 |
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