KR0161723B1 - Forming method of fine pattern - Google Patents

Abstract

The present invention relates to a method of forming a fine pattern for highly integrated semiconductor devices. When the photosensitive film pattern is formed on the conductive layer having the inclined surface by the lower pattern, the exposed light is transmitted from the photosensitive film and reflected from the surface of the conductive layer. The photosensitive film in the exposure area is exposed. Subsequently, when the developing step is performed, a damaged photosensitive film pattern is obtained, and when the conductive layer pattern is formed using the mask, a problem arises in that the conductive layer pattern is poorly formed. Therefore, in the present invention, a planarization layer is formed on the conductive layer and a photoresist pattern is formed on the conductive layer. Then, the etching process is performed using the photoresist pattern, optionally overgrown the metal layer to some extent, and then the etching process is performed. As a result, a fine conductive layer pattern is formed without causing quenching or a short circuit, thereby improving reliability and yield of the semiconductor device, thereby enabling high integration of the semiconductor device.

Description

Micro pattern formation method of semiconductor device

1 is a cross-sectional view showing the formation of a semiconductor device fine pattern according to the prior art.

2A through 2D are cross-sectional views showing a micropattern forming process of a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11,21: semiconductor substrate 13,23: device isolation insulating film

15,25 gate oxide film 17,27 conductive layer for word line

19, 31: photoresist pattern 29: planarization layer

33: metal layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a fine pattern of a semiconductor device, and is a technique of forming a stable fine pattern by preventing a photoresist pattern used as a mask from being damaged by a step when forming a predetermined pattern in a semiconductor integrated circuit.

As semiconductor devices have been highly integrated, gaps between devices and devices, conductive layers, and conductive layers have decreased, and the step height has increased. Therefore, there is a problem that the formation of the fine pattern becomes more difficult as the degree of integration of the device increases.

The problem of the prior art will be described in detail with reference to FIG.

FIG. 1 is a cross-sectional view of sequentially forming a device isolation insulating film 13, a gate oxide film 15, a conductive layer 17, and a photosensitive film pattern 19 on a semiconductor substrate 11. The photoresist pattern 19 is formed by exposing and developing the photoresist using an exposure mask. At this time, the light L injected into the photoresist film during the exposure process causes diffuse reflection due to the inclination of the A portion, so that light is absorbed by the photoresist film in the non-exposed area and subjected to the development process. ) The side wall is damaged. Thus, when the conductive layer pattern is formed using the damaged photosensitive film pattern 9 as a mask, the conductive layer pattern of the correct size is not formed, and even a notching or a short circuit occurs to cause a defect of the transistor. This causes a problem of lowering the yield of the semiconductor element and lowering the reliability.

In order to solve the above problems, the negative photoresist film is more complicated than the positive photoresist film, and the adhesion, resolution, and service life are poor. .

Therefore, in the present invention, in order to form a fine pattern, by forming a stepped conductive layer, forming a planarization layer on top thereof, forming a photoresist pattern on top of the planarization layer, and cutting the insulating film using the photoresist pattern A planarization layer pattern is formed to expose the conductive layer. Then, the photoresist layer pattern is removed and a metal layer is selectively grown only on the conductive layer. Thereafter, an object of the present invention is to provide a method of forming a fine pattern of a semiconductor device, in which a fine conductive layer pattern is formed by an etching process using the metal layer.

Features of the method for forming a fine pattern of a semiconductor device for achieving the above object,

Sequentially forming a device isolation insulating film, a gate oxide film, a word line conductive layer, and a planarization layer on the semiconductor substrate;

Forming a photoresist pattern on the planarization layer;

Selectively etching the planarization layer using the photoresist pattern as a mask;

Forming a metal layer connected to the conductive layer by a selective growth method, but overgrowth to surround a predetermined portion of the planarization layer;

Forming a planarization layer pattern by selectively etching the planarization layer secondly using the metal layer as a mask;

Removing the metal layer by using an etching selectivity difference between the metal layer and the planarization layer pattern;

And forming a conductive layer pattern by an etching process using the planarization layer pattern as a mask.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are cross-sectional views illustrating a process of forming a fine pattern of a semiconductor device as an embodiment of the present invention.

FIG. 2A shows a device isolation insulating film 23 formed on a semiconductor substrate 21 on which a well is formed, followed by depositing a gate oxide film 25 and a conductive layer 27 for a word line. After the impurity is implanted into the layer 27 and the planarization layer 29 is formed as an insulating film thereon, a cross-sectional view showing the formation of the photoresist pattern 31 for forming a word line on the planarization layer 29. to be.

Here, the device isolation insulating film 23 is formed by LOCOS (LOCal Oxide Silicate, LOCOS) technology. The planarization layer 29 is a CVD oxide film or polyimide formed by S.O.G. (SOG: Spin On Glass, SOG), chemical vapor deposition (CVD) technology, which is easy to planarize. It is formed by.

In addition, the word line conductive layer 27 is formed of polycrystalline silicon, polycide, or the like.

In addition, the photosensitive film pattern 31 may be formed evenly on the planarization layer 29 even if there is a step difference between the device isolation insulating layers 23, without defects such as mismatching due to diffuse reflection.

In FIG. 2B, the planarization layer 29 is etched using the photoresist pattern 31 as a mask, and the photoresist pattern 31 is removed. A cross-sectional view of a selective growth of a metal layer 33 made of a tungsten layer on the conductive layer 27 for word lines is shown.

Here, the metal layer 33 is formed so as to apply a predetermined portion of the planarization layer 29 by overgrown the tungsten layer by the selective growth method on the conductive layer 27 for the word line. In this case, the conductive layer pattern to be formed later may be more finely formed by controlling the degree of overgrowth of the metal layer 33.

2C is a cross-sectional view illustrating the formation of the planarization layer 29 pattern by selectively etching the planarization layer 29 and removing the metal layer 33 by a wet method using the metal layer 33 as a mask.

In the wet method, the metal layer 33, the planarization layer 29 pattern adjacent thereto, and the conductive layer 27 for the word line are made using the difference in etching selectivity.

FIG. 2D is a cross-sectional view of the conductive layer 27 pattern formed by etching the word line conductive layer 27 and removing the flattening layer 29 pattern using the planarization layer 29 pattern as a mask. .

According to the present invention described above, it is possible to form a pattern that can prevent the naming or short-circuit in a simple process, and the size of the conductive layer pattern can be adjusted by controlling the degree of overgrowth of the metal layer. As a result, deterioration of the characteristics of the transistor or the wiring can be prevented, so that the reliability of the semiconductor device can be improved and the yield of the semiconductor device can be improved.

Claims (4)

Sequentially forming a device isolation insulating film, a gate oxide film, a word line conductive layer and a planarization layer on the semiconductor substrate, forming a photoresist pattern on the planarization layer, and using the photoresist pattern as a mask. Forming a metal layer connected to the conductive layer by a selective growth method, but overgrowing to cover a predetermined portion of the planarization layer, and selectively selecting the planarization layer using the metal layer as a mask. Etching to form a planarization layer pattern, removing the metal layer using an etching selectivity difference between the metal layer and the planarization layer pattern, and forming a conductive layer pattern by etching using the planarization layer pattern as a mask. Method for forming a fine pattern of a semiconductor device comprising a. The method of claim 1, wherein the word line conductive layer is formed of polysilicon or polysides. The method of claim 1, wherein the planarization layer is formed of any one of an SOG film, a CVD oxide film, and a polyimide film. The method of claim 1, wherein the metal layer is formed of a tungsten film.