KR100222749B1 - 반도체 기억회로의 데이터 유지시간 연장장치 및 연장방법 - Google Patents
반도체 기억회로의 데이터 유지시간 연장장치 및 연장방법 Download PDFInfo
- Publication number
- KR100222749B1 KR100222749B1 KR1019960002739A KR19960002739A KR100222749B1 KR 100222749 B1 KR100222749 B1 KR 100222749B1 KR 1019960002739 A KR1019960002739 A KR 1019960002739A KR 19960002739 A KR19960002739 A KR 19960002739A KR 100222749 B1 KR100222749 B1 KR 100222749B1
- Authority
- KR
- South Korea
- Prior art keywords
- potential
- memory cell
- period
- cell transistor
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP95-020149 | 1995-02-08 | ||
| JP95-020,149 | 1995-02-08 | ||
| JP2014995 | 1995-02-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960032489A KR960032489A (ko) | 1996-09-17 |
| KR100222749B1 true KR100222749B1 (ko) | 1999-10-01 |
Family
ID=12019104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960002739A Expired - Fee Related KR100222749B1 (ko) | 1995-02-08 | 1996-02-05 | 반도체 기억회로의 데이터 유지시간 연장장치 및 연장방법 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5654913A (enExample) |
| KR (1) | KR100222749B1 (enExample) |
| TW (1) | TW306001B (enExample) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3862333B2 (ja) * | 1996-12-10 | 2006-12-27 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| US5898633A (en) * | 1997-05-21 | 1999-04-27 | Motorola, Inc. | Circuit and method of limiting leakage current in a memory circuit |
| US6178121B1 (en) * | 1997-12-11 | 2001-01-23 | Seiko Epson Corporation | Semiconductor memory device, semiconductor device, and electronic apparatus using the semiconductor device |
| US6268748B1 (en) | 1998-05-06 | 2001-07-31 | International Business Machines Corp. | Module with low leakage driver circuits and method of operation |
| KR20000027646A (ko) * | 1998-10-28 | 2000-05-15 | 김영환 | 반도체 메모리 소자 |
| KR100363107B1 (ko) | 1998-12-30 | 2003-02-20 | 주식회사 하이닉스반도체 | 반도체메모리 장치 |
| US6185125B1 (en) * | 1999-12-15 | 2001-02-06 | Winbond Electronics Corp. | Circuit for measuring the data retention time of a dynamic random-access memory cell |
| US6646949B1 (en) | 2000-03-29 | 2003-11-11 | International Business Machines Corporation | Word line driver for dynamic random access memories |
| US6343044B1 (en) * | 2000-10-04 | 2002-01-29 | International Business Machines Corporation | Super low-power generator system for embedded applications |
| JP4262912B2 (ja) * | 2001-10-16 | 2009-05-13 | Necエレクトロニクス株式会社 | 半導体記憶装置 |
| KR100476891B1 (ko) * | 2002-04-18 | 2005-03-17 | 삼성전자주식회사 | 반도체 메모리 장치의 동작 모드에 따라 가변적인리스토어 시간을 갖는 리프레쉬 회로 및 그 리프레쉬 방법 |
| WO2005024834A2 (en) * | 2003-09-05 | 2005-03-17 | Zmos Technology, Inc. | Low voltage operation dram control circuits |
| US7095669B2 (en) * | 2003-11-07 | 2006-08-22 | Infineon Technologies Ag | Refresh for dynamic cells with weak retention |
| US6992917B2 (en) * | 2003-12-15 | 2006-01-31 | International Business Machines Corporation | Integrated circuit with reduced body effect sensitivity |
| US7375402B2 (en) * | 2004-07-07 | 2008-05-20 | Semi Solutions, Llc | Method and apparatus for increasing stability of MOS memory cells |
| US7082073B2 (en) * | 2004-12-03 | 2006-07-25 | Micron Technology, Inc. | System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices |
| KR100673901B1 (ko) * | 2005-01-28 | 2007-01-25 | 주식회사 하이닉스반도체 | 저전압용 반도체 메모리 장치 |
| KR101152497B1 (ko) * | 2005-06-30 | 2012-06-04 | 엘지디스플레이 주식회사 | 액정표시소자 |
| JP5078118B2 (ja) * | 2006-10-23 | 2012-11-21 | パナソニック株式会社 | 半導体記憶装置 |
| US8004920B2 (en) | 2007-05-29 | 2011-08-23 | Micron Technology, Inc. | Power saving memory apparatus, systems, and methods |
| KR100924205B1 (ko) * | 2008-05-28 | 2009-10-29 | 주식회사 하이닉스반도체 | 반도체 기억 장치 |
| US8605489B2 (en) * | 2011-11-30 | 2013-12-10 | International Business Machines Corporation | Enhanced data retention mode for dynamic memories |
| JP2015118724A (ja) | 2013-11-13 | 2015-06-25 | 株式会社半導体エネルギー研究所 | 半導体装置及び半導体装置の駆動方法 |
| KR102324627B1 (ko) | 2014-10-31 | 2021-11-10 | 삼성전자주식회사 | 자기 저항 소자를 포함하는 반도체 소자 |
| KR20180077973A (ko) * | 2016-12-29 | 2018-07-09 | 삼성전자주식회사 | 리프레쉬 동작을 제어하는 메모리 장치 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04179164A (ja) * | 1990-11-08 | 1992-06-25 | Sharp Corp | 半導体メモリ装置 |
| US5253205A (en) * | 1991-09-05 | 1993-10-12 | Nippon Steel Semiconductor Corporation | Bit line and cell plate clamp circuit for a DRAM |
| JPH05291534A (ja) * | 1992-04-14 | 1993-11-05 | Hitachi Ltd | 電荷蓄積素子を有する半導体装置 |
| JPH0611156A (ja) * | 1992-06-26 | 1994-01-21 | Matsushita Electric Works Ltd | 蓄冷システム |
| US5488587A (en) * | 1993-10-20 | 1996-01-30 | Sharp Kabushiki Kaisha | Non-volatile dynamic random access memory |
-
1996
- 1996-01-29 TW TW085101075A patent/TW306001B/zh active
- 1996-02-05 KR KR1019960002739A patent/KR100222749B1/ko not_active Expired - Fee Related
- 1996-02-06 US US08/597,250 patent/US5654913A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR960032489A (ko) | 1996-09-17 |
| TW306001B (enExample) | 1997-05-21 |
| US5654913A (en) | 1997-08-05 |
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