KR100218342B1 - Method for contact filling and metal wire forming of semiconductor - Google Patents

Method for contact filling and metal wire forming of semiconductor Download PDF

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Publication number
KR100218342B1
KR100218342B1 KR1019960066627A KR19960066627A KR100218342B1 KR 100218342 B1 KR100218342 B1 KR 100218342B1 KR 1019960066627 A KR1019960066627 A KR 1019960066627A KR 19960066627 A KR19960066627 A KR 19960066627A KR 100218342 B1 KR100218342 B1 KR 100218342B1
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South Korea
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plug
forming
semiconductor
contact
via hole
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KR1019960066627A
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Korean (ko)
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KR19980048086A (en
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김정주
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구본준
엘지반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체의 컨택매립 및 배선형성방법에 관한 것으로, 종래 기술에 의한 반도체의 컨택매립 및 배선형성방법은 돌출되거나 잔류된 W플러그 등을 제거하기 위해서 반드시 에치백 공정이나 화학적 또는 기계적인 연마가 필요하게 되므로 공정수의 증가와 함께 생산성이 떨어지게 되는 문제점을 초래하였다. 이러한 문제점을 해결하기 위하여 본 발명은 아래 도면에 도시된 바와 같이, 깊이가 가장 깊은 비아홀을 갖는 컨택트 핀 즉, FG를 기준으로 하여 소정의 높이를 갖는 W플러그를 형성한 후, 상기 A1을 Cold-Hot Deposition하여 A1플러그와 그 A1플러그를 연결하는 배선을 형성하므로써, 상기 W플러그가 돌출되지 않아 그 W플러그를 제거하기 위해 에치백 공정이나 화학적 또는 기계적인 연마가 필요없게 되어 공정수의 절감됨과 아울러 상기 반도체의 생산성이 향상되게 되는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for filling a contact and forming a wiring of a semiconductor. The method for forming a contact and forming a wiring of a semiconductor according to the related art requires an etch back process or chemical or mechanical polishing to remove protruding or remaining W plugs. Since it is necessary to increase the number of processes has caused a problem that the productivity falls. In order to solve this problem, the present invention, as shown in the drawings below, after forming a contact pin having the deepest via hole, that is, a W plug having a predetermined height based on FG, Cold-A1 By forming hot wires to connect the A1 plug with the A1 plug, the W plug does not protrude, eliminating the need for an etch back process or chemical or mechanical polishing to remove the W plug. There is an effect that the productivity of the semiconductor is improved.

Description

반도체의 컨택매립 및 배선형성방법Contact embedding and wiring formation method of semiconductor

본 발명은 반도체의 컨택매립 및 배선형성방법에 관한 것으로, 특히 깊이가 다른 다수개의 컨택이 형성되어 있는 기판의 한 컨택을 기준으로 하여 텅스텐(W) 또는 알류미늄(A1)을 선택적으로 매립하거나 배선을 형성하여 상기 기판의 제조공정을 단순화 함과 아울러 생산성을 향상할 수 있도록 한 반도체의 컨택매립 및 배선형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for filling a contact and forming a wiring of a semiconductor, and in particular, selectively embeds tungsten (W) or aluminum (A1) or wires based on a contact of a substrate on which a plurality of contacts having different depths are formed. The present invention relates to a method for forming a contact buried and wiring of a semiconductor, which is formed to simplify the manufacturing process of the substrate and to improve productivity.

일반적으로, 반도체 제조공정시에 컨택을 형성하여 그 컨택을 매립하거나 상기 컨택과 컨택을 연결하는 배선을 형성하는데 이러한 컨택매립과 배선형성방법을 상기 제1도와 제2도를 참조하여 설명하면 다음과 같다. 상기 제1도에 도시된 바와 같이 깊이가 다른 컨택인 다수개의 FG와 UG 그리고 TG가 형성되고, 그 컨택이 위치하는 곳에는 소정의 폭을 갖는 비아(Via)홀(la)이 구비되어 있는 기판(1)이 형성되어 있다.In general, in the semiconductor manufacturing process, a contact is formed to fill a contact or to form a wiring connecting the contact and the contact. A method of forming a contact and wiring is described with reference to FIGS. 1 and 2 as follows. same. As shown in FIG. 1, a substrate having a plurality of FG, UG, and TG, which are contacts having different depths, is formed, and a via hole la having a predetermined width is provided where the contact is located. (1) is formed.

상기와 같이 형성된 기판(1)은 상기 제2도에 도신된 바와 같이, 상기 비아홀(la)에 Ti/TiN 배리어(Barrier)(1b)를 형성하고, 그 배리어(1b)가 형성된 비아홀(1a)에 소정의 두께를 갖는 W를러그(Plug)(lc)를 형성한다.As described above with reference to FIG. 2, the substrate 1 formed as described above forms a Ti / TiN barrier 1b in the via hole la, and the via hole 1a in which the barrier 1b is formed. W having a predetermined thickness is formed into a lug lc.

이때 상기 W플러그(lc)는 깊이가 가장 깊은 컨택인 상기 FG를 기준으로 형성하고, 상기 비아홀(la)로 돌출되거나 잔류된 W플러그(lc) 즉, UG 또는 TG 컨택이 있는 비아홀(la)부의 W플러그(lc)는 화학적 또는 기계적인 연마(CMP : Chemical Mechanical Polishing)를 한 후, 에치백(Etch Back)하여 일정한 높이를 갖도록 형성하고, 다시 상기 W플러그(lc) 위에 Ti/TiN 배리어(lb')를 형성한다.At this time, the W plug lc is formed based on the FG which is the deepest contact, and the W plug lc protruding or remaining into the via hole la, that is, the via hole la having the UG or TG contact. The W plug lc is formed to have a constant height by chemical mechanical polishing (CMP), and then etched back, and again, a Ti / TiN barrier (lb) on the W plug lc. Form ').

또, 상기 W플러그(lc) 위에 형성된 Ti/TiN 배리어(lb')를 소정의 깊이로 에칭(Etching)한 후, 알루미늄 금속을 스퍼터링(Sputtering)이나 리플로우(Reflow)하여 상기 컨택을 매립하거나 연결하는 배선(ld)을 형성하게 되는 것이다.Further, after etching the Ti / TiN barrier lb 'formed on the W plug lc to a predetermined depth, the contact is buried or connected by sputtering or reflowing aluminum metal. The wiring ld is formed.

도면상의 미설명 부호 le는 IMD이다.Reference numeral le in the drawings is IMD.

그러나, 상기와 같은 방법은 돌출되거나 잔류된 W플러그 등을 제거하기 위해서 반드시 에치백 공정이나 화학적 또는 기계적인 연마가 필요하게 되므로 공정수의 증가와 함께 생산성이 떨어지게 되는 문제점을 초래하였다.However, the method as described above requires an etch back process or chemical or mechanical polishing to remove the protruding or remaining W plugs, thereby causing a problem in that productivity decreases with an increase in the number of processes.

따라서, 본 발명은 상기의 문제점을 해결하여 공정수를 줄임과 아울러 생산성을 향상할 수 있는 반도체의 컨택매립 및 배선형성방법을 제공함에 있다.Accordingly, the present invention is to provide a method for forming a contact buried and wiring of a semiconductor which can solve the above problems and reduce the number of processes and improve productivity.

제1도는 일반적인 기판의 종단구조를 보인 단면도.1 is a cross-sectional view showing a termination structure of a general substrate.

제2도는 종래 기술에 의한 반도체의 컨택매립 및 배선형성을 도시한 설명도.2 is an explanatory diagram showing contact embedding and wiring formation of a semiconductor according to the prior art.

제3도는 본 발명에 의한 반도체의 컨택매립 및 배선형성을 도시한 설명도.3 is an explanatory diagram showing contact filling and wiring formation of a semiconductor according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 기판 11a, 11a' : 배리어11 substrate 11a, 11a 'barrier

11b : W 플러그 11c : A1 플러그11b: W plug 11c: A1 plug

11d : 배선11d: wiring

본 발명의 목적은 컨택이 있는 단차진 다수개의 바아홀이 형성된 기판의 바아홀에 Ti/TiN 배리어를 형성하는 단계와, 그 배리어가 형성된 깊이가 가장 깊은 비아홀을 기준으로 하여 깊이가 가장 낮은 비아홀에 넘치지 않도록 W플러그를 증작하는 단계와, 또 상기 W플러그가 증착된 비아홀에 Ti/TiN 배리어를 형성하는 단계와, 상기 W플러그와 Ti/TiN 배리어가 형성된 비아홀에 A1플러그와 그 Al플러그를 연결하는 배선을 형성하는 단계로 진행하는 것을 특징으로 하는 반도체의 컨택매립 및 배선형성방법에 의하여 달성된다.It is an object of the present invention to form a Ti / TiN barrier in a bar hole of a substrate on which a plurality of stepped bar holes are formed, and a via hole having the lowest depth based on the deepest via hole in which the barrier is formed. Forming a W plug so as not to overflow, and forming a Ti / TiN barrier in the via hole on which the W plug is deposited, and connecting the A1 plug and the Al plug to the via hole in which the W plug and the Ti / TiN barrier are formed. It is achieved by the method of forming a contact and wiring formation of a semiconductor, characterized in that the step of forming a wiring.

다음은, 본 발명에 의한 반도체의 컨택매립 및 배선형성방법의 일실시예를 첨부된 도면에 의거하여 상세하게 설명한다.Next, an embodiment of a method for contact filling and wiring formation of a semiconductor according to the present invention will be described in detail with reference to the accompanying drawings.

제3도는 본 발명에 의한 반도체의 컨택매립 및 배선형성을 도시한 설명도3 is an explanatory diagram showing contact filling and wiring formation of a semiconductor according to the present invention.

상기 제3도에 도시된 바와 같이, 본 발명에 의한 반도체의 컨택매립 및 배선형성방법은, 깊이가 다른 컨택인 다수개의 FG와 UG 그리고 TG가 형성되고, 그 컨택이 위치하는 곳에는 소정의 폭을 갖는 비아(Via)홀이 구비되어 있는 기판(11)에, 먼저 상기 기판(11)에 형성되어 있는 비아홀에 Ti/TiN 배리어(11a)를 형성하고, 그 배리어(11a)가 형성된 깊이가 가장 깊은 비아홀을 갖는 컨택트 핀 즉, FG를 기준으로 하여 상기 비아홀에 넘치지 않도록 W를 증착하여 소정의 높이를 갖는 W플러그(11b)를 형성한다.As shown in FIG. 3, according to the present invention, in the method of forming a contact in a semiconductor and forming a wire, a plurality of FGs, UGs, and TGs, which are contacts having different depths, are formed, and a predetermined width is provided where the contacts are located. First, a Ti / TiN barrier 11a is formed in a via hole formed in the substrate 11 in a substrate 11 having a via hole having a via hole, and the depth at which the barrier 11a is formed is the greatest. A W pin 11b having a predetermined height is formed by depositing W so as not to overflow the via hole based on the FG, that is, a contact pin having a deep via hole.

또, 상기 W플러그(11b)가 증착된 비아홀에 Ti/TiN 배리어(11a')를 형성하고, 상기 W플러그(11b)와 Ti/TiN배리어(11a')가 형성된 비아홀에 A1을 Cold-Hot Deposition 하여 A1플러그(11c)와 그 A1플러그(11c)를 연결하는 배선(11d)을 형성한다.In addition, a Ti / TiN barrier 11a 'is formed in the via hole in which the W plug 11b is deposited, and A1 is cold-hot deposited in the via hole in which the W plug 11b and the Ti / TiN barrier 11a' are formed. Thus, the wiring 11d connecting the A1 plug 11c and the A1 plug 11c is formed.

도면상의 미설명 부호 11e는 IMD이다.Reference numeral 11e in the drawings is an IMD.

상기와 같이, 깊이가 가장 깊은 비아홀을 갖는 컨택트 핀 즉, FG를 기준으로 하여 소정의 높이를 갖는 W플러그를 형성한 후, 상기 A1을 Cold-Hot Deposition하여 A1플러그와 그 A1플러그를 연결하는 배선을 형성하므로써, 상기 W플러그가 돌출되지 않아 그 W플러그를 제거하기 위해 에치백 공정이나 화학적 또는 기계적인 연마가 필요없게 되어 공정수의 절감됨과 아울러 상기 반도체의 생산성이 향상되게 되는 효과가 있다.As described above, after forming a contact pin having the deepest via hole, that is, a W plug having a predetermined height based on the FG, the wiring connecting the A1 plug and the A1 plug by cold-hot deposition of the A1. Since the W plug does not protrude, there is no need for an etch back process or chemical or mechanical polishing to remove the W plug, thereby reducing the number of processes and improving the productivity of the semiconductor.

Claims (1)

컨택이 있는 단차진 다수개의 비아홀이 형성된 기판의 비아홀에 Ti/TiN 베리어를 형성하는 단계와, 그 베리어가 형성된 깊이가 가장 깊은 비아홀을 기준으로 하여 깊이가 가장 낮은 비아홀에 넘치지 않도록 W플러그를 증착하는 단계와, 또 사이 W플러그가 증착된 바아홀에 Ti/TiN 베리어를 형성하는 단계와, 상기 W플러그와 Ti/TiN 베리어가 형성된 비아홀에 A1플러그와 그 A1플러그를 연결하는 배선을 형성하는 단계로 진행하는 것을 특징으로 하는 반도체의 컨택매립 및 배선형성방법.Forming a Ti / TiN barrier in a via hole of a substrate having a plurality of stepped via holes, and depositing a W plug so that the barrier does not overflow the lowest via hole based on the deepest via hole. And forming a Ti / TiN barrier in the bar hole in which the W plug is deposited, and forming a wiring connecting the A1 plug and the A1 plug in the via hole in which the W plug and the Ti / TiN barrier are formed. A contact embedding and wiring forming method for a semiconductor, characterized in that the progress.
KR1019960066627A 1996-12-17 1996-12-17 Method for contact filling and metal wire forming of semiconductor KR100218342B1 (en)

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