KR100208439B1 - Method of forming polysilicon layer in semiconductor device - Google Patents

Method of forming polysilicon layer in semiconductor device Download PDF

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KR100208439B1
KR100208439B1 KR1019950010983A KR19950010983A KR100208439B1 KR 100208439 B1 KR100208439 B1 KR 100208439B1 KR 1019950010983 A KR1019950010983 A KR 1019950010983A KR 19950010983 A KR19950010983 A KR 19950010983A KR 100208439 B1 KR100208439 B1 KR 100208439B1
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forming
silicon
amorphous silicon
polysilicon layer
silicon substrate
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KR1019950010983A
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Korean (ko)
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권오성
김진태
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김영환
현대전자산업주식회사
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Priority to KR1019950010983A priority Critical patent/KR100208439B1/en
Priority to JP8106869A priority patent/JPH08306642A/en
Priority to GB9608822A priority patent/GB2300517B/en
Priority to DE19617833A priority patent/DE19617833A1/en
Priority to CN96107491A priority patent/CN1083158C/en
Priority to TW085105355A priority patent/TW291572B/zh
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Publication of KR100208439B1 publication Critical patent/KR100208439B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

본 발명은 반도체 소자의 폴리실리콘층 형성방법에 관한 것으로, 도전층의 접촉저항을 감소시키며, 폴리실리콘의 그레인크기를 증가시키기 위하여 플라즈마(Plasma)처리를 통해 노출된 실리콘기판상에 잔류되는 자연산화막 및 이물질을 제거한 후 비정질실리콘을 증착하고 실리콘이온을 주입한 다음 재결정화시키므로써 소자의 전기적특성이 향상될 수 있도록 한 반도체 소자의 폴리실리콘층 형성방법에 관한 것이다.The present invention relates to a method for forming a polysilicon layer of a semiconductor device, and to reduce the contact resistance of the conductive layer, and to increase the grain size of the polysilicon, a natural oxide film remaining on the exposed silicon substrate through the plasma (Plasma) treatment And a method for forming a polysilicon layer of a semiconductor device to improve the electrical characteristics of the device by removing foreign substances, depositing amorphous silicon, injecting silicon ions, and recrystallizing the same.

Description

반도체 소자의 폴리실리콘층 형성방법Polysilicon layer formation method of semiconductor device

제1a 및 제1b도는 종래 반도체 소자의 폴리실리콘층 형성방법을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a method of forming a polysilicon layer of a conventional semiconductor device.

제2a 내지 제2d도는 본 발명에 따른 반도체 소자의 폴리실리콘층 형성방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of a device for explaining a method of forming a polysilicon layer of a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘기판 2 : 접합부1: silicon substrate 2: junction

3 : 절연층 4 : 콘택홀3: insulation layer 4: contact hole

5 및 6A : 폴리실리콘층 6 : 비정질실리콘5 and 6A polysilicon layer 6: amorphous silicon

10 : 자연산화막10: natural oxide film

본 발명은 반도체 소자의 폴리실리콘층 형성방법에 관한 것으로, 특히 플라즈마(Plasma)처리를 통해 노출된 실리콘기판상에 잔류되는 자연산화막 및 이물질을 제거한 후 비정질실리콘을 증착하고 실리콘이온을 주입한 다음 재결정화시키므로써 소자의 전기적특성이 향상될 수 있도록 한 반도체 소자의 폴리실리콘층 형성방법에 관한 것이다.The present invention relates to a method for forming a polysilicon layer of a semiconductor device, and in particular, after removing a natural oxide film and foreign substances remaining on a silicon substrate exposed through plasma treatment, depositing amorphous silicon, injecting silicon ions, and recrystallization. The present invention relates to a method for forming a polysilicon layer of a semiconductor device so that the electrical properties of the device can be improved.

일반적으로 반도체 소자의 제조공정에서 폴리실리콘층은 도전층으로 이용된다. 그러면 종래 반도체 소자의 폴리실리콘층 형성방법을 제1a 및 제1b도를 통해 설명하면 다음과 같다.In general, the polysilicon layer is used as the conductive layer in the manufacturing process of the semiconductor device. A method of forming a polysilicon layer of a conventional semiconductor device will now be described with reference to FIGS. 1A and 1B.

제1a 및 제1b도는 종래 반도체 소자의 폴리실리콘층 형상방법을 설명하기 위한 소자의 단면도로서,1A and 1B are cross-sectional views of a device for explaining a method of forming a polysilicon layer of a conventional semiconductor device.

제1a도는 접합부(2)가 형성된 실리콘기판(1)상에 절연층(3)을 형성한 후 콘택홀마스크(Contact hole Mask)를 이용한 사진 및 식각공정을 통해 상기 절연층(3)을 패터닝하여 상기 접합부(2)상부의 실리콘기판(1)이 노출되도록 콘택홀(4)을 형성한 상태의 단면도인데, 이때 노출된 실리콘기판(1)상에 자연산화막(10)이 성장된다.In FIG. 1A, after forming the insulating layer 3 on the silicon substrate 1 on which the junction part 2 is formed, the insulating layer 3 is patterned through a photolithography and an etching process using a contact hole mask. The contact hole 4 is formed in a state in which the silicon substrate 1 on the junction 2 is exposed, and the natural oxide film 10 is grown on the exposed silicon substrate 1.

제1b도는 상기 자연산화막(10)을 제거하기 위하여 BOE 또는 HF용액을 사용하여 습식세정(Wet cleaning)공정을 실시한 후 300℃의 반응로내에서 상기 접합부(2)와 접속되도록 폴리실리콘층(5)을 형성시킨 상태의 단면도인데, 이와같은 방법에 의해 형성된 상기 폴리실리콘층(5)은 그레인(Grain: A)의 크기가 예를들어 0.1 내지 0.5㎛정도로 작기 때문에 전자(Electron)의 이동도(Mobility) 또는 전도도가 저하되는 단점이 있으며, 또한 상기 습식세정공정시 완전히 제거되지 않고 잔류되는 자연산화막(10)으로 인해 접촉(Contact)저항이 증대되어 소자의 전기적 특성이 저하된다.Figure 1b is a polysilicon layer (5) to be connected to the junction 2 in a 300 ° C reactor after a wet cleaning process using a BOE or HF solution to remove the natural oxide film 10 ) Is a cross-sectional view of the polysilicon layer 5 formed by the above method, and the mobility of electrons (Electron) is small because the size of grain (A) is small, for example, about 0.1 to 0.5 μm. Mobility or conductivity is reduced, and due to the natural oxide film 10 that is not completely removed during the wet cleaning process, the contact resistance is increased, thereby lowering the electrical characteristics of the device.

따라서 본 발명은 플라즈마 처리를 통해 노출된 실리콘기판상에 잔류되는 자연산화막 및 이물질을 제거한 후 비정질실리콘을 증착하고 실리콘이온을 주입한 다음 재결정화시키므로써 상기한 단점을 해소할 수 있는 반도체 소자의 폴리실리콘층 형성방법을 제공하는데 그 목적이 있다.Therefore, the present invention removes the natural oxide film and foreign matter remaining on the exposed silicon substrate through plasma treatment, deposits amorphous silicon, injects silicon ions, and recrystallizes the poly-semi-conductor of the semiconductor device. It is an object to provide a method for forming a silicon layer.

상기한 목적을 달성하기 위한 본 발명은 접합부가 형성된 실리콘기판상에 절연층을 형성한 후 콘택홀마스크를 이용한 사진 및 식각공정을 통해 상기 절연층을 패터닝하여 상기 접합부상부의 실리콘기판이 노출되도록 콘택홀을 형성하는 단계와, 상기 단계로부터 노출된 실리콘기판상에 성장된 자연산화막을 제거하기 위하여 습식세정공정을 실시하고 플라즈마처리를 실시한 다음 상기 실리콘기판을 증착반응로내부로 로딩하는 단계와, 상기 단계로부터 소정의 온도범위에서 비정질실리콘을 증착한 후 소정의 이온주입량 및 이온주입에너지를 이용하여 상기 비정질실리콘내에 실리콘이온을 주입시키는 단계와, 상기 단계로부터 상기 비정질실리콘을 재결정화시키기 위하여 열처리공정을 실시하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is formed by forming an insulating layer on the silicon substrate on which the junction is formed, and then patterning the insulating layer through a photo-etching process using a contact hole mask to expose the silicon substrate on the junction portion. Forming a hole, performing a wet cleaning process and performing a plasma treatment to remove the native oxide film grown on the silicon substrate exposed from the step, and then loading the silicon substrate into the deposition reactor; Depositing amorphous silicon at a predetermined temperature range from the step, and implanting silicon ions into the amorphous silicon using a predetermined ion implantation amount and ion implantation energy; and from the step, a heat treatment process for recrystallizing the amorphous silicon. Characterized in that the step consisting of.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제2a 내지 제2d도는 본 발명에 따른 반도체 소자의 폴리실리콘층 형성방법을 설명하기 위한 소자의 단면도로서,2A through 2D are cross-sectional views of a device for explaining a method of forming a polysilicon layer of a semiconductor device according to the present invention.

제2a도는 접합부(2)가 형성된 실리콘기판(1)상에 절연층(3)을 형성한 후 콘택홀마스크를 이용한 사진 및 식각공정을 통해 상기 절연층(3)을 패터닝하여 상기 접합부(2)상부의 실리콘기판(1)이 노출되도록 콘택홀(4)을 형성한 상태의 단면도인데, 이때 노출된 실리콘기판(1)상에 자연산화막(10)이 성장된다.FIG. 2A illustrates that the insulating layer 3 is formed on the silicon substrate 1 on which the junction part 2 is formed, and then patterned to form the insulating layer 3 through a photolithography and an etching process using a contact hole mask. The contact hole 4 is formed so that the upper silicon substrate 1 is exposed. In this case, the natural oxide film 10 is grown on the exposed silicon substrate 1.

제2b도는 상기 자연산화막(10)을 제거하기 위하여 BOE 또는 HF용액을 사용하여 습식세정공정을 실시하고, CF4가스를 이용한 플라즈마처리를 20 내지 40초(sec) 정도 실시한 다음 대기(공기)상태의 반응로내부에 N2가스를 공급하여 산소의 농도를 감소시킨 상태에서 상기 실리콘기판(1)을 상기 반응로내부로 로딩(Loading)한다. 이후 560 내지 580℃의 온도범위에서 SiH4가스의 열분해를 이용한 저압화학기상증착(LPCVD) 방법으로 비정질실리콘(Amorphous Si; 6)을 1000 내지 3000Å 정도의 두께로 증착한 상태의 단면도인데, 상기 CF4가스를 이용한 플라즈마처리는 상기 습식 세정시 완전히 제거되지 않고 잔류되는 자연산화막 및 폴리실리콘층 형성시 그레인성장의 핵이되는 O2및 H2등과 같은 이물질을 완전히 제거시키기 위한 것이며, 상기 실리콘기판(1)의 로딩시 N2가스를 공급하여 반응로내부의 산소농도를 낮추기 때문에 로딩되는 과정에서 산화막의 성장을 억제시킨다.FIG. 2b is a wet cleaning process using BOE or HF solution to remove the natural oxide film 10, and plasma treatment using CF 4 gas for about 20 to 40 seconds (sec) and then in an air (air) state. The silicon substrate 1 is loaded into the reactor in a state where the concentration of oxygen is reduced by supplying N 2 gas into the reactor. Thereafter, a cross-sectional view of amorphous silicon (Amorphous Si) 6 deposited at a thickness of about 1000 to 3000 Pa by low pressure chemical vapor deposition (LPCVD) using thermal decomposition of SiH 4 gas at a temperature range of 560 to 580 ° C., CF Plasma treatment using 4 gas is to completely remove foreign substances such as O 2 and H 2 , which are nuclei of grain growth when forming a natural oxide film and a polysilicon layer, which are not completely removed during the wet cleaning, and the silicon substrate ( When loading 1), N 2 gas is supplied to lower the oxygen concentration in the reactor, thereby inhibiting the growth of the oxide film during the loading process.

제2c도는 1015Cm-2정도의 상태를 갖는 이온주입량(Dose) 및 소정의 이온주입 에너지(Energy)를 이용하여 상기 비정질실리콘(6)에 실리콘이온을 주입시키는 상태의 단면도이다.FIG. 2C is a cross-sectional view of a state in which silicon ions are implanted into the amorphous silicon 6 using an ion implantation dose having a state of about 10 15 Cm −2 and a predetermined ion implantation energy.

제2d도는 500 내지 700℃의 온도 및 N2가스분위기 상태에서 열처리공정을 실시하여 상기 비정질실리콘(6)을 재결정화(Recrystallization)시키므로써 폴리실리콘층(6A)이 형성된 상태의 단면도인데, 이때 상기 CF4가스를 이용한 플라즈마처리에 의해 그레인성장의 핵이되는 이물질이 완전히 제거됨으로 인해 그레인(B)의 성장이 최대화되고, 상기 비정질실리콘에 주입된 실리콘이온에 의해 내부의 축적에너지가 증가되어 그레인(B)의 크기은 매우 커지게 된다. 참고적으로 이와같은 방법을 이용하면 1㎛ 이상의 크기를 갖는 그레인을 얻을 수 있다.FIG. 2d is a cross-sectional view of a polysilicon layer 6A formed by recrystallization of the amorphous silicon 6 by performing a heat treatment process at a temperature of 500 to 700 ° C. and an N 2 gas atmosphere. Plasma treatment using CF 4 gas completely removes foreign matter, which is the nucleus of grain growth, and maximizes the growth of grain B, and the internal accumulated energy is increased by the silicon ions injected into the amorphous silicon. The size of B) becomes very large. For reference, using this method, grains having a size of 1 μm or more can be obtained.

상술한 바와같이 본 발명에 의하면 비정질실리콘을 증착하기전에 자연산화막을 완전히 제거시켜 접촉저항을 감소시키고, 실리콘이온주입 및 재결정화에 의해 그레인의 크기가 최대화되도록 하여 전자의 이동도 및 전도도를 증가시키므로써 소자의 전기적 특성이 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, before the deposition of amorphous silicon, the natural oxide film is completely removed to reduce contact resistance, and the size of grain is maximized by silicon ion implantation and recrystallization, thereby increasing electron mobility and conductivity. There is an excellent effect that the electrical characteristics of the device can be improved.

Claims (9)

반도체 소자의 폴리실리콘층 형성방법에 있어서, 접합부가 형성된 실리콘기판상에 절연층을 형성한 후 콘택홀마스크를 이용한 사진 및 식각공정을 통해 상기 절연층을 패터닝하여 상기 접합부상부의 실리콘기판이 노출되도록 콘택홀을 형성하는 단계와, 상기 단계로부터 노출된 실리콘기판상에 성장된 자연산화막을 제거하기 위하여 습식세정공정을 실시하고 플라즈마처리를 실시한 다음 상기 실리콘기판을 증착반응로내부로 로딩하는 단계와, 상기 단계로부터 소정의 온도범위에서 비정질실리콘을 증착한 후 소정의 이온주입량 및 이온주입에너지를 이용하여 상기 비정질실리콘내에 실리콘이온을 주입시키는 단계와, 상기 단계로부터 상기 비정질실리콘을 재결정화시키기 위하여 열처리공정을 실시하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.In the method of forming a polysilicon layer of a semiconductor device, after forming an insulating layer on the silicon substrate on which the junction is formed, the insulating layer is patterned by photolithography and etching using a contact hole mask to expose the silicon substrate on the junction. Forming a contact hole, performing a wet cleaning process to remove the natural oxide film grown on the silicon substrate exposed from the step, performing a plasma treatment, and then loading the silicon substrate into the deposition reactor; Depositing amorphous silicon at a predetermined temperature range from the step and injecting silicon ions into the amorphous silicon using a predetermined ion implantation amount and ion implantation energy; and a heat treatment process for recrystallizing the amorphous silicon from the step A half characterized by consisting of Polysilicon layer forming method of the conductor element. 제1항에 있어서, 상기 습식세정공정시 BOE용액을 사용하는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.The method of claim 1, wherein the BOE solution is used in the wet cleaning process. 제1 또는 제2항에 있어서, 상기 습식세정공정시 HF용액을 사용하는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.The method of forming a polysilicon layer of a semiconductor device according to claim 1 or 2, wherein an HF solution is used during the wet cleaning process. 제1항에 있어서, 상기 플라즈마처리는 CF4가스를 이용하며, 20 내지 40초동안 실시되는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.The method of claim 1, wherein the plasma treatment is performed using CF 4 gas and is performed for 20 to 40 seconds. 제1항에 있어서, 상기 실리콘기판을 증착반응로내부로 로딩하는 단계에서 반응로내부의 산소농도를 감소시키기 위하여 N2가스를 공급하는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.The method of claim 1, wherein in the loading of the silicon substrate into the deposition reactor, N 2 gas is supplied to reduce the oxygen concentration in the reactor. 제1항에 있어서, 상기 비정질실리콘은 560 내지 580℃의 온도범위에서 SiH4가스의 열분해를 이용한 저압화학기상증착방법에 의해 증착되는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.The method of claim 1, wherein the amorphous silicon is deposited by a low pressure chemical vapor deposition method using pyrolysis of SiH 4 gas in a temperature range of 560 to 580 ° C. 7 . 제1 또는 제6항에 있어서, 상기 비정질실리콘은 1000 내지 3000Å의 두께로 증착되는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.7. The method of claim 1 or 6, wherein the amorphous silicon is deposited to a thickness of 1000 to 3000 GPa. 제1항에 있어서, 상기 실리콘이온은 1015Cm-2정도의 상태를 갖는 이온주입량으로 주입되는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.The method of claim 1, wherein the silicon ions are implanted at an ion implantation amount having a state of about 10 15 Cm −2 . 제1항에 있어서, 상기 비정질실리콘을 재결정화시키기 위한 열처리공정은 500 내지 700℃의 온도 및 N2가스분위기 상태에서 실시되는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 형성방법.The method of claim 1, wherein the heat treatment process for recrystallizing the amorphous silicon is performed at a temperature of 500 to 700 ° C. and an N 2 gas atmosphere.
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GB9608822A GB2300517B (en) 1995-05-04 1996-04-30 Method of manufacturing a semiconductor device
DE19617833A DE19617833A1 (en) 1995-05-04 1996-05-03 Method of manufacturing a semiconductor device
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