JPH08306642A - Polysilicon layer formation method of semiconductor element - Google Patents
Polysilicon layer formation method of semiconductor elementInfo
- Publication number
- JPH08306642A JPH08306642A JP8106869A JP10686996A JPH08306642A JP H08306642 A JPH08306642 A JP H08306642A JP 8106869 A JP8106869 A JP 8106869A JP 10686996 A JP10686996 A JP 10686996A JP H08306642 A JPH08306642 A JP H08306642A
- Authority
- JP
- Japan
- Prior art keywords
- forming
- semiconductor device
- polysilicon layer
- silicon
- amorphous silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 62
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims description 100
- 239000004065 semiconductor Substances 0.000 title claims description 61
- 230000015572 biosynthetic process Effects 0.000 title claims 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 74
- 239000010703 silicon Substances 0.000 claims abstract description 74
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 60
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000004140 cleaning Methods 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 19
- -1 silicon ions Chemical class 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000005979 thermal decomposition reaction Methods 0.000 claims abstract description 9
- 238000006243 chemical reaction Methods 0.000 claims description 17
- 239000007789 gas Substances 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 16
- 238000009832 plasma treatment Methods 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- 239000000126 substance Substances 0.000 claims description 14
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 12
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 229910000077 silane Inorganic materials 0.000 claims description 8
- 239000011261 inert gas Substances 0.000 claims description 6
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 6
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 2
- 238000001953 recrystallisation Methods 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000005234 chemical deposition Methods 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Recrystallisation Techniques (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子のポリ
シリコン（polysilicon ）層形成方法に関するものであ
り、特に、プラズマ（plasma）処理により露出したシリ
コン基板上に残留する自然酸化膜及び異物質を除去した
後、不活性ガスが供給される蒸着反応炉内部にシリコン
基板をローデング（loading ）して非晶質シリコンを蒸
着させ、シリコンイオン（silicon ion ）を注入した
後、再結晶化（recrystallization ）させることによ
り、素子の電気的特性が向上できるようにした半導体素
子のポリシリコン層形成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a polysilicon layer of a semiconductor device, and more particularly, to a natural oxide film and foreign substances remaining on a silicon substrate exposed by plasma treatment. After the removal, the silicon substrate is loaded into the deposition reactor where an inert gas is supplied to deposit amorphous silicon, and silicon ions are injected, followed by recrystallization. The present invention relates to a method for forming a polysilicon layer of a semiconductor device, in which the electrical characteristics of the device can be improved.
【０００２】[0002]
【従来の技術】一般に、半導体素子の製造において、ポ
リシリコン層は導電層として利用される。従来の半導体
素子のポリシリコン層の形成方法を図１（Ａ）及び図１
（Ｂ）で次の如く説明する。2. Description of the Related Art Generally, a polysilicon layer is used as a conductive layer in the manufacture of semiconductor devices. A conventional method for forming a polysilicon layer of a semiconductor device is shown in FIGS.
(B) will be described as follows.
【０００３】図１（Ａ）及び図１（Ｂ）は、従来の半導
体素子のポリシリコン層形成方法を説明するための断面
図である。1A and 1B are sectional views for explaining a conventional method for forming a polysilicon layer of a semiconductor device.
【０００４】図１（Ａ）は、接合部２が形成されたシリ
コン基板１上に絶縁層３を形成した後、コンタクトホー
ルマスク（contact hole mask ）を利用した写真及びエ
ッチング工程を通じて絶縁層３をパターニング（patter
ning）して、上記接合部２上部のシリコン基板１が露出
するようにコンタクトホール４を形成した状態の断面図
であり、このとき露出したシリコン基板１上に自然酸化
膜10が成長する。In FIG. 1A, an insulating layer 3 is formed on a silicon substrate 1 on which a bonding portion 2 is formed, and then the insulating layer 3 is formed through a photo and etching process using a contact hole mask. Patterning
and a contact hole 4 is formed so that the silicon substrate 1 above the bonding portion 2 is exposed, and a natural oxide film 10 grows on the exposed silicon substrate 1.
【０００５】[0005]
【発明が解決しようとする課題】図１（Ｂ）は、上記自
然酸化膜10を除去するため、ＢＯＥ（緩衝酸化膜エッチ
ング）溶液又はＨＦ溶液を使用して湿式洗浄（wet clea
ning）工程を実施した後、３００℃の反応炉内で上記接
合部２と接続されるようポリシリコン層５を形成した状
態の断面図であり、このような方法により形成された上
記ポリシリコン層５は、グレーン（grain ）Ａの大きさ
が、例えば０．１乃至０．５μｍ程度と小さいため、電
子（electron）の移動度（mobility）又は伝導度が低下
する短所がある。尚、上記湿式洗浄工程で完全に除去さ
れず残留する自然酸化膜10のために接触（contact ）抵
抗が増大して素子の電気的特性が低下する。FIG. 1B illustrates a wet cleaning process using a BOE (buffer oxide etching) solution or an HF solution to remove the native oxide film 10.
FIG. 3 is a cross-sectional view showing a state in which a polysilicon layer 5 is formed so as to be connected to the junction 2 in a reaction furnace at 300 ° C. after performing the ning) step, and the polysilicon layer formed by such a method. In No. 5, since the size of the grain A is small, for example, about 0.1 to 0.5 μm, the mobility or conductivity of electrons is reduced. In addition, the natural oxide film 10 which is not completely removed and remains in the wet cleaning process increases contact resistance and deteriorates electrical characteristics of the device.
【０００６】従って、本発明は、プラズマ処理で露出し
たシリコン基板上に残留する自然酸化膜及び異物質を除
去した後、不活性ガスが供給される蒸着反応炉内部にシ
リコン基板をローディングして非晶質シリコンを蒸着
し、シリコンイオンを注入した後、再結晶化させること
により、上記の短所を解決することができる半導体素子
のポリシリコン層形成方法を提供することにその目的が
ある。Therefore, according to the present invention, after removing the natural oxide film and the foreign substances remaining on the silicon substrate exposed by the plasma treatment, the silicon substrate is loaded into the deposition reaction furnace to which an inert gas is supplied and the non-existence of the foreign substance is removed. An object of the present invention is to provide a method for forming a polysilicon layer of a semiconductor device, which can solve the above disadvantages by vapor-depositing crystalline silicon, implanting silicon ions, and then recrystallizing.
【０００７】[0007]
【課題を解決するための手段】上記の目的を達成するた
めの本発明は、接合部が形成されたシリコン基板上に絶
縁層を形成し、上記絶縁層をパターニングして、上記接
合部のシリコン基板が露出するようにコンタクトホール
を形成する段階と、上記段階から、露出したシリコン基
板上の自然酸化膜及び異物質を除去するために湿式洗浄
工程を実施し、プラズマ処理を実施した後、上記シリコ
ン基板を不活性ガスが供給される蒸着反応炉内部にロー
ディングする段階と、上記段階から、所定の温度の範囲
で非晶質シリコンを蒸着した後、所定のイオン注入量及
びイオン注入エネルギーを利用して、上記非晶質シリコ
ン内にシリコンイオンを注入する段階と、上記段階か
ら、上記非晶質シリコンを再結晶化させるために熱処理
工程を実施する段階から成ることを特徴とする。SUMMARY OF THE INVENTION To achieve the above object, the present invention provides an insulating layer formed on a silicon substrate on which a bonding portion is formed, the insulating layer is patterned, and the silicon of the bonding portion is formed. From the step of forming a contact hole so that the substrate is exposed, and from the above step, a wet cleaning process is performed to remove the native oxide film and foreign substances on the exposed silicon substrate, and plasma treatment is performed. The step of loading the silicon substrate into the deposition reaction furnace supplied with the inert gas, and the step of depositing amorphous silicon in the predetermined temperature range from the above step, and then using the predetermined ion implantation amount and ion implantation energy. And implanting silicon ions into the amorphous silicon, and performing a heat treatment process to recrystallize the amorphous silicon from the above steps. Characterized in that it comprises al.
【０００８】[0008]
【発明の実施の形態】以下、添付した図面を参照して本
発明を詳細に説明する。図２（Ａ）乃至図２（Ｄ）は、
本発明による半導体素子のポリシリコン層形成方法を説
明するための素子の断面図である。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 2A to 2D,
FIG. 6 is a cross-sectional view of an element for explaining a method for forming a polysilicon layer of a semiconductor element according to the present invention.
【０００９】図２（Ａ）は、接合部２が形成されたシリ
コン基板１上に絶縁層３を形成した後、コンクトホール
マスクを利用した写真及びエッチング工程で上記絶縁層
３をバターニングして、上記接合部２上部のシリコン基
板１が露出するようにコンタクトホール４を形成した状
態の断面図であり、この時、露出したシリコン基板１上
に、自然酸化膜10か形成される。In FIG. 2A, after the insulating layer 3 is formed on the silicon substrate 1 on which the joint 2 is formed, the insulating layer 3 is patterned by a photo and etching process using a contact hole mask. 3 is a cross-sectional view showing a state in which a contact hole 4 is formed so that the silicon substrate 1 above the bonding portion 2 is exposed. At this time, a natural oxide film 10 is formed on the exposed silicon substrate 1.
【００１０】図２（Ｂ）は、上記自然酸化膜10を除去す
るため、ＢＯＥ又はＨＦ溶液を使用して湿式洗浄工程を
実施し、４フッ化炭素ガス（ＣＦ4 ）を利用したプラズ
マ処理を２０乃至４０秒実施した後、大気（空気）状態
の反応炉内部に窒素（Ｎ2 ）のような不活性ガスを供給
して酸素の濃度を減少させた状態で、上記シリコン基板
１を上記反応炉内にローディングする。In FIG. 2B, in order to remove the natural oxide film 10, a wet cleaning process is performed using a BOE or HF solution, and a plasma treatment using carbon tetrafluoride gas (CF 4 ) is performed. After performing the reaction for 20 to 40 seconds, the silicon substrate 1 is subjected to the reaction in the state where the oxygen concentration is reduced by supplying an inert gas such as nitrogen (N 2 ) into the reaction furnace in the air state. Load in furnace.
【００１１】この後、５６０乃至５８０℃の温度の範囲
でシランガス（ＳｉＨ4 ）の熱分解を利用した低圧化学
蒸着（ＬＰＣＶＤ；low pressure chemical vapour dep
osition ）方法により非晶質シリコン（amorphous sili
con ）６を１０００乃至３０００Å程度の厚さで蒸着し
た状態の断面図である。After this, low pressure chemical vapor deposition (LPCVD) utilizing the thermal decomposition of silane gas (SiH 4 ) in the temperature range of 560 to 580 ° C.
of amorphous silicon (amorphous silicon)
FIG. 3 is a cross-sectional view of a state in which (con) 6 is vapor-deposited with a thickness of about 1000 to 3000 Å.
【００１２】上記４フッ化炭素ガスを利用したプラズマ
処理は、上記湿式洗浄時に完全に除去されず残留する自
然酸化膜及びポリシリコン層が形成される時、グレーン
成長の核になる酸素（Ｏ2 ）及び水素（Ｈ2 ）等のよう
な異物質を完全に除去するためであり、上記シリコン基
板１のローディング時に窒素ガスを供給して反応炉内部
の酸素濃度を下げるためにローディングする過程で酸化
膜の成長を抑制する。The plasma treatment using the above-mentioned carbon tetrafluoride gas forms oxygen (O 2) which becomes nuclei for grain growth when a natural oxide film and a polysilicon layer which are not completely removed and remain during the wet cleaning are formed. ) And hydrogen (H 2 ) and other foreign substances are completely removed, and nitrogen gas is supplied at the time of loading the silicon substrate 1 to reduce the oxygen concentration in the reactor. Inhibits film growth.
【００１３】図２（Ｃ）は、１０15ｃｍ-2のイオン注入
量（dose）及び所定のイオン注入エネルギー（energy）
を利用して、上記非晶質シリコン６にシリコンイオンを
注入する状態の断面図である。FIG. 2C shows an ion implantation dose (dose) of 10 15 cm -2 and a predetermined ion implantation energy (energy).
FIG. 6 is a cross-sectional view of a state in which silicon ions are implanted into the amorphous silicon 6 by utilizing the above.
【００１４】図２（Ｄ）は、５００乃至７００℃の温度
及び窒素ガス雰囲気の状態で熱処理工程を実施して、上
記非晶質シリコン６を再結晶化させることにより、ポリ
シリコン層6Aが形成された状態の断面図である。In FIG. 2D, a heat treatment process is performed at a temperature of 500 to 700 ° C. and in a nitrogen gas atmosphere to recrystallize the amorphous silicon 6 to form a polysilicon layer 6A. It is a sectional view of the state where it was made.
【００１５】この時、上記４フッ化炭素ガスを利用した
プラズマ処理によりグレーン成長の核になる異物質が完
全に除去されるためグレーンＢの成長が最大化され、上
記非晶質シリコンに注入されるシリコンイオンにより内
部の蓄積エネルギーが増加してグレーンＢの大きさは著
しく大きくなる。参考に、このような方法を利用する
と、１μｍ以上の大きさのグレーンを得ることができ
る。At this time, since the foreign substance which becomes the nucleus of the grain growth is completely removed by the plasma treatment using the carbon tetrafluoride gas, the growth of the grain B is maximized and is injected into the amorphous silicon. The silicon ions contained in the grains increase the energy stored therein and the size of the grain B becomes significantly large. For reference, using such a method, grains having a size of 1 μm or more can be obtained.
【００１６】[0016]
【発明の効果】上述した如く、本発明によれば非晶質シ
リコンを蒸着する前に、自然酸化膜を完全に除去して接
触抵抗を減少させ、シリコンイオン注入及び再結晶化に
より、グレーンの大きさが最大化されるようにして、電
子の移動度及び伝導度を増加させることにより、素子の
電気的特性を向上することができる卓越した効果があ
る。As described above, according to the present invention, the natural oxide film is completely removed before the deposition of amorphous silicon to reduce the contact resistance, and the grain ion is removed by the silicon ion implantation and the recrystallization. By increasing the electron mobility and conductivity by maximizing the size, there is an excellent effect that the electrical characteristics of the device can be improved.
【図１】（Ａ）及び（Ｂ）は、従来の半導体素子のポリ
シリコン層形成方法を説明するための素子の断面図であ
る。1A and 1B are cross-sectional views of an element for explaining a conventional method for forming a polysilicon layer of a semiconductor element.
【図２】（Ａ）乃至（Ｄ）は、本発明による半導体素子
のポリシリコン層形成方法を説明するための素子の断面
図である。2A to 2D are cross-sectional views of a device for explaining a method for forming a polysilicon layer of a semiconductor device according to the present invention.
１…シリコン基板、２…接合部、３…絶縁層、４…コン
タクトホール、５，6A…ポリシリコン層、６…非晶質シ
リコン、10…自然酸化膜DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Junction part, 3 ... Insulating layer, 4 ... Contact hole, 5,6A ... Polysilicon layer, 6 ... Amorphous silicon, 10 ... Natural oxide film
Claims (47)
おいて、 接合部が形成されたシリコン基板上に絶縁層を形成した
後、上記絶縁層をパターニングして上記接合部のシリコ
ン基板が露出するようにコンタクトホールを形成する段
階と、 上記段階から、露出したシリコン基板上の自然酸化膜と
異物質を除去するために湿式洗浄工程を実施し、プラズ
マ処理を実施した後、上記シリコン基板を不活性ガスが
供給される蒸着反応炉内部にローディングする段階と、 上記段階から、非晶質シリコンを蒸着した後、上記非晶
質シリコン内にシコンイオンを注入する段階と、 上記段階から、上記非晶質シリコンを再結晶化させるた
めに熱処理工程を実施する段階から成ることを特徴とす
る半導体素子のポリシリコン層形成方法。1. A method for forming a polysilicon layer of a semiconductor device, wherein an insulating layer is formed on a silicon substrate having a joint, and then the insulating layer is patterned to expose the silicon substrate at the joint. From the step of forming a contact hole, and from the above step, a wet cleaning process is performed to remove foreign substances and foreign substances on the exposed silicon substrate, and plasma treatment is performed. Is loaded into the deposition reaction furnace, the amorphous silicon is deposited from the above step, and then silicon ions are implanted into the amorphous silicon, and the amorphous silicon is loaded from the above step. A method of forming a polysilicon layer of a semiconductor device, comprising the step of performing a heat treatment process for recrystallizing the semiconductor.
らかの溶液を使用することを特徴とする半導体素子のポ
リシリコン層形成方法。2. The method for forming a polysilicon layer of a semiconductor device according to claim 1, wherein one of a BOE solution and a HF solution is used in the wet cleaning step.
乃至４０秒の間実施することを特徴とする半導体素子の
ポリシリコン層形成方法。3. The plasma treatment according to claim 1, wherein carbon tetrafluoride gas is used,
A method for forming a polysilicon layer of a semiconductor device, wherein the method is performed for 40 seconds to 40 seconds.
段階で、反応炉内の酸素濃度を減少させるために窒素ガ
スを供給することを特徴とする半導体素子のポリシリコ
ン層形成方法。4. The semiconductor device poly according to claim 1, wherein nitrogen gas is supplied to reduce the oxygen concentration in the reaction furnace during the step of loading the silicon substrate into the deposition reaction furnace. Silicon layer formation method.
囲でシランガスの熱分解を利用した低圧化学蒸着方法に
よって蒸着されることを特徴とする半導体素子のポリシ
リコン層形成方法。5. The poly of a semiconductor device according to claim 1, wherein the amorphous silicon is deposited by a low pressure chemical vapor deposition method utilizing thermal decomposition of silane gas in a temperature range of 560 to 580 ° C. Silicon layer formation method.
で蒸着されることを特徴とする半導体素子のポリシリコ
ン層形成方法。6. The method for forming a polysilicon layer of a semiconductor device according to claim 1, wherein the amorphous silicon is deposited to a thickness of 1000 to 3000 Å.
イオン注入量で注入されることを特徴とする半導体素子
のポリシリコン層形成方法。7. The method for forming a polysilicon layer of a semiconductor device, wherein the silicon ions are implanted with an ion implantation amount of 10 15 cm −2 .
は、５００乃至７００℃の温度及び、窒素ガス雰囲気状
態で実施されることを特徴とする半導体素子のポリシリ
コン層形成方法。8. The semiconductor device according to claim 1, wherein the heat treatment process for recrystallizing the amorphous silicon is performed at a temperature of 500 to 700 ° C. and a nitrogen gas atmosphere. A method for forming a polysilicon layer.
おいて、 接合部が形成されたシリコン基板上に絶縁層を形成した
後、上記絶縁層をパターニングして上記接合部のシリコ
ン基板が、露出するようにコンタクトホールを形成する
段階と、 上記段階から、露出したシリコン基板上の自然酸化膜及
び異物質を除去するために湿式洗浄工程を実施し、プラ
ズマ処理を実施する段階と、 上記段階から、非晶質シリコンを蒸着する段階と、 上記段階から、上記非晶質シリコンを再結晶化させるた
めに熱処理工程を実施する段階から成ることを特徴とす
る半導体素子のポリシリコン層形成方法。9. A method for forming a polysilicon layer of a semiconductor device, wherein an insulating layer is formed on a silicon substrate having a joint, and then the insulating layer is patterned to expose the silicon substrate at the joint. A step of forming a contact hole in the substrate, a step of performing a wet cleaning process to remove the natural oxide film and the foreign substance on the exposed silicon substrate, and a plasma treatment from the above step; A method for forming a polysilicon layer of a semiconductor device, comprising: a step of depositing crystalline silicon; and a step of performing a heat treatment step for recrystallizing the amorphous silicon from the above step.
らかの溶液を使用することを特徴とする半導体素子のポ
リシリコン層形成方法。10. The method for forming a polysilicon layer of a semiconductor device according to claim 9, wherein one of a BOE solution and an HF solution is used in the wet cleaning step.
乃至４０秒の間実施することを特徴とする半導体素子の
ポリシリコン層形成方法。11. The plasma processing according to claim 9, wherein the plasma treatment is performed using oxygen tetrafluoride gas.
A method for forming a polysilicon layer of a semiconductor device, wherein the method is performed for 40 seconds to 40 seconds.
囲で、シランガスの熱分解を利用した低圧化学蒸着方法
により蒸着されることを特徴とする半導体素子のポリシ
リコン層形成方法。12. The semiconductor device according to claim 9, wherein the amorphous silicon is deposited in a temperature range of 560 to 580 ° C. by a low pressure chemical vapor deposition method utilizing thermal decomposition of silane gas. Method for forming polysilicon layer.
で蒸着されることを特徴とする半導体素子のポリシリコ
ン層形成方法。13. The method for forming a polysilicon layer of a semiconductor device according to claim 9, wherein the amorphous silicon is deposited to a thickness of 1000 to 3000Å.
５００乃至７００℃の温度及び窒素ガス雰囲気の状態で
実施されることを特徴とする半導体素子のポリシリコン
層形成方法。14. The heat treatment step for recrystallizing the amorphous silicon according to claim 9,
A method for forming a polysilicon layer of a semiconductor device, which is carried out at a temperature of 500 to 700 ° C. and in a nitrogen gas atmosphere.
において、 接合部が形成されたシリコン基板上に絶縁層を形成した
後、上記絶縁層をパターニングして、上記接合部のシリ
コン基板が露出するようにコンタクトホールを形成する
段階と、 上記段階から、露出したシリコン基板上の自然酸化膜及
び異物質を除去するために湿式洗浄工程を実施し、プラ
ズマ処理を実施した後、上記シリコン基板を不活性ガス
が供給される蒸着反応炉内にローディングする段階と、 上記段階から、非晶質シリコンを蒸着する段階と、 上記段階から、上記非晶質シリコンを再結晶化させるた
めに熱処理工程を実施する段階から成ることを特徴とす
る半導体素子のポリシリコン層形成方法。15. A method for forming a polysilicon layer of a semiconductor device, wherein an insulating layer is formed on a silicon substrate having a joint, and then the insulating layer is patterned to expose the silicon substrate at the joint. After forming a contact hole in the silicon substrate, a wet cleaning process is performed to remove the native oxide film and foreign substances on the exposed silicon substrate, and plasma treatment is performed to inactivate the silicon substrate. Performing a step of loading into a deposition reactor supplied with gas, a step of depositing amorphous silicon from the above step, and a heat treatment step from the above step to recrystallize the amorphous silicon. A method of forming a polysilicon layer in a semiconductor device, the method comprising the steps of:
らかの溶液を使用することを特徴とする半導体素子のポ
リシリコン層形成方法。16. The method for forming a polysilicon layer of a semiconductor device according to claim 15, wherein one of a BOE solution and an HF solution is used in the wet cleaning step.
乃至４０秒の間実施することを特徴とする半導体素子の
ポリシリコン層形成方法。17. The plasma processing according to claim 15, wherein the plasma treatment is performed using carbon tetrafluoride gas.
A method for forming a polysilicon layer of a semiconductor device, wherein the method is performed for 40 seconds to 40 seconds.
ローディングする段階で、反応炉内部の酸素の濃度を減
少させるために窒素ガスを供給することを特徴とする半
導体素子のポリシリコン層形成方法。18. A method for forming a polysilicon layer of a semiconductor device, comprising supplying nitrogen gas to reduce the concentration of oxygen in the reaction furnace during the step of loading the silicon substrate into the deposition reaction furnace. .
囲でシランガスの熱分解を利用した低圧化学蒸着方法に
より蒸着されることを特徴とする半導体素子のポリシリ
コン層形成方法。19. The poly of a semiconductor device according to claim 15, wherein the amorphous silicon is deposited by a low pressure chemical vapor deposition method utilizing thermal decomposition of silane gas in a temperature range of 560 to 580 ° C. Silicon layer formation method.
で蒸着されることを特徴とする半導体素子のポリシリコ
ン層形成方法。20. The method for forming a polysilicon layer of a semiconductor device according to claim 15 or 19, wherein the amorphous silicon is deposited to a thickness of 1000 to 3000Å.
程は、５００乃至７００℃の温度及び窒素ガス雰囲気状
態で実施されることを特徴とする半導体素子のポリシリ
コン層形成方法。21. The semiconductor device according to claim 15, wherein the heat treatment process for recrystallizing the amorphous silicon is performed at a temperature of 500 to 700 ° C. and a nitrogen gas atmosphere. Method for forming polysilicon layer.
において、 接合部が形成されたシリコン基板上に絶縁層を形成した
後、上記絶縁層をパターニングして上記接合部のシリコ
ン基板が露出するようにコンタクトホールを形成する段
階と、 上記段階から、露出したシリコン基板上の自然酸化膜及
び異物質を除去するために湿式洗浄工程を実施し、プラ
ズマ処理を実施する段階と、 上記段階から、非晶質シリコンを蒸着した後、上記非晶
質シリコン内にシリコンイオンを注入する段階と、 上記段階から、上記非晶質シリコンを再結晶化させるた
めに熱処理工程を実施する段階から成ることを特徴とす
る半導体素子のポリシリコン層形成方法。22. A method of forming a polysilicon layer of a semiconductor device, wherein an insulating layer is formed on a silicon substrate having a joint, and then the insulating layer is patterned to expose the silicon substrate of the joint. From the step of forming a contact hole, the step of performing a wet cleaning process to remove the native oxide film and foreign substances on the exposed silicon substrate and performing the plasma treatment, and the step of After depositing the high-quality silicon, the method comprises the steps of implanting silicon ions into the amorphous silicon, and performing a heat treatment process to recrystallize the amorphous silicon. Method for forming polysilicon layer of semiconductor device.
らかの溶液を使用することを特徴とする半導体素子のポ
リシリコン層形成方法。23. The method for forming a polysilicon layer of a semiconductor device according to claim 22, wherein one of a BOE solution and an HF solution is used in the wet cleaning step.
乃至４０秒の間実施することを特徴とする半導体素子の
ポリシリコン層形成方法。24. The plasma treatment according to claim 22, wherein carbon tetrafluoride gas is used for the plasma treatment.
A method for forming a polysilicon layer of a semiconductor device, wherein the method is performed for 40 seconds to 40 seconds.
囲で、シランガスの熱分解を利用する低圧化学蒸着方法
により蒸着されることを特徴とする半導体素子のポリシ
リコン層形成方法。25. The semiconductor device according to claim 22, wherein the amorphous silicon is deposited in a temperature range of 560 to 580 ° C. by a low pressure chemical vapor deposition method utilizing thermal decomposition of silane gas. Method for forming polysilicon layer.
で蒸着されることを特徴とする半導体素子のポリシリコ
ン層形成方法。26. The method for forming a polysilicon layer of a semiconductor device according to claim 22 or 25, wherein the amorphous silicon is deposited to a thickness of 1000 to 3000Å.
注入されることを特徴とする半導体素子のポリシリコン
層形成方法。27. The method of claim 22, wherein the silicon ions are implanted with an ion implantation amount of 10 15 cm −2 .
程は、５００乃至７００℃温度及び窒素ガス雰囲気の状
態で実施されることを特徴とする半導体素子のポリシリ
コン層形成方法。28. The semiconductor device according to claim 22, wherein the heat treatment process for recrystallizing the amorphous silicon is performed at a temperature of 500 to 700 ° C. and a nitrogen gas atmosphere. Method for forming polysilicon layer.
において、 接合部が形成されたシリコン基板上に絶縁層を形成した
後、上記絶縁層をパターニングして上記接合部のシリコ
ン基板が露出するようにコンタクトホールを形成する段
階と、 上記段階から、露出したシリコン基板上の自然酸化膜及
び異物質を除去するために湿式洗浄工程を実施した後、
上記シリコン基板を、不活性ガスが供給される蒸着反応
炉の内部にローディングする段階と、 上記段階から、非晶質シリコンを蒸着した後、上記非晶
質シリコン内にシリコンイオンを注入する段階と、 上記段階から、上記非晶質シリコンを再結晶化させるた
めに熱処理工程を実施する段階から成ることを特徴とす
る半導体素子のポリシリコン層形成方法。29. In the method for forming a polysilicon layer of a semiconductor device, an insulating layer is formed on a silicon substrate having a bonding portion, and then the insulating layer is patterned to expose the silicon substrate of the bonding portion. From the step of forming the contact hole, and from the above step, after performing the wet cleaning process to remove the native oxide film and foreign substances on the exposed silicon substrate,
Loading the silicon substrate into a deposition reaction furnace to which an inert gas is supplied; and depositing amorphous silicon and then implanting silicon ions into the amorphous silicon. A method for forming a polysilicon layer of a semiconductor device, comprising: performing a heat treatment step to recrystallize the amorphous silicon from the above step.
らかの溶液を使用することを特徴とする半導体素子のポ
リシリコン層形成方法。30. The method for forming a polysilicon layer of a semiconductor device according to claim 29, wherein one of a BOE solution and a HF solution is used in the wet cleaning step.
段階で、反応炉内の酸素の濃度を減少させるために窒素
ガスを供給することを特徴とする半導体素子のポリシリ
コン層形成方法。31. The semiconductor device according to claim 29, wherein at the step of loading the silicon substrate into the deposition reaction furnace, nitrogen gas is supplied to reduce the concentration of oxygen in the reaction furnace. Method for forming polysilicon layer.
囲で、シランガスの熱分解を利用した低圧化学蒸着方法
により蒸着されることを特徴とする半導体素子のポリシ
リコン層形成方法。32. The semiconductor device according to claim 29, wherein the amorphous silicon is deposited in a temperature range of 560 to 580 ° C. by a low pressure chemical vapor deposition method utilizing thermal decomposition of silane gas. Method for forming polysilicon layer.
で蒸着されることを特徴とする半導体素子のポリシリコ
ン層形成方法。33. The method for forming a polysilicon layer of a semiconductor device according to claim 29 or 32, wherein the amorphous silicon is deposited to a thickness of 1000 to 3000Å.
注入されることを特徴とする半導体素子のポリシリコン
層形成方法。34. The method of claim 29, wherein the silicon ions are implanted with an ion implantation amount of 10 15 cm −2 .
は、５００乃至７００℃の温度及び窒素ガス雰囲気の状
態で実施されることを特徴とする半導体素子のポリシリ
コン層形成方法。35. The semiconductor device according to claim 29, wherein the heat treatment process for recrystallizing the amorphous silicon is performed at a temperature of 500 to 700 ° C. and in a nitrogen gas atmosphere. Method for forming polysilicon layer.
において、 接合部が形成されたシリコン基板上に絶縁層を形成した
後、上記絶縁層をパターニングして、上記接合部のシリ
コン基板が露出するようにコンタクトホールを形成する
段階と、 上記段階から、露出したシリコン基板上の自然酸化膜及
び異物質を除去するために湿式洗浄工程を実施した後、
上記シリコン基板を不活性ガスが供給される蒸着反応炉
内にローディングする段階と、 上記段階から、非晶質シリコンを蒸着する段階と、 上記段階から、上記非晶質シリコンを再結晶化させるた
めに熱処理工程を実施する段階から成ることを特徴とす
る半導体素子のポリシリコン層形成方法。36. In the method for forming a polysilicon layer of a semiconductor device, an insulating layer is formed on a silicon substrate having a bonding portion, and then the insulating layer is patterned to expose the silicon substrate at the bonding portion. After the step of forming a contact hole in the step, and from the above step, after performing a wet cleaning process to remove the native oxide film and foreign substances on the exposed silicon substrate,
To load the silicon substrate into a deposition reaction furnace supplied with an inert gas, to deposit amorphous silicon from the above steps, and to recrystallize the amorphous silicon from the above steps. A method for forming a polysilicon layer of a semiconductor device, comprising the step of performing a heat treatment step.
らかの溶液を利用することを特徴とする半導体素子のポ
リシリコン層形成方法。37. The method for forming a polysilicon layer of a semiconductor device according to claim 36, wherein one of a BOE solution and a HF solution is used in the wet cleaning step.
階で、反応炉内の酸素の濃度を減少させるために窒素ガ
スを供給することを特徴とする半導体素子のポリシリコ
ン層形成方法。38. The method of claim 36, wherein nitrogen gas is supplied to reduce the oxygen concentration in the reaction furnace during the loading of the silicon substrate into the deposition reaction furnace. Silicon layer formation method.
囲でシランガスの熱分解を利用した低圧化学蒸着方法に
より蒸着されることを特徴とする半導体素子のポリシリ
コン層形成方法。39. The poly-type semiconductor device according to claim 36, wherein the amorphous silicon is deposited by a low pressure chemical vapor deposition method utilizing thermal decomposition of silane gas in a temperature range of 560 to 580.degree. Silicon layer formation method.
で蒸着されることを特徴とする半導体素子のポリシリコ
ン層形成方法。40. The method for forming a polysilicon layer of a semiconductor device according to claim 36, wherein the amorphous silicon is deposited to a thickness of 1000 to 3000Å.
は、５００乃至７００℃の温度及び窒素ガス雰囲気の状
態で実施されることを特徴とする半導体素子のポリシリ
コン層形成方法。41. The semiconductor device according to claim 36, wherein the heat treatment process for recrystallizing the amorphous silicon is performed at a temperature of 500 to 700 ° C. and in a nitrogen gas atmosphere. Method for forming polysilicon layer.
において、 接合部が形成されたシリコン基板上に絶縁層を形成した
後、上記絶縁層をパターニングして、上記接合部のシリ
コン基板が露出するようにコンタクトホールを形成する
段階と、 上記段階から、露出したシリコン基板上の自然酸化膜及
び異物質を除去するために湿式洗浄工程を実施する段階
と、 上記段階から、非晶質シリコンを蒸着した後、上記非晶
質シリコンにシリコンイオンを注入する段階と、 上記段階から、上記非晶質シリコンを再結晶化させるた
めに熱処理工程を実施する段階から成ることを特徴とす
る半導体素子のポリシリコン層形成方法。42. In the method of forming a polysilicon layer of a semiconductor device, an insulating layer is formed on a silicon substrate having a bonding portion, and then the insulating layer is patterned to expose the silicon substrate of the bonding portion. A contact hole is formed on the silicon substrate, a wet cleaning process is performed to remove the natural oxide film and foreign substances on the exposed silicon substrate, and amorphous silicon is deposited from the above process. After that, a step of implanting silicon ions into the amorphous silicon, and a step of performing a heat treatment step to recrystallize the amorphous silicon from the step described above are included in the polysilicon of the semiconductor device. Layer forming method.
らかの溶液を使用することを特徴とする半導体素子のポ
リシリコン層形成方法。43. The method for forming a polysilicon layer of a semiconductor device according to claim 42, wherein one of a BOE solution and an HF solution is used in the wet cleaning step.
囲でシランガスの熱分解を利用した低圧化学蒸着方法に
より蒸着されることを特徴とする半導体素子のポリシリ
コン層形成方法。44. The poly according to claim 42, wherein the amorphous silicon is deposited by a low pressure chemical vapor deposition method utilizing thermal decomposition of silane gas in a temperature range of 560 to 580 ° C. Silicon layer formation method.
で蒸着されることを特徴とする半導体素子のポリシリコ
ン層形成方法。45. The method for forming a polysilicon layer of a semiconductor device according to claim 42, wherein the amorphous silicon is deposited to a thickness of 1000 to 3000Å.
注入されることを特徴とする半導体素子のポリシリコン
層形成方法。46. The method for forming a polysilicon layer of a semiconductor device according to claim 42, wherein the silicon ions are implanted with an ion implantation amount of 10 15 cm −2 .
は、５００乃至７００℃の温度及び窒素ガス雰囲気の状
態で実施されることを特徴とする半導体素子のポリシリ
コン層形成方法。47. The semiconductor device according to claim 42, wherein the heat treatment process for recrystallizing the amorphous silicon is performed at a temperature of 500 to 700 ° C. and a nitrogen gas atmosphere. Method for forming polysilicon layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR95-10983 | 1995-05-04 | ||
| KR1019950010983A KR100208439B1 (en) | 1995-05-04 | 1995-05-04 | Method of forming polysilicon layer in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08306642A true JPH08306642A (en) | 1996-11-22 |
Family
ID=19413757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8106869A Pending JPH08306642A (en) | 1995-05-04 | 1996-04-26 | Polysilicon layer formation method of semiconductor element |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH08306642A (en) |
| KR (1) | KR100208439B1 (en) |
| CN (1) | CN1083158C (en) |
| DE (1) | DE19617833A1 (en) |
| GB (1) | GB2300517B (en) |
| TW (1) | TW291572B (en) |
Cited By (1)
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|---|---|---|---|---|
| US8541822B2 (en) | 2008-11-21 | 2013-09-24 | Sharp Kabushiki Kaisha | Semiconductor device and method for producing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107192A (en) * | 1997-12-30 | 2000-08-22 | Applied Materials, Inc. | Reactive preclean prior to metallization for sub-quarter micron application |
| KR102178535B1 (en) | 2014-02-19 | 2020-11-13 | 삼성전자주식회사 | Methods of manufacturing semiconductor devices |
| CN106571289B (en) * | 2015-10-13 | 2020-01-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method thereof and electronic device |
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| JP2697645B2 (en) * | 1994-10-31 | 1998-01-14 | 日本電気株式会社 | Method for manufacturing semiconductor device |
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- 1995-05-04 KR KR1019950010983A patent/KR100208439B1/en not_active IP Right Cessation
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- 1996-04-26 JP JP8106869A patent/JPH08306642A/en active Pending
- 1996-04-30 GB GB9608822A patent/GB2300517B/en not_active Expired - Fee Related
- 1996-05-03 DE DE19617833A patent/DE19617833A1/en not_active Ceased
- 1996-05-04 TW TW085105355A patent/TW291572B/zh active
- 1996-05-04 CN CN96107491A patent/CN1083158C/en not_active Expired - Fee Related
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|---|---|---|---|---|
| JPH0322527A (en) * | 1989-06-20 | 1991-01-30 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0350823A (en) * | 1989-07-19 | 1991-03-05 | Nec Corp | Manufacture of semiconductor device |
| JPH04188752A (en) * | 1990-11-21 | 1992-07-07 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPH05275365A (en) * | 1992-03-30 | 1993-10-22 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| JPH0729852A (en) * | 1993-07-07 | 1995-01-31 | Kawasaki Steel Corp | Fabrication of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8541822B2 (en) | 2008-11-21 | 2013-09-24 | Sharp Kabushiki Kaisha | Semiconductor device and method for producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2300517B (en) | 1999-07-28 |
| GB9608822D0 (en) | 1996-07-03 |
| GB2300517A (en) | 1996-11-06 |
| CN1144397A (en) | 1997-03-05 |
| KR100208439B1 (en) | 1999-07-15 |
| CN1083158C (en) | 2002-04-17 |
| DE19617833A1 (en) | 1996-11-07 |
| TW291572B (en) | 1996-11-21 |
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