KR100198433B1 - Channelized frame relay network/service interworking equipement in atm switching system - Google Patents

Abstract

The present invention relates to a frame relay network / service interworking apparatus for processing by channel in an ATM exchange. The purpose is to enable interworking between ATM subscribers and frame relay subscribers. The configuration includes a transmitter for transmitting data, a receiver for receiving data, an HDLC controller for configuring and transmitting a frame with a flag and an FCS, an auxiliary controller for controlling a bus and an interrupt so that the HDLC controller operates efficiently, It is composed of a total control unit for controlling and monitoring the whole, and a clock / power supply unit for receiving a clock and supplying a clock and power to the whole. Possible applications of the configuration of the present invention are the channel-specific and non-channel-specific processing of the UNI and NNI network interworking and service interworking frame relay.

Description

Frame relay network / service interworking device for each channel in ATM switch

The present invention relates to an apparatus for accommodating a frame relay subscriber and a network in an ATM switch, and more particularly, to a frame relay network / service interworking apparatus for processing by a channel in an ATM switch.

In general, the ATM network is recognized as the main network of the high-speed service, and in view of the development and pilot service of the ATM exchanger and the commercial service of the frame relay, the ATM exchanger connects the frame relay subscriber and the network to the ATM subscriber. There is an urgent need for a function that enables interworking between a subscriber and a frame relay subscriber. In addition, in view of the fact that the use of frame relay subscribers occupies about 50% at 64 Kbps, a channel-based service is suitable for the exchange.

As ATM networks have emerged as high-speed communication networks, researches and standards on interworking between ATM networks and existing networks have been conducted. As a high speed communication network before ATM, frame relay has been used for LNA-to-LAN connection, which is advantageous for high speed data transmission and high capacity file transmission. Recently, an ATM switching function is adopted in a private frame relay switch, and an ATM connection function is also possible. Therefore, interworking between public ATM and frame relay is essential at the stage that frame relay is in service and ATM service is being tested in various countries. The frame relay service has been started in Korea, and the type of accommodating subscribers in the frame relay network is DS1 / E1 for each channel via multiple devices. This is effective for accepting subscribers having a bandwidth of about 64 Kbps. This is a method for accommodating low-speed clustered subscribers in a frame relay exchange, and thus has recently specified a channelized function as a function of the frame relay exchange. In case of interlocking frame relay in ATM exchange, subscriber may be directly accommodated and frame relay network may be matched. When matching frame relay subscribers, channelized functionality is also required at ATM switches. When such a function is implemented on the ATM side, a function of converting a frame into an ATM cell is required.

In the ATM, frame relay interworking began to be studied in the 1990s. In recent years, the specification has been advanced considerably, and the network interworking to PVC is almost completed. It is also the primary practice of this type of service worldwide. Such function has been implemented in Korea, and only the network interworking function is confirmed as E1 which is not channelized. The minimum bandwidth in the channelized is 64Kbps, and the DS1 can be divided into 31 64Kbps units for 23 E1s. Therefore, in case of channelized frame relay, 31 HDLC controllers are required for each DS1 / E1. In consideration of price and space, the HDLC controller is advantageously a device having a large number of HDLC controllers in one device. In addition, a function of decomposing a frame into an AAL5 ATM cell and a memory for storing a frame or an ATM cell are required. Typically, devices that perform AAL5 functions are expensive and have the ability to process data at 155Mbps.

However, there has been a problem in that it is impossible to interwork between an ATM subscriber and a frame relay subscriber by connecting a frame relay subscriber and a network in an ATM switch.

The present invention devised to solve the above problems has an object to enable interworking between ATM subscribers and frame relay subscribers.

A feature of the present invention for achieving the above object is a transmitter for transmitting data, a receiver for receiving data, an HDLC controller for configuring and transmitting a frame with a flag and an FCS, and a bus for operating the HDLC controller efficiently. It consists of an auxiliary constrainer for controlling interrupts, an entire control unit for controlling and monitoring the whole, and a clock / power supply unit for receiving the clock and supplying the clock and power to the whole.

The frame relay aimed at by the present invention uses DS1 of 1.544 Mbps or E1 of 2.048 Mbps as the maximum transmission medium. Therefore, when accommodating the interworking function in the ATM switch, there is a need for a strategy of mapping several DS1 / E1 to one AAL5 functional element. Another problem that may arise in this case is the processor's ability. In addition to the transmission between frames passing through multiple DS1 / E1s and ATM cells via AAL5 devices, more header conversion is required when interworking services. In the case of 16-bit or 32-bit memory, the occupied space is almost independent of the memory capacity. When memory read / write occurs as little as possible, the memory is classified by function in consideration of the increase in data processing efficiency. This memory will increase linearly. In addition, in terms of exchange, accommodating a large number of subscribers on the same board is advantageous in terms of price. However, when replacing a board in case of service failure, service for all subscribers on the same board is suspended. In the present invention, in consideration of the above problems, the number of DS1 / E1, HDLC control element for processing more than 31 channels, memory configuration for efficient data processing and transmission, AAL5 functional element, capable of performing the above-described functions fully The present invention was constructed by selecting a processor or the like. In the present invention, since the channelized function is used without distinction between channels, the channelized function is not channelized, and since channelization and non-channelization are possible, there are much more various configurations to directly accommodate the frame relay subscriber. It is possible. As described above, the present invention performs the conversion between the frame of the frame relay and the cell of the ATM.

1A to 1B are frame configuration diagrams of an ATM cell and a frame relay according to the present invention.

2 is a diagram illustrating a conversion procedure between a frame and an ATM cell according to the present invention.

3 is a system structural diagram of the present invention.

4 is a block diagram of a frame relay network / service interworking device according to the present invention.

* Explanation of symbols for main parts of the drawings

100: ACS 200: ALS

300: FMDA 400: FCDA

500: FRSA 511: clock receiver

512: DC / DC power control unit 521: HDLC control memory unit

522: HDLC control unit 523: DS1 / E synchronization unit

531: bus arbitration unit 532: interrupt control unit

533: DS1 / E connection 541: RS232C control unit

542: processor control unit 550: IPC transmission unit

561: Receive Packet Memory Unit 562: AAL5 Receive Control Memory Unit

563: AAL5 packet receiving control unit 564: FIFO receiving unit

571: Transmission packet memory section 572: AAL5 transmission control memory section

573: AAL5 packet transmission control unit 574: FIFO transmission unit

Hereinafter, with reference to the accompanying drawings will be described in detail one of the preferred embodiments according to the present invention.

1A to 2B are frame configuration diagrams of an ATM cell and a frame relay according to the present invention. Referring to FIG. 1, a frame configuration of an ATM cell and a frame relay according to the present invention will be described below.

In the figure, MSB stands for Most Significant Bit and LSB stands for Least Significant Bit. CFC stands for General Flow Control, and VPI stands for Virtual Path Indentifier. VCI stands for Virtual Channel Identifier, and PTI stands for Payloard Type Identifier. CLP stands for Cell Loss Priority, and DLCI stands for Data Link Connection Identifier. C / R stands for Command / Response and BECN stands for Backward Explicit Congestion Notification. FECN stands for Forword Explicit Congestion Notification and DE stands for Discard Eligible. The ATM cell consists of 53 bytes, of which 5 bytes are headers describing the cell's belonging and characteristics. In the case of UNI, the highest 4 bit CFC of the header is not used. The other 8 bits of VPI and 16 bits of VCI indicate the cell's affiliation, and the next 3 bits of PTI describe the characteristics of 48 bytes of payload, including EFCI. Next, the CLP 1 bit indicates the cell loss priority, and if 'CLP = 1', it indicates that the cell can be discarded preferentially when the network is to be protected by congestion. The next HEC is a CRC for 4 bytes of headers for detecting errors occurring in the headers, and a 1-bit correction function is also possible. The frame is indicated by the FCS of CRC-16 for the user information and header and user information of the frame relay capable of a 1 byte start flag described in 7E (H), a header of 2 to 4 bytes and up to 1600 bytes, and 7E (H). It consists of a one-byte termination flag. The header is basically 2 bytes, in this case 10-bit DLCI, which is the ID of measurement 2, C / R bits indicating whether the frame is a command or response, FECN indicating forward network congestion, BECN indicating reverse network congestion, It consists of a DE indicating the frame discarding priority.

2 is a diagram illustrating a conversion procedure between a frame and an ATM cell according to the present invention. Referring to FIG. 2, a change procedure between a frame and an ATM cell according to the present invention will be described.

H stands for header of the associated layer and T stands for tailer of the associated layer. In the present invention, when performing the service interworking function between the frame relay and the ATM, the conversion between the frame and the cell is the frame of the ITU-T Q.922 core type to remove the header and tail and add padding and trailer in the function of AAL5 The CPCS-PDU of AAL5 is composed, which is decomposed into the payload of the ATM cell, and the header information of the ATM cell is mapped to the header of the frame to be placed in front of the payload of each cell, thereby forming a plurality of complete ATM cells. Assembly as a frame in an ATM cell is performed with its inverse transform.

3 is a system structural diagram to which the present invention belongs. Referring to Figure 3 describes the structure of the system to which the present invention belongs.

The ATM switch has a three-stage switch structure by the ATM local switch ALS 200 and the ATM central switch ACS 100. The module to which the present invention belongs is connected to the 155.52 Mbps port from the ALS 100, and information transmission is performed. Accordingly, the network synchronization clock is supplied with a separate cable. Module to which the present invention belongs is composed of one FMDA (300), one FCDA (400) and the present invention FRSA (500) consisting of a maximum of 16 sheets. The frame is received by the FRSA 500 to perform the functions of FIG. 2, and the FMDA 300 multiplexes cells from several FRSA 500s and transmits them through IMI. Looking at the main functions of each board in performing these functions, the main functions of the FMDA (300) include the IPC master function of the module, the function of connecting to the ALS 100 and IMI, ATM cell multiplexing / demultiplexing function, FIFO UPC for monitoring the compliance of the traffic parameters negotiated with the network for the input cell, the function of transmitting the ATM cell to be performed with the present invention, the module maintenance and call processing message to the IPC message with the present invention through DPRAM. / NPC function and ATM cell VPI / VCI conversion. The main function of FCDA 400 is to receive 46.94Mhz network synchronous clock, which is required for communication between FMDA 300 and FRSA 500 (23.47Mhz, 11.73Mhz) and DS1 / E1 clock (16.384). Mhz, 12.353Mhz) has the ability to generate and disassemble. Looking at the approximate function for performing the functions of FIG. 2 of the FRSA 500, the function of connecting the DS1 / E1, the HDLC control function, the packet memory function for storing the frame, the function of disassembling / assembling the AAL5 frame into ATM cells, There is a function for transmitting ATM cells.

4 is a block diagram of a frame relay network / service interworking apparatus according to the present invention.

Referring to FIG. 4, the configuration of a frame relay network / service interworking apparatus according to the present invention will be described.

DS1 / E1 line connection 533 is made in ITU-T Rec. It is a line connection part including four DS1 / E1 which satisfy G.703 and G.704, and it performs clock recovery, line performance monitoring, and alarm indication signal (AIS) transmission function. It also has a processor and connectivity. The embodiment of the present invention uses the PM4314 QDSX, and provides four DS1 / E1 line connection functions in one device.

The DS1 / E1 register 523 recovers clock and data using a digital phase locked loop (DPLL) and performs a CRC multiframe setting function and a line performance monitoring function using the same. It also has the ability to connect to the processor for initial configuration, status monitoring and control. In connection with the DS1 / E1 line connection part 533, the measurement 1 function of the frame relay is realized. As an example of the DS1 / E1 register 523, PM6344 EQUAD is used for E1, and PM4344 TQUAD is used for DS1. . The PM6344 and PM4344 can connect four E1s and DS1s, respectively, and have the same pinout, which makes them easy to implement on the same PCB.

The DC / DC power supply control unit 512 performs a function of converting to + 5V / 6A power by inputting -48V, and the present invention prepares for power failure when using a common DC / DC converter and facilitates board replacement. In order to use a power conversion device of the on-board (on-board) type was used. Other than the conversion function, there is a function to switch the power first when the board is dismounted. In the present embodiment, a custom-made power pack was used.

As shown in FIG. 3, the clock receiving unit 511 divides the network synchronization clock among the clocks generated by the FCDA 400, 11.7373Mhz and 23.474Mhz transmit the FDMA 300 and the cell of FIG. It receives 12.352Mhz for matching and 16.384Mhz clock for matching E1. In the present embodiment, in the present invention, the clock transmission signal level is set as PECL, which has the same performance as the ECL signal, and unlike the ECL, a single + 5v power supply is required, which makes the function of the DC / DC power control unit 512 complicated. To avoid that. In this example, 1141LF is used for PECL reception.

The HDLC controller 522 has 31 HDLC controller connection functions per PCM highway, that is, per DS1 / E1. In this embodiment, four HDLC control elements are used by using a device (PEB20320) having 32 HDLC controllers. . The parallel bus is connected to the data and address buses such as the processor, the transmit packet memory 571, and the receive packet memory 561, and the initialization and configuration change of the HDLC controller is different from the general method of accessing the registers of the device. The processor performs the write / read operation on the external HDLC control memory unit corresponding to the initial memory access value of the controller. The frame received by the HDLC control unit 522 is controlled by the DMA control of the control element and is written to the reception packet memory unit 561 having a predetermined address without control of the processor. When writing is completed, an interrupt corresponding to frame reception completion is generated so that the processor can immediately process the received frame by reading the HDLC control memory unit 521. The frame transmission starts by instructing the HDLC control memory unit 521 to transmit a frame from a specific address of the transmission packet memory unit 571 while the processor has completed writing the frame to be transmitted to the transmission packet memory unit 571. The HDLC control unit 522 configures the frame with a flag and an FCS as shown in FIG. 1 and transmits the data through the DS1 / E1 connection unit 533. When the transmission is completed, the HDLC control unit 522 describes this in the HDLC control memory unit 521. It prepares for the next frame transmission by informing the processor. As described in the HDLC control unit 522, the HDLC control memory 521 performs a function in which all control commands and status reports between the processor and four HDLC elements are described. Simultaneous connection of four HDLC devices is possible with different initial address assignments, and a 32-bit data bus is used for fast access. In this embodiment, 32-bit SRAM is configured.

The AAL5 packet transmission control unit 573 configures user information stored in the reception packet memory unit 561 into an AAL5 CPCS-PDU, and decomposes the information into ATM cells, and receives the reception packet memory unit 561 and a 32-bit data bus. 16 bits are connected to the AAL5 transmission control memory unit 572 and 16 bits are connected to the FIFO transmitter 574. The AAL5 packet transmission control unit 573 reads the ATM user information stored in the reception packet memory unit 9561 of the address addressed by the processor in a DMA manner, adds padding and CPCS taylor to form an AAL5 CPCS-PDU, and decomposes the ATM. It creates a payload for the cell and writes it to the cell send FIFO with each payload prepended with the ATM header information that the processor tells. In this example, SARA-S was used.

The AAL5 transmission control memory unit 572 is composed of 16-bit SRAM as a memory for transferring control parameters between the AAL5 packet transmission control unit 573 and the processor.

The receiving packet memory unit 561 is used to store the frame received by the HDLC control unit 522 and to convert the received frame to the AAL5 user information by modifying the header of the receiving frame and the like through the processor. In this embodiment, the maximum frame length is limited to 1600 bytes recommended by the frame relay forum, frames are received at a maximum of 124 channels, and 32 bits of 1 megabyte capacity is guaranteed to ensure 5 times the minimum memory in consideration of simultaneous multipleness. SRAM module was used.

The FIFO transmitter 574 transmits the ATM cell to the FMDA 300 of FIG. 3 and writes to the FIFO according to the 11.7373 MHz cell synchronization clock. ATM cell transmission is made of 16 bits, and thus, a 56-byte internal ATM cell having a 53-byte ATM cell and a 3-byte routing information area completes one cell write with 28 data transfers. In the present invention, if there is data in the FIFO transmitter 574, the FMDA 300 reads the cell. In this example, IDT72841 was used.

The AAL5 packet reception control unit 563 assembles an ATM cell to generate an AAL5 CPCS-PDU. The AAL5 packet reception control unit 563 is connected to a processor, a transmission packet memory unit 571 by a 32-bit data bus, and an AAL5 reception control memory unit 562. ) Is connected in 16 bits and the FIFO receiver 564 is connected in 16 bits. The AAL5 packet reception control unit 563 receives an ATM cell from the FIFO reception unit 564, assembles it into an AAL5 CPCS-PDU, stores it in the transmission packet memory unit 571 by DMA, and receives the corresponding VPI / VCI from the AAL5. Stored in the control memory unit 562 and generates an interrupt to the processor to be processed by the processor. In this example, SARA-R was used.

The AAL5 reception control memory unit 562 is composed of 16-bit SRAM as a memory for transferring control parameters between the AAL5 packet reception control unit 563 and the processor.

The transmission packet memory unit 571 stores the AAL5 CPCS-PDU received by the AAL5 packet reception control unit 563, and is used to modify the AAL5 CPCS-PDU header or the like and to store the AAL5 CPCS-PDU header as a frame relay frame. In addition, the converted frame is read by the HDLC control unit 522 and transmitted to DS1 / E1. In this embodiment, a 32-bit SRAM module having a capacity of 1 megabyte is used under the same condition as that of the reception packet memory unit 561.

The FIFO receiving unit 564 reads from the FIFO according to the 11.737 MHz cell synchronization clock as to receive the ATM cell from the FMDA 300 of FIG. ATM cell transmission is made of 16 bits in the same manner as the FIFO transmitter 574, and IDT72841 is used in this embodiment.

The IPC transmitter 550 is used to transmit IPC information between the FMDA 300 and the FRSA 500 of FIG. The FMDA 300 and the FRSA 500 divide the memory area using DPRAM, and the write area in the FMDA 300 is used as the read area in the FRSA 500, and the write in the FRSA 500 is performed. The area to be used as the area to be read in the FMDA (300). When writing, it indicates the validity of data at a specific location and the data length. After reading, it displays the read completion to guarantee the safe data transmission. In this embodiment, 8 bits are transmitted using IDT7132.

The processor control unit 542 uses two processors, namely, MC68EC040 and MC68360, and is composed of 16-bit ROM and 32-bit SRAM. The MC68360 operates in the companion mode of the MC68EC040, which does not operate the CPU part but only the peripheral functions. The MC68EC040 operates as the master of the MC68360 with only the CPU function. This improves processor performance by four to five times the performance of the MC680360 only. In order to interlock frame relay in ATM exchange, basically, every frame should be converted into AAL5 CPCS-PDU as shown in Fig. 2, and the ATM cell should be received to convert AAL5 CPCS -PDU into frame. In the case of interworking, a high-performance processor is required to process the Multiprotocol Encapsulation function supporting the transmission of X.25 and LAN and the like, and a high performance processor. In order to handle the traffic of the DS1 / E1 frame relay, it is solved by using two processors as described above. As mentioned above, the function of FIG. 2 is the most important function of the processor control unit 542, and the DS1 / E1 connection unit 533, the DS1 / E1 register 523, and the HDLC control unit (2) are largely implemented to realize such a function. 522, the AAL5 packet reception control section 563, and the AAL5 packet transmission control section 573, and initializes and controls elements. In addition, by transmitting the defined message with the FMDA (300) through the IPC transmitter 550, it is possible to oversee the maintenance information and the like other than the user information transmission in the FMDA (300).

The RS232C controller 541 provides a man-machine interface, and the present invention uses a universal asynchronous receiver and transmission (UART) function provided by the MC68360 and a signal conversion device between the TTL and the RS232C.

The bus arbitration unit 531 smoothly mediates the sharing of the data bus and the address bus between the processor and the various devices. In the present invention, the bus arbitration unit 531 is implemented as AHDL, which is a type of VHDL, using the EPLD EPM9560GC 280. The HDLC control unit 522, the AAL5 packet reception control unit 563, and the AAL5 packet transmission control unit 573 share the reception packet memory unit 561 and the transmission packet memory unit 571, and perform data by using DMA when writing and reading data. Thus, it becomes a one-time bus master, and the processor also needs to write / read these memories. Therefore, the bus arbitration unit 531 combines the events in each device to smoothly mediate when two or more devices to write or read the same memory occur simultaneously and to control the bus to be used efficiently. Do this. For example, an event in which the HDLC control unit 522 receives one frame through DS1 / E1 requires writing to the reception packet memory unit 561, and an event in which an ATM cell is received through the FIFO receiving unit 564 is transmitted. The packet memory unit 571 needs to be written. In this case, since different memories are used, simultaneous processing is possible by controlling the buffer to use the address and data buses as local buses in the bus arbiter.

The interrupt control unit 532 generates a function for smoothly and efficiently controlling interrupts in various devices and generates control signals required for the AAL5 packet transmission control unit and the AAL5 packet reception control unit. In addition, the self test receives the cell output from the AAL5 packet transmitter from the interrupt controller and inputs it to the FIFO receiver. In addition, it performs a function of resetting peripheral devices. In this example, the same EPLD EPM9560GC280 is used.

As described above, according to the present invention, the DS1 / E1 can be used as the DS1 / E1, which can be used as the DS1 / E1 according to the elements of the DS1 / E1 synchronizer 523, and multiple subscribers are multiplexed to one DS1 / E1. There is an effect that it is possible to provide a channelized frame relay that is serviced, and thus it is also possible to be unchannelized to allocate one subscriber to DS1 / E1 when necessary. In addition, there is another advantage in processing DS1 / E1, which is slower than STM-1 155Mbps in ATM, in order to efficiently use processor and AAL5 devices.

Due to the present invention, a frame relay subscriber and a network can be directly connected to an ATM switch, and a service can be converted and provided without a recognition of an ATM subscriber or a frame relay subscriber in communication between an ATM subscriber and a frame relay subscriber by a service interworking function. There is another effect.

Claims (7)

An HDLC controller which physically connects to a frame relay subscriber with DS1 / E1 and configures and transmits a frame with a flag and an FCS; A packet transmitter for converting AAL5 packet data into an ATM cell for transmission; A packet receiver configured to receive an ATM cell and assemble AAL5 packet data; An auxiliary controller configured to control a bus and an interrupt so that the HDLC controller, the packet transmitter, and the packet receiver operate efficiently; A clock / power supply unit configured to receive a clock, supply a clock to a packet, a receiver, and the like, and input + 48V to supply + 5V; And a total control unit that has a processor, performs an IPC with an upper processor, provides an interface means between a human-machine, and controls and monitors the functions of all peripheral devices. Service Interlock. 2. The apparatus of claim 1, wherein the HDLC control unit comprises: a DS1 / E1 line connecting means for recovering a clock from a DS1 / E1 line connected in a frame relay subscriber direction and detecting a failure; DS1 / E1 synchronization means for recovering data using DPLL and monitoring CRC multi-frame setting and performance using it; HDLC control means for connecting the DS1 / E1 synchronization means with the PCM by way of highways and having 32 HDLC functions per DS1 / E1 and configuring frames with flags and FCSs and transmitting them through the DS1 / E1 transmission means; And HDLC control storage means used by the processor to control the memory through the memory so that the HDLC control means transmits and receives the frame. The frame and the AAL5 CPCS-PDU of claim 1, wherein the packet transmitter converts a frame received through the HDLC control unit into an AAL5 CPCS-PDU, decomposes it into an ATM cell, and transmits the frame information to the exchanger. Receive packet storage means for storing; A packet transmission control means for padding the AAL5 CPCS-PDU with 0 and adding a trailer to an integer multiple of 48 bytes, putting it in a payload of an ATM cell, assembling it into an ATM cell, and transmitting the packet; Transmission control storage means used by the processor to control via a memo so that the packet transmission control means performs transmission control; And the packet transmission control step comprises a FIFO transmission means which is a transmission port of an ATM cell for transmitting the ATM cell. 2. The apparatus of claim 1, wherein the packet receiving unit comprises: packet reception control means for receiving an ATM cell and assembling an AAL5 CPCS-PDU; Transmission packet storage means for storing the user information so that the processor changes the information into frame-type user information so that the packet reception control means performs reception control and transmits it to the frame by the HDLC control unit; And the packet reception control means comprises a FIFO receiving means serving as a receiving port of an ATM cell for receiving the ATM cell. 2. The apparatus of claim 1, wherein the auxiliary control unit comprises: bus arbitration means for efficiently using an address bus and a data bus; And collecting interrupt sources to efficiently handle interrupts generated from various peripheral devices, generating control signals necessary for the packet transmitter and the packet receiver, and forming a loopback from the packet transmitter to the packet receiver during self-test. Frame relay network / service interworking apparatus for processing per channel in the ATM switch, characterized in that the control means. 2. The apparatus of claim 1, wherein the entire control unit comprises: conversion means for converting every frame into an AAL5 CPCS-PDU, and further converting an AAL5 CPCS-PDU assembled by receiving and assembling an ATM cell; Processor control means for initializing and controlling all peripheral function blocks; Human-machine interface means for providing an interface between a human-machine; Frame relay network / service interworking apparatus for processing per channel in the ATM switch, characterized in that the processor means having a sufficient capability to perform the function by connecting to the four DS1 / E1. The method of claim 6, wherein the conversion means analyzes the header information related to the frame with respect to the packet receiver and finds the VPI / VCI of the ATM by reflecting the frame information, and the user requests the service interworking and multi-protocol encapsulation. Information is converted into an AAL5 CPCS-PDU in a frame which is converted into an ATM standard to form an AAL5 CPCS-PDU; The service interworking and multi-protocol encapsulation functions are required for the AAL5 CPCS-PDU which receives the VPI / VCI associated with the AAL5 CPCS-PDU from the packet receiver, recognizes the head of the frame corresponding to the packet transmitter. The frame relay processed by the channel in the ATM exchange which converts the information of the user to the frame relay standard and performs the conversion function from the AAL5 CPCS-PDU to the frame which positions the frame head at the top after such conversion. Network / Service Interlock.