KR19990085948A - Frame Relay Protocol Processing Unit - Google Patents

Abstract

The present invention relates to a frame relay protocol, which is one of the interface standards between an IWF (Interworking Function) and a mobile communication exchange defined in IS-658 for wireless data service in a code division multiple access (CDMA) mobile communication system. Frame relay protocol).

The present invention secures a frame relay technology that is not currently implemented in a switching system, and thus has a low protocol complexity and a low rate of information transmission per hour, which are disadvantages in packet switching or circuit switching. In order to overcome this problem and achieve efficient and high-speed transmission, transmission is performed using a main processor that includes a high-level Data Link Control (HDLC) controller function and a link access procedure for frame mode bearer service (LAPF) processing program. Alternatively, an apparatus for processing an L2 protocol, which is a data link layer among matching functions in a mobile communication switching system, may be achieved by controlling a data link for switching and performing LAPF processing.

Description

Frame Relay Protocol Processing Unit

The present invention relates to an interface device of a code division multiple access (CDMA) switching system, and more particularly, to an apparatus for processing an L2 protocol, which is a data link layer corresponding to a frame relay technology. will be.

In general, as a switching method of a mobile switching system, the circuit selects and connects a circuit every time it communicates, and sends a data by dividing it into packets of a certain length and a circuit switching method that separates the circuit after termination. There is a packet switching method that shares a line without occupying the network.

Compared to the frame relay technology, which is not yet implemented in the switching system, the circuit switching or packet switching method is a barrier to information transmission because the information transmission rate is low and the protocol is complicated.

In order to overcome such obstacles and the disadvantage that the information transmission rate per hour is low, a large amount of time is required to deliver a large amount of information. The newly emerged protocol devotes retransmission control in case of transmission error to realize high-speed transmission. It is a frame relay protocol that realizes data multiplexing at the link layer level (Layer 2).

In the CDMA mobile communication system using the frame relay method, a network element called an IWF (InterWorking Function) is newly added.

However, in the related art, an efficient and suitable apparatus for processing Q.922 (LAPF: Link Access Procedure for Frame mode bearer service), which is a Layer 2 protocol, which is a data link layer among frame relay protocols for accessing and matching the mobile communication switch and the IWF. There was no problem.

Accordingly, the present invention has been proposed to solve the conventional problems as described above, and an object of the present invention is to provide a code division multiple access (CDMA) mobile communication system using a frame relay protocol. Frame that can handle Q.922 (LAPF: Link Access Procedure for Frame mode bearer service), a Frame Relay Layer 2 protocol, among interface devices connecting IWF (InterWorking Function) and mobile communication switch added for wireless data service The present invention provides a relay protocol processing apparatus.

In order to achieve the above object, a frame relay protocol processing apparatus according to the present invention includes: a main processor having a high-level data link control (HDLC) controller function and controlling LAPF processing and overall operation; Fast Static Random Access Memory (FSRAM) used for high speed data storage to speed up data processing in the LAPF protocol processing; A field programmable gate array (FPGA) unit for allowing a user to create a program of the system; The second DPRAM (Dual Port RAM), which exchanges signal data through the L3 layer and the VERSA Module European (VME) bus, and the Operating System (OS) and Link Access Procedure for Frame mode bearer service (LAPF) programs stored in the ROM will be installed. DRAM (Dynamic RAM); Technical features include a sub highway (SHW) interface unit for matching pure data input from the mobile station to the exchanger, and a framer and LIU unit for trunk interface.

1 is a block diagram showing a frame relay protocol processing apparatus of the present invention;

2 is a flowchart illustrating a frame relay protocol process according to the present invention.

<Explanation of symbols for the main parts of the drawings>

1: main processor 3: FPGA

7: second DPRAM 8: DRAM

12: Framer & Line Interface (Framer & LIU)

Hereinafter, an embodiment according to the technical spirit of the present invention, the frame relay protocol processing apparatus configured as described above will be described in detail.

1 is a block diagram showing the configuration of a frame relay protocol processing apparatus.

As shown therein, a main processor unit 1 having a 32-channel HDLC (High-level Data Link Control) function using a Motorola MC68MH360 as a main processor; An FPGA (Field Programmable Gate Arrary) unit 3 which enables a user to easily program an operation sequence in which data is processed; 256Kbyte local local random access memory (SRAM) for basic memory configuration; A 256Kbyte ROM (ROM) 5 for a program in which an OS and a LAPF processing program are stored; Fast Static RAM (FSRAM) 2 for frame relay data transmission / reception, which stores pure data output from the mobile station at high speed; A first Dual Port RAM 6 for communicating with a Rate Adapation portion; A second DPRAM 7 for exchanging signal data with the L3 layer via a VERSA Module European (VME) bus; A DRAM (Dynamic RAM, Dynamic RAM) 8 on which an operating system (OS) of the ROM 5 and a link access procedure for frame mode bearer service (LAPF) program are to be mounted; A digital switch section 9 for channel switching; A Framer & LIU (Line Interface Unit) unit 12 for a trunk interface; A clock generator 10 for supplying a clock to the system; It is characterized in that it is composed of a SHW (Sub HighWay) interface unit 11 for receiving data, clock and frame synchronization signals from the time switch.

Although not shown in the drawing, the FPGA (Field Programmable Gate Arrary) unit 3 is an error for notifying that the reset unit for the reset operation of the system, the error processing, and the data signal have been normally received. Detection and DSACK (Data Signal Acknowledgment) Generator and Multiple I / O (Input / Output) Chips and Memory Connected to System Bus A status divider with status information about the clock divider to obtain an output proportional to the division of one clock into another clock, and a clock fail detection and clock multiplexer and a VME bus to multiplex the wrong clock and clock. It is composed of VME control unit for matching and control.

Referring to Figure 1 attached to the operation of the frame relay protocol processing apparatus according to the present invention configured as described above are as follows.

First, the packet, asynchronous, and fax data, which are pure data entered from the mobile station to the mobile communication switch via the base station and the control station, are switched through a time switch and enter the sub highway (SHW) interface unit 11.

The pure data enters the 32 channel HDLC (high level data link control) of the main processor 1 of the MC68MH360 and is subjected to LAPF processing by a link access procedure for frame mode bearer service (LAPF) processing program. The signal data transferred to the second DPRAM 7 through the VME bus is added to the pure data, and processed LAPF, and then through the digital switch unit 9 and the trunk through the framer & LIU (Line Interface Unit) unit 12. ) Is sent to the interface part.

In order to increase the data processing speed during the LAPF protocol processing, data is stored in a fast static RAM (FSRAM) 2 prepared for high-speed data storage.

The FSRAM 2 is prepared in sufficient size as follows in consideration of the frame relay protocol characteristics.

That is, frame relay maximum packet size × Number of channels × Send / Receive (Tx, Rx) × Appropriate Frame Rate (16) = 1600 × 32 × 2 × 16 = 1638400 = 1.64 MBytes are prepared.

In order to process the LAPF signal quickly, the interface on the L3 side of the second DPRAM 7 for communication with L3, which is a network layer, uses a VME bus.

In addition, in order to increase the channel utilization, the data transmission channel and the signal transmission channel are separated from each other and the receiving portion determines whether the received data is the signal data or the pure data when receiving the data, and if the signal data is transmitted to the second DPRAM 7 to L3. If the data is transmitted to the processing unit, the data is stored in the FSRAM 2 and transmitted to the receiving subscriber via the base station and the control station through the SHW interface unit 11.

Upon reception, the data coming in through the trunk line is extracted as serial data through the Framer & LIU unit 12 and then enters the MC68MH360 which is the main processor 1 via the digital switch 9.

Here, after the LAPF processing is performed by software using HDLC, the signal data is sent to the L3 processing unit through the VME bus through the second DPRAM 7, and the pure data is transmitted to the subscriber through the time switch.

2 is a flowchart illustrating a procedure of executing firmware by the frame relay protocol processing device of the present invention.

As shown therein, first, the entire initialization routine of the apparatus in which each register and memory inside the MC68MH360 is initialized is executed (ST 1).

Next, a test is performed on each part of the entire hardware that performs the test work on the SRAM, DRAM, DPRAM, FSRAM, digital switch, Framer & LIU (ST 2).

After the test operation, the OS and the LAPF software mounted in the ROM are moved to the DRAM area (ST 3).

Here, the reason for moving these OSs and LAPFs in the ROM to the DRAM area is that the DRAM has a faster data access speed than the ROM.

In addition, by using DRAM, many memory buffers required for protocol processing can be provided. This is also because the ROM is accessed with 16 bits due to the hardware structure of the device, but the DRAM is designed with a 32-bit data bus.

After the operating system (OS) is started (ST 4), events related to each processing task and time are registered with the scheduler (ST 5).

The scheduler registration (ST5) also includes the physical layer L1 hardware initialization and LAPF protocol.

After the operation is performed, event processing and schedule processing are performed according to the state registered in the scheduler (ST 6), and the task ST 6 continues by looping.

As described above, the frame relay protocol processing apparatus according to the present invention is required to be essentially accommodated for the implementation of the frame relay interface technology for wireless data service, which is currently required to add its functions by almost all carriers. By implementing the Frame Relay Layer 2 protocol processing device, it is possible to transmit high-efficiency and high-speed data by overcoming the shortcomings of existing packet communication. Can also be applied.

In addition, high-speed data transfer technology is required in the future of IMT-2000, and it can be applied. In the next-generation ATM (Asynchronous Transfer Mode) exchange technology, a connection with a frame relay network is required. There is an effect that can be used.

Claims (1)

In the frame relay protocol processing apparatus, A sub-highway interface unit for receiving pure data from the mobile station and transmitting pure data processed by the exchange to other subscribers; Dual Port RAM (DPRAM) for exchanging signal data through L3 layer (Layer3, network layer) and VME bus; A main processor that receives pure data from the subhighway interface unit and performs link access procedure for frame (LAPF) processing by adding the signal data input to the DPRAM, and has a high-level data link control (HDLC) function to control the overall operation; A digital switch for switching LAPF processed data in the main processor; A framer and line interface unit for framing the signal switched by the digital switch under the control of the main processor to interface with the trunk of the receiver; An FSRAM for storing pure data at a high speed during LAPF processing under the control of the main processor; A ROM (OS) in which an OS (Operating System) for reading information by the main processor and a LAPF program are stored; DRAM on which the OS and LAPF programs stored in the ROM are mounted; The operating sequence for processing data in the exchange is programmed and includes a field programmable gate array (FPGA) unit having a reset logic, chip select logic, clock divider, status register, error detection, and VME controller function. Frame relay protocol processing unit.