KR0182251B1 - Method of fabricating bipolar transistor - Google Patents
Method of fabricating bipolar transistor Download PDFInfo
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- KR0182251B1 KR0182251B1 KR1019950054398A KR19950054398A KR0182251B1 KR 0182251 B1 KR0182251 B1 KR 0182251B1 KR 1019950054398 A KR1019950054398 A KR 1019950054398A KR 19950054398 A KR19950054398 A KR 19950054398A KR 0182251 B1 KR0182251 B1 KR 0182251B1
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- 239000012535 impurity Substances 0.000 abstract description 4
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- 230000015556 catabolic process Effects 0.000 description 2
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- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
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- H—ELECTRICITY
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
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Abstract
본 발명은 에미터영역의 에지부위에서의 전계밀집 현상을 개선하도록 한 바이폴라 트랜지스터의 제조방법을 개시한다. 이 방법은 기판에 제1도전형의 콜렉터영역을 형성하는 단계, 상기 콜렉터영역에 제2도전형의 베이스영역을 형성하는 단계, 상기 베이스영역 상에 소정 사이즈의 개구부들을 갖는 절연막의 패턴을 형성하는 단계, 상기 절연막의 패턴을 마스크로 이용하여 제1도전형의 불순물을 이온주입하고 이를 확산시켜 상기 베이스영역에 에미터영역을 형성하는 단계를 포함하되 상기 개구부들의 사이즈를 상기 에미터영역의 중심으로부터 외곽으로 갈수록 작게 형성한다.The present invention discloses a method of manufacturing a bipolar transistor to improve the field density phenomenon at the edge portion of the emitter region. The method includes forming a collector region of a first conductivity type on a substrate, forming a base region of a second conductivity type on the collector region, and forming a pattern of an insulating film having openings of a predetermined size on the base region. And forming an emitter region in the base region by implanting impurities of the first conductivity type using the pattern of the insulating layer as a mask and diffusing them to form an emitter region in the base region. The smaller it goes to the outer shape.
따라서, 에미터영역과 베이스영역의 접합부위가 완만하게 형성되어 에미터영역의 접합깊이가 그 중앙부위에서 외관방향으로 갈수록 작아지므로 에미터 에지 영역에서의 전계 밀집효과가 개선되고 전류능력의 증가와 동시에 스위칭 스피드 개선이 이룩된다.Therefore, the junction area between the emitter region and the base region is formed smoothly, and the junction depth of the emitter region becomes smaller from the center portion toward the outer direction, so that the electric field density effect in the emitter edge region is improved and the current capability increases. The switching speed improvement is achieved.
Description
본 발명은 바이폴라 트랜지스터의 제조방법에 관한 것으로, 특히 에미터의 에지부분의 전계밀집(electric field crowding) 현상을 개선할 수 있도록 한 바이폴라 트랜지스터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bipolar transistor, and more particularly, to a method for manufacturing a bipolar transistor that can improve electric field crowding at the edge of an emitter.
바이폴라 트랜지스터는 그 응용회로에서, 증폭단이나 스위칭 동작단에 주로 사용되어 왔으며, 최근의 응용기기의 대형화 대용량화 추세에 따라 고내압(high breakdown voltage), 대전류(high current) 및 이에 대한 고속의 스위칭 특성이 중요하게 대두되고 있다.Bipolar transistors have been mainly used in amplification stages or switching operation stages in their application circuits, and according to the recent trend of large-scale and large-capacity applications, high breakdown voltage, high current, and high-speed switching characteristics thereof It is important.
최근의 바이폴라 트랜지스터의 기술 동향은 칩의 크기를 증가시키지 않으면서도 전류용량을 증가시킬 수 있는 방법에 대한 연구가 주류를 이루어 왔다.Recently, the technology trend of the bipolar transistor has been the mainstream research on how to increase the current capacity without increasing the size of the chip.
종래의 일반적인 바이폴라 트랜지스터의 구조에서는 트랜지스터 동작시 에미터 측면의 에지쪽으로 전류가 집중되는 에미터 밀집(emitter crowding)현상이 심각하여 대전류의 실현이 어렵다.In the structure of a conventional general bipolar transistor, emitter crowding, in which current is concentrated toward an edge of an emitter side during transistor operation, is serious, and thus, realization of a large current is difficult.
도1은 종래 기술에 따라 형성된 바이폴라 트랜지스터를 도시한 단면도이다.1 is a cross-sectional view showing a bipolar transistor formed according to the prior art.
도1에 도시된 바와 같이, 기판(도시 안됨)의 N형 콜렉터영역(10)상에 P형 베이스영역(12)이 형성되고, 베이스영역(12)에 N+형 에미터영역(14)이 형성된다. 에미터영역(14)과 베이스영역(12) 사이의 표면 상에 에미터영역(14)과 베이스영역(12)을 위한 콘택홀을 갖는 절연층(16)의 패턴이 형성되고, 에미터전극(18)과 베이스전극(20)이 각각 에미터영역(14)과 베이스영역(12)에 전기적으로 연결된다. 기판의 콜렉터영역(10)의 하부면에 콜렉터전극(22)이 형성된다.As shown in FIG. 1, a P-type base region 12 is formed on an N-type collector region 10 of a substrate (not shown), and an N + type emitter region 14 is formed on the base region 12. Is formed. On the surface between the emitter region 14 and the base region 12, a pattern of an insulating layer 16 having contact holes for the emitter region 14 and the base region 12 is formed, and the emitter electrode ( 18 and the base electrode 20 are electrically connected to the emitter region 14 and the base region 12, respectively. The collector electrode 22 is formed on the lower surface of the collector region 10 of the substrate.
여기서, 점선은 에미터영역(14)과 베이스영역(12)의 접합 계면에서의 공핍층을 나타낸다.Here, the dotted line indicates the depletion layer at the junction interface between the emitter region 14 and the base region 12.
그런데, 종래에는 에미터영역(14)과 베이스영역(12) 양단에 인가된 순방향 바이어스가 에미터의 에지부위에서 가장 크게 인가되고, 이에 따라 도1의 원 내부에 화살표로 도시된 바와 같이, 에미터영역의 측면 에지부분에서 전계집중이 커져 전류의 흐름이 상기 에지부위에 많이 몰리게 된다. 또한 이러한 전계집중의 증가는 상기 에지부위에서 충돌전리(impactionization)를 일으키고, 따라서, 에미터-베이스 간의 브레이크다운(breakdown)이 에지부분에서 주로 발생한다.However, in the related art, the forward bias applied to both the emitter region 14 and the base region 12 is most applied at the edge portion of the emitter, and accordingly, as shown by the arrow in the circle of FIG. The field concentration is increased at the side edge portion of the rotor region, and current flows a lot at the edge portion. This increase in field concentration also results in impulseization at the edge, so breakdown between emitter and base occurs mainly at the edge.
이러한 현상은 상기 에미터영역(14) 에지부위의 각도가 작을수록, 즉 에지부위가 뾰족할수록 심화된다.This phenomenon is exacerbated as the angle of the edge portion of the emitter region 14 is smaller, that is, the sharper edge portion is.
따라서, 본 발명의 목적은 에미터 에지부분의 전계밀집현상을 개선할 수 있는 바이폴라 트랜지스터의 제조방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a method of manufacturing a bipolar transistor that can improve the field density phenomenon of the emitter edge portion.
제1도는 종래 기술에 따라 형성된 바이폴라 트랜지스터를 도시한 단면도.1 is a cross-sectional view illustrating a bipolar transistor formed according to the prior art.
제2도는 본 발명의 일 실시예에 따라 제조된 바이폴라 트랜지스터를 도시한 단면도.2 is a cross-sectional view illustrating a bipolar transistor manufactured according to an embodiment of the present invention.
제3도는 본 발명의 일 실시예에 따른 바이폴라 트랜지스터의 제조방법을 설명하기 위해 도시한 단면도.3 is a cross-sectional view illustrating a method of manufacturing a bipolar transistor according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
50 : 콜렉터영역 52 : 베이스영역50: collector area 52: base area
54 : 산화막의 패턴 56 : 에미터영역54 pattern of oxide film 56 emitter region
58 : 절연층 60 : 베이스전극58: insulating layer 60: base electrode
62 : 베이스전극 64 : 콜렉터전극62: base electrode 64: collector electrode
상기 목적을 달성하기 위하여 본 발명은 기판에 제1도전형의 콜렉터영역을 형성하는 단계; 상기 콜렉터영역에 제2도전형의 베이스영역을 형성하는 단계; 상기 베이스영역 상에 소정 사이즈의 개구부들을 갖는 절연막의 패턴을 형성하는 단계; 상기 절연막의 패턴을 마스크로 이용하여 제1도전형의 불순물을 이온주입하고 이를 확산시켜 상기 베이스영역에 에미터영역을 형성하는 단계를 포함하되 상기 개구부들의 사이즈를 상기 에미터영역의 중심으로부터 외곽으로 갈수록 작게 형성하는 것을 특징으로 한다.In order to achieve the above object, the present invention comprises the steps of forming a collector region of the first conductivity type on the substrate; Forming a base region of a second conductivity type in the collector region; Forming a pattern of an insulating film having openings of a predetermined size on the base region; Implanting an impurity of a first conductivity type using a pattern of the insulating film as a mask and diffusing the same to form an emitter region in the base region, wherein the size of the openings is formed from the center of the emitter region to the outside. It is characterized by forming smaller and smaller.
바람직하게는 상기 절연막의 패턴을 산화막으로 형성한다.Preferably, the pattern of the insulating film is formed of an oxide film.
본 발명에 따르면, 에미터영역과 베이스영역의 접합부위가 완만하게 형성되어 에미터영역의 접합깊이가 그 중앙부위에서 외곽방향으로 갈수록 작아진다. 따라서, 본 발명은 에미터 에지 영역에서의 전계 밀집효과를 개선하여 전류능력을 증가시킴과 동시에 스위칭 스피드를 개선할 수 있다.According to the present invention, the joint portion of the emitter region and the base region is formed smoothly so that the junction depth of the emitter region becomes smaller from the center portion toward the outer direction. Therefore, the present invention can improve the field density in the emitter edge region to increase the current capability and at the same time improve the switching speed.
이하, 첨부한 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in more detail the present invention.
도2는 본 발명의 일 실시예에 따라 제조된 바이폴라 트랜지스터를 도시한 단면도이다.2 is a cross-sectional view illustrating a bipolar transistor manufactured according to an embodiment of the present invention.
도2에 도시된 바와 같이, 콜렉터영역(50)에 베이스영역(52)이 형성되고, 베이스영역(52)에 에미터영역(56)이 형성되고, 베이스영역(52)과 에미터영역(56) 사이의 표면 상에 에미터전극(60)과 베이스전극(62)의 콘택홀을 갖는 절연층(58)의 패턴이 형성되고, 에미터전극(60)과 베이스전극(62)이 각각 에미터영역(56)과 베이스영역(52)에 전기적으로 연결된다. 콜렉터전극(64)이 기판의 하부면에 형성된다.As shown in Fig. 2, the base region 52 is formed in the collector region 50, the emitter region 56 is formed in the base region 52, and the base region 52 and the emitter region 56 are formed. A pattern of the insulating layer 58 having contact holes of the emitter electrode 60 and the base electrode 62 is formed on the surface between them, and the emitter electrode 60 and the base electrode 62 are respectively emitters. It is electrically connected to the region 56 and the base region 52. The collector electrode 64 is formed on the lower surface of the substrate.
상기한 구조에 따르면, 종래에 비해 에미터영역(56)의 에지 부위의 각도가 커지고 에지 영역이 넓어져, 에미터-베이스 접합부위가 완만하게 형성되어 있으므로, 에미터영역의 측면 에지부분에서 발생되는 전계가 원내부의 화살표로 표시된 바와 같이, 분되고 전류밀집 현상이 개선된다.According to the above structure, since the angle of the edge portion of the emitter region 56 is larger and the edge region is wider than the conventional one, the emitter-base junction is formed smoothly, so that it occurs at the side edge portion of the emitter region. The electric field to be divided is broken down as indicated by the arrow inside the circle, and the current density phenomenon is improved.
도3은 본 발명의 일 실시예에 따른 바이폴라 트랜지스터 제조방법을 설명하기 위해 도시한 단면도이다.3 is a cross-sectional view illustrating a bipolar transistor manufacturing method according to an embodiment of the present invention.
도3에 도시된 바와 같이, 먼저, 기판(도시 안됨)에 형성된 제1도 전형의 콜렉터영역(50) 내에 통상의 방법을 이용하여 제2도전형의 베이스영역(52)을 형성한다.As shown in FIG. 3, first, the base region 52 of the second conductive type is formed in the first conductive type collector region 50 formed on the substrate (not shown) using a conventional method.
베이스영역(52)이 형성되고 나면, 그 결과물 상에 절연막, 예컨대 산화막을 증착하고 그 산화막을 에미터영역(56)의 형성을 위한 개구부들이 개구된 산화막(54)의 패턴으로 형성한다. 이를 좀 더 상세히 언급하면, 개구부들을 에미터영역(56)의 중심으로부터 외곽으로 갈수록 h1, h2, h3,..., hn의 사이즈로 각각 형성한다. 여기서, h1은 h2보다 크고, h2는 h3보다 크고, h3은 hn보다 크다.After the base region 52 is formed, an insulating film, for example, an oxide film is deposited on the resultant, and the oxide film is formed in a pattern of the oxide film 54 with openings for forming the emitter region 56. In more detail, the openings are formed in sizes h1, h2, h3,..., Hn as they go outward from the center of the emitter region 56. Where h1 is greater than h2, h2 is greater than h3, and h3 is greater than hn.
즉 개구부들을 에미터영역(56)의 중심으로부터 외곽으로 갈수록 작은 사이즈로 형성한다.That is, the openings are formed in a smaller size from the center of the emitter region 56 toward the outside.
이후, 산화막(54)의 패턴을 마스크로 사용하고 상기 결과물 내에 제1도전형 불순물을 이온주입하고 이를 확산시켜 베이스영역(52)에 에미터영역(56)을 형성한다.Subsequently, the emitter region 56 is formed in the base region 52 by using the pattern of the oxide film 54 as a mask and ion implanting the first conductive impurity into the resulting product.
에미터영역(56)이 형성되고 나면, 산화막(54)의 패턴을 제거하고 도2에 도시된 바와 같이, 상기 기판 상에 절연층(58)을 적층하고 나서 절연층(58)에 통상의 사진식각공정에 의해 에미터전극(60)과 베이스전극(62)을 위한 콘택홀을 형성하고 각각의 콘택홀을 거쳐 에미터영역(56)과 베이스영역(52)에 전기적으로 접촉하는 에미터전극(60)과 베이스전극(62)을 형성한다. 또한, 기판의 하부면에 콜렉터전극(64)을 형성하여 바이폴라 트랜지스터를 완성한다. 따라서, 본 발명은 도3에 도시된 바와 같이, 에미터영역의 에지부위가 넓고 완만한 형태를 갖도록 형성할 수 있다. 이는 개구부의 크기에 따라 불순물 주입량이 달라지게 되고, 수직 및 측면확산이 결정되기 때문이다.After the emitter region 56 is formed, the pattern of the oxide film 54 is removed, and an insulating layer 58 is laminated on the substrate as shown in FIG. By forming an contact hole for the emitter electrode 60 and the base electrode 62 by an etching process, the emitter electrode electrically contacting the emitter region 56 and the base region 52 through the respective contact holes ( 60 and the base electrode 62 are formed. In addition, the collector electrode 64 is formed on the lower surface of the substrate to complete the bipolar transistor. Therefore, the present invention can be formed such that the edge portion of the emitter region is wide and smooth, as shown in FIG. This is because the amount of impurity injection varies depending on the size of the opening, and the vertical and side diffusions are determined.
이상에서 살펴본 바와 같이 본 발명에 따른 바이폴라 트랜지스터의 제조방법에 의하면, 에미터-베이스 접합부위가 완만하게 형성되므로 에지부위에서 전계가 분산되므로 전류밀집 현상이 개선된다.As described above, according to the method of manufacturing the bipolar transistor according to the present invention, since the emitter-base junction portion is formed smoothly, the electric current is dispersed at the edge portion, thereby improving current density.
따라서, 본 발명은 전류능력을 향상시킬 수 있다. 뿐만 아니라, 종래의 구조에 비해 에미터영역의 외곽부위의 농도가 낮아 스위치 '온'시 에미터에서 베이스로 이동되는 캐리어가 작게되고 그 결과, '오프'시 캐리어의 추출 시간이 짧아져 스위칭 스피드가 개선될 수 있으며, 특히 캐리어의 축적시간 측면에서의 효과가 크다.Therefore, the present invention can improve the current capability. In addition, the concentration of the outer portion of the emitter region is lower than that of the conventional structure, so that the carrier moving from the emitter to the base when the switch is 'on' is small, and as a result, the extraction time of the carrier is shortened when the 'off' is switched. Can be improved, especially in terms of the accumulation time of the carrier.
한편, 본 발명을 일실시예를 들어 한정적으로 설명하였으나, 이에 한정되지 않고 본 발명의 사상의 범위 내에서 당해 분야의 통상의 지식을 가진 자에 의해 본원 발명에 대한 각종 변형이 가능함은 자명하다.On the other hand, the present invention has been described by way of example only, but not limited to this, it is obvious that various modifications to the present invention can be made by those skilled in the art within the scope of the spirit of the present invention.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950054398A KR0182251B1 (en) | 1995-12-22 | 1995-12-22 | Method of fabricating bipolar transistor |
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| KR1019950054398A KR0182251B1 (en) | 1995-12-22 | 1995-12-22 | Method of fabricating bipolar transistor |
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| KR970052985A KR970052985A (en) | 1997-07-29 |
| KR0182251B1 true KR0182251B1 (en) | 1999-04-15 |
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