KR0169790B1 - A vertical structure bipolar transistor with large current and high speed switching characteristics and method for manufacturing thereof - Google Patents
A vertical structure bipolar transistor with large current and high speed switching characteristics and method for manufacturing thereof Download PDFInfo
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- KR0169790B1 KR0169790B1 KR1019950050544A KR19950050544A KR0169790B1 KR 0169790 B1 KR0169790 B1 KR 0169790B1 KR 1019950050544 A KR1019950050544 A KR 1019950050544A KR 19950050544 A KR19950050544 A KR 19950050544A KR 0169790 B1 KR0169790 B1 KR 0169790B1
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- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 229910052742 iron Inorganic materials 0.000 claims abstract description 3
- 230000001788 irregular Effects 0.000 claims abstract 2
- 238000005530 etching Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 3
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- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000002347 injection Methods 0.000 abstract description 9
- 239000007924 injection Substances 0.000 abstract description 9
- 239000000969 carrier Substances 0.000 abstract description 2
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- 229910052710 silicon Inorganic materials 0.000 description 3
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- 230000007423 decrease Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
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- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Abstract
본 발명은 대전류 및 고속 스위칭 특성을 갖는 수직 구조 바이폴라 트랜지스터에 관한 것으로서, 콜렉터로 사용되는 제1전도형의 반도체기판; 상기 기판 상에 침적되어 있고, 상부가 요철(凹凸)을 이루는 제2전도형의 베이스 확산 영역; 상기 베이스 확산 영역의 철(凸)부에 형성된 제1전도형의 불순물이 주입된 에미터 영역; 상기 베이스 확산 영역의 상부에 침적된 절연막; 상기 절연막을 통해 하부의 메이터 영역 및 베이스 영역과 각각 연결된 제1 및 제2전극을 포함하여 이루어진 것으로, 에미터에서 베이스로 캐리어 주입시 측면으로의 주입을 방지하여 에미터 주입 효율이 커지므로 전류 특성이 향상되고 에미터 엣지로의 전류밀집 현상을 방지할 수 있으며, 또한 스위치 '온'시 콜렉터 저농도 영역에 축적된 캐리어가 '오프'시 베이스 전극으로 추출될 때 캐리어의 흐르는 경로의 저항이 줄어드는 효과가 있어 스위칭 속도가 개선된다.The present invention relates to a vertical bipolar transistor having high current and high speed switching characteristics, comprising: a first conductive semiconductor substrate used as a collector; A base diffusion region of a second conductivity type deposited on the substrate and having an irregular top portion; An emitter region in which impurities of a first conductivity type formed in the iron portion of the base diffusion region are implanted; An insulating film deposited on the base diffusion region; It includes first and second electrodes connected to the lower mater region and the base region through the insulating film, respectively, to prevent the injection to the side when the carrier is injected from the emitter to the base to increase the emitter injection efficiency of the current characteristics This improves and prevents current density toward the emitter edge and reduces the resistance of the carrier's flowing path when carriers accumulated in the collector low concentration region at switch 'on' are extracted to the base electrode at 'off' The switching speed is improved.
Description
제1도는 종래 바이폴라 트랜지스터의 구조 단면도.1 is a structural cross-sectional view of a conventional bipolar transistor.
제2도는 종래 다른 바리폴라 트랜지스터의 구조 단면도.2 is a structural cross-sectional view of another conventional baripolar transistor.
제3도는 종래 또 다른 바이폴라 트랜지스터의 구조 단면도.3 is a structural cross-sectional view of another conventional bipolar transistor.
제4도는 본 발명에 따른 바이폴라 트랜지스터의 구조 단면도.4 is a structural cross-sectional view of a bipolar transistor according to the present invention.
제5도는 본 발명에 따른 바이폴라 트랜지스터의 구조 단면도.5 is a structural cross-sectional view of a bipolar transistor according to the present invention.
제6도는 본 발명에 따른 바이폴라 트랜지스터의 구조 단면도.6 is a structural cross-sectional view of a bipolar transistor according to the present invention.
제7도는 본 발명에 따른 바이폴라 트랜지스터의 제조 공정도.7 is a manufacturing process diagram of a bipolar transistor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 실리콘 기판 20 : 베이스 확산 영역10 silicon substrate 20 base diffusion region
30,30a : 에미터 영역 40 : 절연막30,30a: emitter region 40: insulating film
50,50a,51,52 : 전극 60,60a : 인액티브 영역50, 50a, 51, 52: electrode 60, 60a: inactive area
70 : 접합부위70: junction
본 발명은 반도체 장치에 관한 것으로서, 보다 상세하게는 대전류 및 고속 스위칭 특성을 갖는 수직 구조 바이폴라 트랜지스터 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a vertical structure bipolar transistor having high current and high speed switching characteristics, and a manufacturing method thereof.
최근 바이폴라 파워 스위칭 트랜지스터가 고내압, 대전류 용량이 요구되는 CRT 장비, 예를 들어 대형 텔레비젼과 컬러 모니터 등에 적용되고 있다.Recently, bipolar power switching transistors have been applied to CRT equipment requiring high breakdown voltage and large current capacity, for example, large televisions and color monitors.
이 경우 보통 유도성 부하회로에 적용이 되는데, 스위치 오프시 에미터의 가운데 부분에 국부적으로 전류가 집중되어 소자가 파괴되는 이차 항복현상에 의해 역방향 안전동작 영역이 제한을 받게 된다.In this case, it is usually applied to inductive load circuit. In case of switch-off, the reverse safety operation area is limited by the secondary breakdown phenomenon where the current is concentrated in the center of the emitter and the device is destroyed.
이를 제1도내지 제3도에 도시한 종래 바이폴라 트랜지스터의 구조 단면도를 참조하여 설명하면 다음과 같다.This will be described with reference to the cross-sectional structure of the conventional bipolar transistor shown in FIGS. 1 to 3 as follows.
종래에는 베이스 확산 영역(20)상에 선택적으로 에미터 소스를 확산 시켜 에미터(30)를 형성하였으며, 또한 제2도에 도시한 바와 같이 에미터(30)의 중앙 부분에 인액티브 영역(60)(60a)을 형성하여 스위치 오프시 에미터(30) 중앙 부분에 전류가 밀집되는 현상을 개선하거나, 또는 제3도에 도시한 바와 같이 베이스(20)의 하부 콜렉터(기판:10)와의 접합 부위(70)의 농도를 낮게 하여 스위칭 스피드를 개선하고자 하였다.In the related art, the emitter source is selectively diffused on the base diffusion region 20 to form the emitter 30, and as shown in FIG. 2, the inactive region 60 is formed at the center of the emitter 30. As shown in FIG. (60a) to improve the phenomenon that the current is concentrated in the central portion of the emitter 30 when the switch off, or as shown in Figure 3, the junction with the lower collector (substrate: 10) of the base 20 The concentration of the region 70 was lowered to improve the switching speed.
그러나 이들 바이폴라 트랜지스터는 베이스 형성후 마스킹을 통해 선택된 부분에 에미터를 확산시켜 형성한 것으로서, 소자가 '온'동작시 에미터 엣지로의 전류 밀집 현상과 측면 주입으로 인한 에미터 주입 효율 감소 및 전류 능력이 부족하게 되는 문제점을 갖고 있다.However, these bipolar transistors are formed by diffusing the emitter to the selected part through masking after base formation, which reduces the current injection efficiency and the emitter injection efficiency due to side current injection to the emitter edge when the device is 'on'. There is a problem of lack of ability.
또한 스위칭 측면에서도 '오프'동작시 콜렉터 영역에서 베이스로 넘어온 캐리어가 베이스 단자로 빠져나갈 때 저항이 커서 스위칭 스피드가 떨어지게 되는 단점이 있다.In addition, in terms of switching, when the carrier moves from the collector region to the base to the base terminal during the 'off' operation, the switching speed decreases due to a large resistance.
본 발명은 이러한 종래 기술의 문제점을 해결하고자 한 것으로, 그 목적은 고출력, 고내압, 고속 스위칭 특성을 갖으며 넓은 역방향 안전동작영역을 갖는 수직 구조 바이폴라 트랜지스터를 제공하는데 있다.The present invention has been made to solve the problems of the prior art, and an object thereof is to provide a vertical bipolar transistor having high output, high breakdown voltage, and high speed switching characteristics and having a wide reverse safety operation region.
또한 본 발명의 다른 목적은 상기 수직 구조 바이폴라 트랜지스터의 바람직한 제조 방법을 제공하는데 있다.It is another object of the present invention to provide a preferred method of manufacturing the vertical bipolar transistor.
또한 본 발명의 목적을 달성하기 위한 대전류 및 고속 스위칭 특성을 갖는 수직 구조 바이폴라 트랜지스터는, 베이스를 형성한 후 전체에 에미터를 형성한 다음 베이스 전극을 만들 부분을 식각하여 제거함으로써, 에미터 측면 주입을 방지하여 에미터 주입 효율 및 전류 능력을 향상시키고, 스위칭 측면에서도 베이스 전극과 콜렉터간의 저항을 줄임으로써 스위칭 스피드를 개선한 데에 그 특징이 있는 것이다.In addition, the vertical structure bipolar transistor having high current and high speed switching characteristics to achieve the object of the present invention, by forming an emitter in the whole after forming the base, and then by removing the portion to form the base electrode, emitter side injection This feature is characterized by improved emitter injection efficiency and current capability, and improved switching speed by reducing resistance between the base electrode and the collector in terms of switching.
즉, 대전류 및 고속 스위칭 특성을 갖는 수직 구조 바이폴라 트랜지스터는,That is, the vertical bipolar transistor having high current and high speed switching characteristics,
콜렉터로 사용되는 제1전도형의 반도체기판;A first conductive semiconductor substrate used as a collector;
상기 기판상에 침적되어 있고, 상부가 요철(凹凸)을 이루는 제2전도형의 베이스 확산 영역:A second conductivity type base diffusion region deposited on the substrate and having an uneven top portion;
상기 베이스 확산 영역의 철(凸)부에 형성된 제1전도형의 불순물이 주입된 에미터 영역;An emitter region into which an impurity of a first conductivity type formed in the iron portion of the base diffusion region is implanted;
상기 베이스 확산 영역의 상부에 침적된 절연막;An insulating film deposited on the base diffusion region;
상기 절연막을 통해 하부의 에미터 영역 및 베이스 영역과 각각 연결된 제1 및 제2전극을 포함하여 이루어진다.And first and second electrodes connected to the emitter region and the base region, respectively, through the insulating layer.
또한 상기 대전류 및 고속 스위칭 특성을 갖는 수직 구조 바이폴라 트랜지스터의 제조 방법은,In addition, the manufacturing method of the vertical structure bipolar transistor having the high current and high speed switching characteristics,
제1전도형의 반도체 기판상에 제2전도형의 베이스 영역을 확산시키는 단계;Diffusing a second conductive base region on the first conductive semiconductor substrate;
상기 베이스 확산 영역의 상부 전면에 에미터 영역을 형성을 위한 제1전도형의 불순물 이온 주입을 실시하는 단계;Performing impurity ion implantation of a first conductivity type to form an emitter region on an upper front surface of the base diffusion region;
상기 베이스 확산 영역의 상부를 선택적으로 식각하여 에미터 영역을 형성하는 단계;Selectively etching an upper portion of the base diffusion region to form an emitter region;
상기 결과물의 상부에 절연막을 침적하는 단계;Depositing an insulating film on top of the resultant product;
상기 절연막에 하부의 에미터 영역 및 베이스 영역에 연결되는 콘택홀을 형성하는 단계; 및Forming a contact hole in the insulating layer, the contact hole being connected to a lower emitter region and a base region; And
상기 결과물의 상부에 금속층을 형성/식각하여 하부의 에미터 영역과 베이스 영역에 연결되는 제1 및 제2전극을 형성하는 단계를 포함하여 이루어진다.Forming / etching a metal layer on top of the resultant to form first and second electrodes connected to the emitter region and the base region of the lower portion.
이하, 본 발명을 첨부 도면을 참조하여 상세히 설명하고자 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제4도 내지 제6도는 본 발명의 바이폴라 트랜지스터에서 전류 능력 향상과 스위칭 스피드의 개선을 목적으로 기존의 베이스-에미터 구조를 개량하여 도시한 구조 단면도이다. 그리고 제7도는 제4도에 도시된 바이폴라 트랜지스터의 제조 공정도이다.4 to 6 are structural cross-sectional views of an existing base-emitter structure for the purpose of improving current capability and switching speed in the bipolar transistor of the present invention. 7 is a manufacturing process diagram of the bipolar transistor shown in FIG.
제7a,b도에서와 같이, N형 실리콘 기판(10)상에 P형 베이스 영역(20)을 확산하여 형성한 후, 이의 상부 전면에 걸쳐 인 이온을 주입하여 베이스 확산 영역(20)의 표면 근방에 불순물 영역을 형성한다.As shown in FIGS. 7A and 7B, the P-type base region 20 is diffused and formed on the N-type silicon substrate 10, and then phosphorus ions are implanted over the upper surface of the base diffusion region 20. Impurity regions are formed in the vicinity.
다음 제7c도에 도시된 바와 같이, 상기 베이스 확산 영역(20)상부를 형성하고자 하는 에미터 영역을 제외한 상태로 습식 식각하여 에미터 영역(30)(30a)을 형성한다. 이때에 식각은 에미터 영역(30)(30a)의 깊이보다 더 깊게 실시한다.Next, as shown in FIG. 7C, the emitter regions 30 and 30a are wet-etched with the exception of the emitter region to form the upper portion of the base diffusion region 20. At this time, the etching is performed deeper than the depth of the emitter regions 30 and 30a.
다음 제7d에 도시된 바와 같이, 상기 결과물 상에 절연막(40), 바람직하게는 산화막을 형성한 후, 제7e도와 같이 포토레지스트를 식각마스크로 사용하여 하부의 에미터 영역(30) 및 베이스 영역(20)을 연결하는 콘택홀을 상기 절연막(40)상에 형성하고, 그 위에 제7f도와 같이 금속을 적층/식각하여 각각 에미터 전극(50)(50a) 및 베이스 전극(51)을 형성한다. 그리고, 실리콘 기판(10) 하부에 콜렉터 전극(52)을 형성하여 트랜지스터를 제조한다.Next, as shown in 7d, after forming an insulating film 40, preferably an oxide film on the resultant, the lower emitter region 30 and the base region using a photoresist as an etch mask as shown in FIG. 7e. Contact holes for connecting the 20 are formed on the insulating film 40, and metals are stacked / etched on the insulating film 40 to form emitter electrodes 50, 50a and base electrodes 51, respectively. . The collector electrode 52 is formed under the silicon substrate 10 to manufacture a transistor.
이 때에 제5도에 도시된 바와 같이, 에미터 영역(30)의 하부 중앙 부분에 인액티브 영역(60)(60a)을 형성하여 스위치 오프시 에미터 가운데 부위로 전류가 밀집되는 현상을 방지하면서 전류를 분산시켜 주도록 하면 역방향 안전동작 영역을 더 넓어진다.At this time, as shown in FIG. 5, the inactive regions 60 and 60a are formed in the lower center portion of the emitter region 30 to prevent the current from being concentrated in the center of the emitter when the switch is off. Distributing the current widens the reverse safe operating area.
또한 제6도에 도시한 바와 같이, 베이스 영역(20)아래 부분에 저농도의 베이스 접합 부위(70)를 형성하여 콜렉터(10)로 넘어가는 캐리어의 양을 줄여줌으로써 스위칭 스피드를 증가시킬 수 있다.In addition, as shown in FIG. 6, the switching speed may be increased by forming a low concentration base junction portion 70 below the base region 20 to reduce the amount of carriers passing to the collector 10.
이상에서 상세히 설명한 바와 같이, 본 발명은 에미터에서 베이스로 캐리어의 주입시 측면으로의 주입을 방지하여 에미터 주입 효율이 커지므로 전류 특성이 향상되며, 에미터 엣지로의 전류밀집 현상을 방지할 수 있다. 또한, 스위치'온'시 콜렉터 저농도 영역에 축적된 캐리어가 '오프'시 베이스 전극으로 추출될 때 캐리어의 흐르는 경로의 저항이 줄어드는 효과가 있어 스위칭 속도가 개선되는 것이다.As described in detail above, the present invention prevents the injection of the carrier from the emitter to the base, thereby increasing the emitter injection efficiency, thereby improving current characteristics, and preventing current condensation at the emitter edge. Can be. In addition, when the carrier accumulated in the collector low concentration region at the switch 'on' is extracted to the base electrode when the 'off', the resistance of the flow path of the carrier is reduced, thereby improving the switching speed.
Claims (5)
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| US7365373B2 (en) | 1998-06-05 | 2008-04-29 | The Board Of Trustees Of The Leland Stanford Junior University | Thyristor-type memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7365373B2 (en) | 1998-06-05 | 2008-04-29 | The Board Of Trustees Of The Leland Stanford Junior University | Thyristor-type memory device |
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