KR100269631B1 - Insulated gate bipolar transistor and manufacturing method thereof - Google Patents

Abstract

PURPOSE: An insulated gate bipolar transistor of a semiconductor device and its manufacturing method are provided to reduce the area of the device than the prior SA-LIGBT and have the improved switching operation characteristic. CONSTITUTION: First and second conductivity type semiconductor layers(22,23) are successively formed. A first conductivity type sinker layer(27) is formed in the first direction by being doped in high density. First and second conductivity type cathode-use impurity diffusion areas(28,26) are formed respectively in low and high density respectively in the second direction crossing the first direction to have a certain width, and in the first direction to have a thin thickness over the upper side of the first conductivity type impurity diffusion area. A gate insulation layer is placed in the first direction to cover the parts of the first and second cathode-use impurity diffusion areas. The gate(29) doped with the first conductivity type is formed on the gate insulation layer in the first direction. First wiring is formed in the first direction to be apart from the gate. Being apart from the first cathode-use conductivity type impurity diffusion area and in junction with the upper and lower part of the second conductivity type semiconductor layer in turn in the first direction, first and second conductivity type anode-use impurity diffusion areas(24,25) are formed with high density. A second wiring is formed thereon in the first direction.

Description

Insulated gate bipolar transistor in semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor of a semiconductor device and a method for manufacturing the same. In particular, the active area of a cathode is formed by a plurality of p + / n + captions, which are alternately arranged, thereby reducing the device area and improving switching characteristics compared with the conventional structure. The present invention relates to a shorted anode lateral insulated-gate bipolar transistor (SA-LIGBT) and a method of manufacturing the same.

In general, IGBT has the disadvantage of slow turn-off speed. In order to improve this, an anode structure is formed as a shorted-anode, which is called SA-LIGBT. In order to make up for the disadvantages of such a structure, a long anode structure is required. That is, the increased pitch size is required, which increases the volume occupied by the device area, which is not beneficial to the integration of the device. The p + diffusion region and the n + diffusion region of the anode are disposed parallel to the electron current direction, thereby turning off the device. It causes parasitic hole injection.

Lateral IGBTs have been proposed to implement smart integrated circuits in a mixed form with other integrated circuits. Lateral IGBTs have the same MOS-type control scheme compared to lateral DMOS transistors, but operate in silicon controlled rectifier (SCR) mode, resulting in improved current drive capability. In this case, SCR refers to silicon-controlled rectifier, which is formed by alternately joining p-type and n-type capacities by using a silicon single crystal to form an electrode at both ends, and rectifying characteristics are obtained by applying a DC current to the gate. The magnitude of the voltage at which the conduction state starts depends on the magnitude of the current, and once the current flows, the conduction state continues until the anode voltage becomes zero. Therefore, the output voltage as an average value can be adjusted by changing the gate current. have. This is widely used in various aspects, such as speed control of a dimmer and an electric motor.

However, lateral IGBTs, unlike lateral DMOS, require two time carriers to recombine with each other when the gate virus is turned off and turned off from normal operation. As a result, the switching operation time is considerably longer than that of the DMOS and the DMOS, which are mostly composed of electronic current components.

To overcome this problem, SA-LIGBT has been proposed to greatly improve switching operation characteristics at the expense of some current driving capability. As shown in FIG. 1, the structure is formed by side-by-side diffusion of a p + region and an n + region to an anode region.

1 is a perspective view illustrating a bipolar transistor structure of a semiconductor device manufactured according to the prior art.

First, the p-type epitaxial layer 2 doped with boron ions to a thickness of 35-40 μm is formed on the p-type silicon substrate 1 doped with boron ions. The epitaxial layer has a resistance of 60-90 ohm-cm. The n-type epitaxial layer 3 doped with phosphorus (P) ions is formed on the p-type epitaxial layer 2 to a thickness of 4-8 μm.

Then, a p + sinker layer 7 having a high concentration of boron ions diffused into p + impurity ions is formed. The p-type polysilicon layer 9 doped with boron ions is formed on the n-type epitaxial layer 3 including the p + sinker layer 7 by low pressure chemical vapor deposition (LPCVD). Then, a mask layer (not shown) which opens only the upper right side of the p + type sinker layer 7 is formed on the polysilicon layer 9, and then n + type ion implantation using the same as the first mask is performed to form the p + sinker layer 7. After forming the shallow n + type impurity buried layer 6 on the upper surface of the predetermined portion, the first mask is removed.

Next, a second mask (not shown) having a predetermined length over a part of the n + type impurity buried layer 6 and a part of the n type epitaxial layer 3 is formed to define a gate, and then etching is performed using the same. A portion of the polysilicon layer 9 is removed to define the gate 9 to remove the second mask. The gate 9 defined in this way is formed in parallel with the n + type impurity buried layer 6 and is doped with p type as described above.

In the conventional double diffusion method, the phosphorus (P) ion of the n + impurity buried layer 6 and the p-type boron ion doped in the gate 9 are near the upper surface of the n-type epitaxial layer 3. N + region (6) and p region (8) are formed by the extraction at. In this case, the n + region 6 becomes a cathode 6 and the p region 8 becomes a p-type base 8. At this time, the p base 8 is formed by diffusion of impurity ions from the gate 9 doped with p-type impurity (self-aligned to gate), and the n + region 6 which becomes the cathode 6. Is formed on the surface of the n-type epitaxial layer 3 so that the p base 8 is connected to the p + sinker layer 7 and is positioned below the gate 9 across the bottom and sides thereof.

The anode p + region 4, which is in parallel with the gate 9, is shallower on the upper surface of the n-type epitaxial layer 3 at a predetermined distance from the side of the gate 9 so as to secure a drift region. After forming, the n + region 5 for anode is formed in the same manner next to the 4.

And forming an insulating layer (not shown) on the entire surface of the n-type epitaxial layer 3 including the formed elements, and then removing a portion of the insulating layer to cover the surface area across the n + region 6 and the p + sinker layer 7. And a portion of the anode p + region 4 and the anode n + region 5 are opened, and aluminum is then deposited to form the cathode wiring 11 and the anode wiring 10, respectively. Each of the wirings 11 and 10 formed at this time is formed in parallel with the gate 9.

In the shorted anode-lateral insulated gate bipolar transistor (SA-LIGBT) formed in FIG. The n + region 5 for the anode serves as a path through which electrons escape during the turn-off operation. Since there is a MOS electronic current component in the total current, the current density in the turned-on state is higher than the lateral DMOS and lower than the lateral IGBT. Therefore, the SA-LIGBT is considerably improved than the lateral DMOS, but considerably improved than the lateral IGBT. The turn-off characteristic at this time is determined by adjusting the ratio of the diffusion widths of the respective regions 4 and 5.

As described above, the conventional SA-LIGBT has to form the p + region and the n + region adjacent to each other simultaneously in the horizontal direction in forming the anode cushion. However, each impurity diffusion region formed in parallel with the gate requires an increased area, that is, an increased pitch size, and thus has a problem in that it is opposed to high integration of the device.

In the conventional SA-LIGBT, since the anode p + region is formed closer to the drift region than the n + region, a part of the electron current components flowing under the anode p + region during the turn-off operation biases the p + / n junction forward. bias) to inject holes. Therefore, the holes injected as described above have a problem of delaying the turn-off operation until they remain in the bulk and recombine, thereby slowing down the operation speed.

Accordingly, an object of the present invention is to provide a plurality of p + structures in which a structure of p + and n + impurity diffusion regions of an anode is alternately arranged in a direction parallel to the gate, that is, in a three-dimensional direction, in a method of manufacturing an insulated-gate bipolar transistor (IGBT) of a semiconductor device. And forming an n + impurity diffusion region, thereby reducing the area occupied by the device compared to the conventional SA-LIGBT and providing a device manufacturing method having improved switching operation characteristics.

An insulated-gate bipolar transistor (IGBT) of a semiconductor device according to the present invention for achieving the above objects is a first conductivity type semiconductor substrate, a first conductivity type semiconductor layer formed on the first conductivity type substrate, and a first conductivity type epi A second conductivity type semiconductor layer formed on the taxi layer, a first conductivity type sinker layer doped at a high concentration in a lower portion of the upper surface of the upper surface of the second conductivity type semiconductor layer and formed in the first direction, and a first conductivity type A first conductivity type impurity diffusion region for cathodes connected to the upper right side of the sinker layer and formed at a low concentration in the first direction so as to have a predetermined width in a second direction perpendicular to the first direction, and an upper right side of the first conductivity type sinker layer; The second conductive type impurity for cathode having a shallow thickness over the lower part of the surface and connected to the upper part of the first conductive type impurity diffusion region for the cathode and formed at a high concentration in the first direction. A gate insulating film covering the diffusion region, a part of the second conductive impurity diffusion region for the cathode and the first conductive impurity diffusion region for the cathode, and extending in the first direction and having a first pattern in the same pattern as the gate insulating film; A first doped gate over the gate insulating film in a first direction, a portion of the surface of the second conductive dopant diffusion region for the cathode and a surface of the first conductive sinker layer, the first formed in the first direction so as to be isolated from the gate A plurality of high concentrations are formed on the wiring and the first conductive impurity diffusion region for the cathode in the second direction at predetermined intervals and are alternately bonded to the upper and lower surfaces of the second conductive semiconductor layer in the first direction, respectively. First conductive impurity diffusion region for anode and second conductive impurity diffusion region for anode, and a plurality of first conductive impurity diffusion region for anode and anode A second conductivity type formed of second wiring formed in a first direction over part of the surface of the impurity diffusion region.

In order to achieve the above objects, a method for manufacturing an insulated-gate bipolar transistor (IGBT) of a semiconductor device according to the present invention includes forming a first conductive semiconductor layer on a first conductive semiconductor substrate, and forming a first conductive semiconductor layer on the first conductive semiconductor layer. Forming a second conductive semiconductor layer, forming a high concentration of a first conductive sinker layer in a first direction on the surface and inside of the second conductive semiconductor layer, and forming a first conductive sinker layer Forming a gate insulating film on the second conductive semiconductor layer, including forming a first conductive conductive layer on the gate insulating film, an upper shallow surface of the first conductive sinker layer, and a second conductive semiconductor connected thereto Forming a high concentration of the second conductivity type impurity buried layer for cathode in the first direction on a portion of the shallow surface of the layer, and a part of the upper portion of the second conductivity type impurity buried layer for the cathode and the second conductivity type semiconductor Defining a gate by leaving a portion of the gate insulating film and the first conductive type conductive layer only on a part of the upper surface of the second conductive semiconductor layer at a predetermined distance from the gate in a second direction perpendicular to the first direction. Forming a plurality of first conductivity type diffusion region / second conductivity type diffusion region junctions for the high concentration anode in the first direction on the surface and the lower portion, forming an insulating layer on the front surface of the first conductivity type substrate, and insulating A portion of the layer is removed in the first direction so that the surface portion over the second conductive diffusion region and the first conductive sinker layer for the cathode and the first conductive diffusion region / second conductive diffusion region for the plurality of anodes The cathode wiring and the anode wiring are insulated from the gate and formed in a first direction, respectively.

1 is a perspective view of a bipolar transistor structure of a semiconductor device manufactured according to the prior art.

2 is a perspective view of a bipolar transistor structure of a semiconductor device manufactured according to the present invention.

According to the present invention, an anode p + / n + section formed in parallel with the gate is formed so as to alternately arrange each of the impurity diffusion regions in three dimensions.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Fig. 2 is a perspective view showing a bipolar transistor structure of a semiconductor device manufactured according to the present invention, where I represents the first direction and II represents the second direction and they are orthogonal to each other.

In FIG. 2, the present invention has the following structure.

First, the p-type epitaxial layer 22 doped with boron ions to a thickness of 35-40 μm is positioned on the p-type silicon substrate 21 that is doped with boron ions. The epitaxial layer has a resistance of 60-90 ohm-cm. An n-type epitaxial layer 23, which is a second conductivity type doped with phosphorus (P) ions at a thickness of 4-8 μm, is positioned on the p-type epitaxial layer 22.

A p + sinker layer 27 having a high concentration of boron ions diffused with p + impurity ions at a lower portion of the upper surface of the n-type epitaxial layer 23 is long in the first direction, and the right side thereof (27). The p-type impurity diffusion region 28 formed at a low concentration so as to have a predetermined width in the second direction under the surface of the n-type epitaxial layer 26 connected to the upper end is also elongated in the first direction. At this time, the p-type diffusion region becomes the p-type base 28 and the first direction and the second direction are orthogonal to each other.

An n + diffusion region 26 for cathodes having a shallow thickness over a portion of the upper right surface of the p + type sinker layer 27 and connected to a portion of the p type diffusion region 28 is long in the first direction.

A gate insulating film (not shown) covers a portion of the n + type diffusion region 26 and the p type diffusion region 28 for the cathode and is disposed on the lengths 26 and 28 in the first direction and is long on the gate insulating layer. Doped gate 29 is positioned in the first direction in the same pattern as the gate insulating film.

The first wiring 211 is formed long in the first direction to cover a portion of the surface of the cathode n + diffusion region 26 and the surface of the p + type sinker 27 and to be isolated from the gate 29.

The first p + diffusion region 24 for the anode is disposed at the lower surface of the upper surface of the n-type epitaxial layer 23 at a predetermined distance from the cathode p-type diffusion region 28 in the second direction. The first n + diffusion region 25 for the anode is formed on the lower surface of the upper surface of the n-type epitaxial layer 23 which is formed with a predetermined length in the direction and is adjacent to the first p + diffusion region 24 and is the same in the first direction. do. Each of the first p + diffusion regions 24 and the first n + diffusion regions 25 has a shape in which a plurality of first p + diffusion regions 24 are alternately arranged in a first direction.

In the n-type epitaxial layer 23, the interval between the p-type diffusion region 28 and the plurality of first p + diffusion regions 24 and the second n + diffusion region 25 in the second direction is a drift region. Becomes

The second wiring 210 is formed in a plurality of surfaces of the plurality of first p + diffusion regions 24 and the second n + diffusion regions 25 to extend in the first direction.

The first conductivity type and the second conductivity type may be interchanged with each other.

In the present invention having the structure as described above, in the turn-on operation, the MOS electron current starts to flow from the n + diffusion region 25 of the anode, which passes under the anode p + diffusion region 24. When the voltage drop reaches the value required for p + / n junction (24, 23) turn-on operation, the SCR (silicon controlled rectifier), which is the operation of the original IGBT element, is activated and the current density of this region is rapidly increased. In the turn-off operation, the remaining holes are recombined with the remaining electrons to disappear, and some electron currents that do not recombine exit through the n + diffusion region 25, but do not pass through the lower portion of the p + diffusion region 24. This prevents parasitic hole injection, which causes a turn-off delay.

Referring to FIG. 2, a method of fabricating a semiconductor device according to the present invention is a first conductive type doped with boron ions having a thickness of 35-40 μm on a first conductive p-type silicon substrate 21 doped with boron ions. The p-type epitaxial layer 22 is grown and formed. The epitaxial layer has a resistance of 60-90 ohm-cm. In addition, an n-type epitaxial layer 23 of a second conductivity type doped with phosphorus (P) ions having a thickness of 4-8 μm is formed on the first conductivity-type p-type epitaxial layer 22.

Next, a p + sinker layer 27 having a high concentration of boron ions diffused into a p + type impurity ion, which is a first conductivity type, is formed. And forming a gate insulating film (not shown) on the second conductivity type n-type epitaxial layer 23 including the first conductivity type p + sinker layer 27 and doping boron ions thereon. The silicon layer 29 is formed by vapor deposition by low pressure chemical vapor deposition (LPCVD). Then, a mask layer (not shown) which opens only the upper right side of the p + type sinker layer 27, which is the first conductivity type, is formed on the polysilicon layer 29, and then a high concentration of n + ion implantation, the second conductivity type, is used as the first mask. In order to form a shallow n + type impurity buried layer 26 on the upper surface of the predetermined portion of the p + sinker layer 27 in a high concentration, the first mask is removed.

Next, a second mask having a predetermined length over a portion of the n + type impurity buried layer 26 of the second conductivity type and a portion of the n type epitaxial layer 23 of the second conductivity type to define a gate (not shown) After forming the etching process using the etching process to remove a portion of the gate insulating film and polysilicon layer 29 to define the gate 29, and then remove the second mask. The gate 29 defined as described above is formed in parallel with the n + type impurity buried layer 26 of the second conductivity type in the first direction and is doped with the p type impurity of the first conductivity type as described above.

In addition, the p-type boron ions doped in the gate 29 and the phosphorus (P) ions of the second conductivity type n + impurity buried layer 26 are double n-type epitaxial, which is the second conductivity type. The high concentration n + region 26 and p region 28 are formed as the second conductivity type by being scattered near the upper surface of the shale layer 23. In this case, the n + region 26 becomes a cathode 26, and the p region 28 of the first conductivity type becomes the p-type base 28. At this time, the p base 28 is formed by diffusion of impurity ions from the gate 29 doped with p-type impurity (self-aligned to gate), and also of the second conductivity type that becomes the cathode 26. The n + region 26 is formed on the surface of the n-type epitaxial layer 23 at a high concentration in a shallow first direction, so that the p base 28 is connected to the p + sinker layer 27 and across the lower and side surfaces thereof. The gate 29 is positioned below.

Then, in order to form an anode portion while securing a drift region, the n-type epitaxial layer (in the first direction) is spaced a predetermined distance from the gate 29 or the p-type base 28 in the second direction. A third mask pattern (not shown) for exposing a portion of the part 23 for a long time is defined on the surfaces of all n-type epitaxial layers 23 including the part where the elements are formed. In this case, the third mask pattern alternately exposes a part of the surface of the n-type epitaxial layer 23 at predetermined intervals in the first direction. Using a third mask pattern as an ion implantation protection mask, ion implantation is performed at a high concentration with a first conductivity type impurity to alternately form a plurality of anode p + impurity embedding layers 24, and then remove the third mask pattern. do.

In addition, a fourth mask pattern (not shown) having the same shape in the third mask pattern and the second direction and exposing only the portions which are not ion implanted in the first direction is defined, and then the second conductivity type impurity ion implantation using the same is used. Is carried out at a high concentration to alternately form an anode n + type impurity buried layer 25.

Heat treatment is then performed to allow the ions in the impurity buried layers 24, 25 to sufficiently diffuse to form alternately arranged p + / n + cushions 24, 25 for the anode.

Then, an insulating layer (not shown) is formed on the entire surface of the n-type epitaxial layer 23 including the formed elements, and then a portion of the insulating layer is removed in the first direction so that the cathode n + region 26 and the p + sinker layer are formed. After opening part of the surface portion and the plurality of anode p + regions 24 and anode n + regions 25 over (27), aluminum is deposited to deposit the cathode wiring 211 and the anode wiring 210. It forms in a 1st direction, respectively. At this time, the wiring for the cathode is formed to be isolated from the gate (29).

Accordingly, the present invention relates to a bipolar transistor of a semiconductor device and a method for manufacturing the same. In particular, the active area of a cathode is formed by a plurality of p + / n + captions and arranged alternately, thereby reducing the device area and turning the structure. Off-speed operation provides the advantage of improved switching characteristics.

Claims (11)

A first conductivity type semiconductor substrate, A first conductivity type semiconductor layer formed on the first conductivity type substrate, A second conductivity type semiconductor layer formed on the first conductivity type epitaxial layer, A first conductive sinker layer (sinker) formed in a first direction by being doped at a high concentration on a lower portion of an upper surface of the upper surface of the second conductive semiconductor layer; A first conductivity type impurity diffusion region for cathodes connected to the upper right end of the first conductivity type sinker layer and formed at a low concentration in the first direction to have a predetermined width in a second direction perpendicular to the first direction; The second conductive impurity for cathode, which is connected to the lower surface of the upper right side of the first conductive sinker layer and has a shallow thickness over a part of the upper portion of the first conductive impurity diffusion region for cathode, is formed in a high concentration in the first direction. Diffusion area, A gate insulating film covering a portion of the second conductivity type impurity diffusion region for the cathode and the first conductivity type impurity diffusion region for the cathode and positioned in the first direction; A gate doped with a first conductivity type on the gate insulating film in the first direction in the same pattern as the gate insulating film; First wiring formed in the first direction to cover a portion of the surface of the second conductivity type impurity diffusion region for the cathode and the surface of the first conductivity type sinker layer, and to be isolated from the gate; A plurality of high concentrations are formed at a predetermined distance from the first conductive impurity diffusion region for the cathode in the second direction and alternately bonded to the upper and lower surfaces of the second conductive semiconductor layer in the first direction, respectively. First conductive impurity diffusion regions for anodes and second conductive impurity diffusion regions for anodes, An IGBT of a semiconductor device comprising a plurality of first conductive impurity diffusion regions for the anode and a second wiring formed in the first direction on a part of a surface of the second conductive impurity diffusion region for the anode. The insulated-gate bipolar transistor (IGBT) of a semiconductor device according to claim 1, wherein the resistance of the first conductivity type epitaxial layer is 60-90 ohm-cm. The IGBT of claim 1, wherein the first conductivity type diffusion region is a first conductivity type base. The method of claim 1, wherein the first conductive type impurity diffusion region for the cathode and the plurality of first impurity diffusion regions for the anode and the second impurity diffusion region in the second conductive epitaxial layer in the second direction IGBT of a semiconductor device characterized by being a drift region. The IGBT of the semiconductor device according to claim 1, wherein the first conductivity type is a p-type impurity ion and the second conductivity type is an n-type impurity ion. The IGBT of the semiconductor device according to claim 1, wherein the first conductive semiconductor layer and the second semiconductor layer each comprise an epitaxial layer. Forming a first conductive semiconductor layer on the first conductive semiconductor substrate; Forming a second conductive semiconductor layer on the first conductive semiconductor layer; Forming a first conductive sinker layer having a high concentration on the surface and the inside of the second conductive semiconductor layer in a first direction; Forming a gate insulating film on the second conductive semiconductor layer including the first conductive sinker layer; Forming a first conductivity type conductive layer on the gate insulating film; Forming a second concentration impurity buried layer for cathode in the first direction on the upper shallow surface of the first conductive sinker layer and a portion of the shallow surface of the second conductive semiconductor layer connected thereto; Defining a gate by remaining a portion of the gate insulating layer and the first conductive type conductive layer only on a portion of the second conductive impurity buried layer for the cathode and a portion of the second conductive semiconductor layer only; A plurality of first conductivity type diffusion regions / second conductivity type diffusion regions for a plurality of high-concentration anodes on the surface and the bottom of the second conductivity-type semiconductor layer at predetermined intervals from the gate in a second direction perpendicular to the first direction Forming a cushion in the first direction; Forming an insulating layer on an entire surface of the first conductivity type substrate; A portion of the insulating layer is removed in the first direction so that a surface portion over the second conductive diffusion region for the cathode and the first conductive sinker layer and a plurality of first conductive diffusion regions / seconds for the anode are provided. Forming a cathode wiring and an anode wiring insulated from the gate on a part of a conductive diffusion region section, respectively, in the first direction. The method of claim 7, wherein the first conductive conductive layer is formed by depositing a polysilicon layer doped with a first conductive impurity ion by low pressure chemical vapor deposition. The method according to claim 7, wherein the plurality of anode first conductive diffusion region / second conductive diffusion region section, Defining a first mask pattern exposing only a portion of the second conductivity type semiconductor layer in the first direction at a predetermined interval in a second direction perpendicular to the first direction from the gate; Alternately forming a plurality of first conductive impurity buried layers for the anode by performing ion implantation with a first conductive impurity at a high concentration using the first mask pattern as an ion implantation protection mask; Removing the first mask pattern; Defining a second mask pattern having the same shape in the first mask pattern and the second direction and exposing a portion which is not ion-implanted in the first direction; Alternately forming a second conductive impurity buried layer for the anode by performing a second conductive impurity ion implantation using the second mask pattern at a high concentration; IGBT manufacturing method of a semiconductor device characterized in that it comprises the step of performing a heat treatment on the first conductive semiconductor substrate. 10. The method of claim 9, wherein the first mask pattern alternately exposes a portion of the surface of the second conductivity-type semiconductor layer at predetermined intervals in the first direction. The method of claim 9, wherein the first conductive type and the second conductive type semiconductor layers are formed by epitaxial growth.