KR0179008B1 - Method of manufacturing metal contact - Google Patents
Method of manufacturing metal contact Download PDFInfo
- Publication number
- KR0179008B1 KR0179008B1 KR1019910000578A KR910000578A KR0179008B1 KR 0179008 B1 KR0179008 B1 KR 0179008B1 KR 1019910000578 A KR1019910000578 A KR 1019910000578A KR 910000578 A KR910000578 A KR 910000578A KR 0179008 B1 KR0179008 B1 KR 0179008B1
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- KR
- South Korea
- Prior art keywords
- oxide film
- metal
- metal contact
- film
- forming
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Abstract
본발명은 반도체 소자의 메탈 콘택 제조방법에 관한 것으로 실리콘기판위에 질화막을 형성하여 패터닝하고 열적 산화막을 성장시키는 공정과, 상기 열적 산화막과 질화막을 제거하고 필드 산화막을 성장시키는 공정과, 게이트를 형성하고 커패시터를 제조한 후 산화막과 메탈을 형성하는 공정을 차례로 실시하여서 이루어진다.The present invention relates to a method for fabricating a metal contact of a semiconductor device, comprising: forming a nitride film on a silicon substrate, patterning the same, growing a thermal oxide film, removing the thermal oxide film and the nitride film, and growing a field oxide film; After the capacitor is manufactured, a process of forming an oxide film and a metal is sequentially performed.
Description
제1도는 종래의 공정단면도.1 is a conventional cross-sectional view of the process.
제2도는 본발명의 공정단면도.2 is a process cross-sectional view of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 질화막1 substrate 2 nitride film
3 : 열적 산화막 4 : 필드 산화막3: thermal oxide film 4: field oxide film
5 : 게이트 6 : 노드 폴리실리콘5: gate 6: node polysilicon
7 : 유전막 8 : 플레이트 폴리실리콘7: dielectric film 8: plate polysilicon
9 : 산화막 10 : 메탈9 oxide film 10 metal
본발명은 반도체소자의 메탈 콘택 제조방법에 관한 것으로 특히 게이트의 위치를 낮추고 메탈 콘택 접속부위를 높이어 필름의 높이를 균일하게 평탄화시키면서 더블 메탈 공정및 메탈 스탭 커버리지를 향상시킬 수 있도록 한것이다.The present invention relates to a method for manufacturing a metal contact of a semiconductor device, in particular, to reduce the position of the gate and to increase the metal contact connection portion to improve the double metal process and metal step coverage while uniformly flattening the height of the film.
종래의 메탈 콘택 제조공정은 제1(a)도에 도시된 바와 같이 기판(11)에 필드산화막(12)을 형성하여 액티브 영역을 정의하고 (b)와 같이 게이트(13)를 형성한 후 (c)와 같이 노드 폴리실리콘(14), 유전막(15), 플레이트 폴리실리콘(16)을 형성하여 커패시터를 제조한다.In the conventional metal contact manufacturing process, as shown in FIG. 1 (a), the field oxide film 12 is formed on the substrate 11 to define an active region, and the gate 13 is formed as shown in (b) ( A capacitor is manufactured by forming the node polysilicon 14, the dielectric film 15, and the plate polysilicon 16 as in c).
그리고 산화막(17)을 형성하고 (d)와 같이 콘택을 오픈한 후 메탈(18)을 형성한다.After forming the oxide film 17 and opening the contact as shown in (d), the metal 18 is formed.
그러나, 상기와 같은 종래기술에 있어서는 반도체 셀 구조가 고집적화됨에 따라 메탈 콘택 접속시 에스펙트 비율이 높아짐으로써 메탈(18)이 끊어지기 쉬우며, 필드 산화막(12)과 액티브와의 단차 차이및 커패시터 용량에 따라 필름의 두께가 전체적으로 불균일하여 더블 메탈 공정에 문제점이 있을뿐만 아니라 콘택크기가 작아질수록 메탈(18)과이 숏 가능성이 커지는 문제점이 있다.However, in the conventional technology as described above, as the semiconductor cell structure is highly integrated, the aspect ratio of the metal contact connection is increased, so that the metal 18 is easily broken, and the step difference between the field oxide film 12 and the active and the capacitor capacity are increased. As a result, there is a problem in that the thickness of the film as a whole is not only a problem in the double metal process, but also as the contact size decreases, the probability of the metal 18 and the shot is increased.
본발명은 이와같은 종래의 문제점을 해결하기 위한 것으로 이하에서 본발명의 실시예를 첨부된 도면 제2도에 의하여 상세히 설명하면 다음과 같다.The present invention is to solve such a conventional problem described below in detail with reference to the accompanying drawings, the embodiment of the present invention 2 as follows.
먼저(a)와 같이 실리콘 기판(1)위에 질화막(2)을 형성하여 패터닝(Patterning)하고 (b)와 같이 열적 산화막(3)을 성장시킨다.First, the nitride film 2 is formed on the silicon substrate 1 as shown in (a) and patterned, and the thermal oxide film 3 is grown as shown in (b).
다음에 (c)와 같이 질화막(2)과 열적 산화막(3)을 제거하여 가판(1)만 남게 하고(d)와 같이 필드 산화막(4)을 형성하여 액티브 영역을 정의한다.Next, the nitride film 2 and the thermal oxide film 3 are removed as shown in (c) to leave only the substrate 1, and the field oxide film 4 is formed as shown in (d) to define an active region.
그리고 (e)와 같이 게이트(5)를 형성하고 (f)와 같이 노드 폴리실리콘(6), 유전막(7), 플레이트 폴리실리콘(8)을 형성하여 커패시터를 제조한 후 산화막(9)을 형성하여 콘택을 오픈한 상태에서 메탈(10)을 형성한다.The gate 5 is formed as shown in (e) and the node polysilicon 6, the dielectric film 7, and the plate polysilicon 8 are formed as shown in (f) to form a capacitor, and then an oxide film 9 is formed. By forming the metal 10 in the contact open state.
이상과 같은 본발명에 의하면 액티브영역의 메탈 콘택 부위가 높아지고 필드산화막(4)위의 게이트(5)높이가 낮아져 전체적으로 두께가 균일하여짐으로 더블 메탈 공정에 유리하며 메탈 콘택 부위가 높아짐으로 어스펙트 비율을 감소시켜 메탈(10)이 끊어지는 것을 방지할 수 있다. 또한, 종래의 구조보다 셀 면적을 줄일 수 있어 고집적화가 가능하며 메탈 콘택 부위와 게이트(5)를 완전히 분리시켜 숏 가능성을 배제시킬수 있는 장점을 갖는다.According to the present invention as described above, the metal contact portion of the active region is increased, the height of the gate 5 on the field oxide film 4 is lowered, and the overall thickness is uniform, which is advantageous for the double metal process and the metal contact portion is increased. By reducing the ratio, it is possible to prevent the metal 10 from breaking. In addition, since the cell area can be reduced compared to the conventional structure, high integration is possible, and the metal contact portion and the gate 5 can be completely separated to eliminate the possibility of a shot.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910000578A KR0179008B1 (en) | 1991-01-15 | 1991-01-15 | Method of manufacturing metal contact |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910000578A KR0179008B1 (en) | 1991-01-15 | 1991-01-15 | Method of manufacturing metal contact |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920015439A KR920015439A (en) | 1992-08-26 |
| KR0179008B1 true KR0179008B1 (en) | 1999-04-15 |
Family
ID=19309847
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910000578A KR0179008B1 (en) | 1991-01-15 | 1991-01-15 | Method of manufacturing metal contact |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0179008B1 (en) |
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1991
- 1991-01-15 KR KR1019910000578A patent/KR0179008B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR920015439A (en) | 1992-08-26 |
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