KR0163968B1 - 개선된 테스트 능력을 갖는 부분-주사 내장의 자체 테스트 회로 - Google Patents

개선된 테스트 능력을 갖는 부분-주사 내장의 자체 테스트 회로 Download PDF

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Publication number
KR0163968B1
KR0163968B1 KR1019940010613A KR19940010613A KR0163968B1 KR 0163968 B1 KR0163968 B1 KR 0163968B1 KR 1019940010613 A KR1019940010613 A KR 1019940010613A KR 19940010613 A KR19940010613 A KR 19940010613A KR 0163968 B1 KR0163968 B1 KR 0163968B1
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KR
South Korea
Prior art keywords
capability
flop
terminal
flip
self
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Expired - Fee Related
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KR1019940010613A
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English (en)
Korean (ko)
Inventor
젠 린 치
Original Assignee
로버트. 비. 레비
아메리칸 텔리폰 앤드 텔레그라프 캄파니
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G01R31/318586—Design for test with partial scan or non-scannable parts

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
KR1019940010613A 1993-05-17 1994-05-16 개선된 테스트 능력을 갖는 부분-주사 내장의 자체 테스트 회로 Expired - Fee Related KR0163968B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US063,191 1993-05-17
US08/063,191 US5450414A (en) 1993-05-17 1993-05-17 Partial-scan built-in self-testing circuit having improved testability

Publications (1)

Publication Number Publication Date
KR0163968B1 true KR0163968B1 (ko) 1999-03-20

Family

ID=22047570

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940010613A Expired - Fee Related KR0163968B1 (ko) 1993-05-17 1994-05-16 개선된 테스트 능력을 갖는 부분-주사 내장의 자체 테스트 회로

Country Status (6)

Country Link
US (1) US5450414A (OSRAM)
EP (1) EP0631235B1 (OSRAM)
JP (1) JP3048500B2 (OSRAM)
KR (1) KR0163968B1 (OSRAM)
CA (1) CA2119226C (OSRAM)
TW (1) TW245776B (OSRAM)

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US6256759B1 (en) 1998-06-15 2001-07-03 Agere Systems Inc. Hybrid algorithm for test point selection for scan-based BIST
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US6684358B1 (en) * 1999-11-23 2004-01-27 Janusz Rajski Decompressor/PRPG for applying pseudo-random and deterministic test patterns
US7493540B1 (en) 1999-11-23 2009-02-17 Jansuz Rajski Continuous application and decompression of test patterns to a circuit-under-test
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US8533547B2 (en) 1999-11-23 2013-09-10 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US6874109B1 (en) 1999-11-23 2005-03-29 Janusz Rajski Phase shifter with reduced linear dependency
US9134370B2 (en) 1999-11-23 2015-09-15 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US6557129B1 (en) * 1999-11-23 2003-04-29 Janusz Rajski Method and apparatus for selectively compacting test responses
US9664739B2 (en) 1999-11-23 2017-05-30 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US6745373B2 (en) * 2001-02-20 2004-06-01 International Business Machines Corporation Method for insertion of test points into integrated circuit logic designs
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US7437640B2 (en) * 2003-02-13 2008-10-14 Janusz Rajski Fault diagnosis of compressed test responses having one or more unknown states
US7302624B2 (en) * 2003-02-13 2007-11-27 Janusz Rajski Adaptive fault diagnosis of compressed test responses
JP2005135226A (ja) * 2003-10-31 2005-05-26 Matsushita Electric Ind Co Ltd 半導体集積回路のテスト回路挿入方法及び装置
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US7493434B1 (en) * 2005-05-25 2009-02-17 Dafca, Inc. Determining the value of internal signals in a malfunctioning integrated circuit
JP5136043B2 (ja) * 2007-02-22 2013-02-06 富士通セミコンダクター株式会社 論理回路および記録媒体
JP2008293088A (ja) 2007-05-22 2008-12-04 Nec Electronics Corp 半導体集積回路及びその設計方法
US7882454B2 (en) * 2008-04-28 2011-02-01 International Business Machines Corporation Apparatus and method for improved test controllability and observability of random resistant logic
US8164345B2 (en) * 2008-05-16 2012-04-24 Rutgers, The State University Of New Jersey Spectral and information theoretic method of test point, partial-scan, and full-scan flip-flop insertion to improve integrated circuit testability
JP2011112434A (ja) * 2009-11-25 2011-06-09 Renesas Electronics Corp 論理回路用テストポイント挿入方法、論理回路試験装置
US8819507B2 (en) * 2010-05-10 2014-08-26 Raytheon Company Field programmable gate arrays with built-in self test mechanisms
US8887109B1 (en) * 2013-05-17 2014-11-11 Synopsys, Inc. Sequential logic sensitization from structural description
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US10372855B2 (en) * 2014-02-28 2019-08-06 Mentor Graphics Corporation Scan cell selection for partial scan designs
US10527674B2 (en) 2017-08-21 2020-01-07 International Business Machines Corporation Circuit structures to resolve random testability
KR102450484B1 (ko) * 2020-12-18 2022-09-30 연세대학교 산학협력단 테스트 포인트 삽입을 통하여 향상된 검출율을 가지는 고장 검출 방법, 고장 검출 장치 및 가중치 인가 회로
KR102513278B1 (ko) * 2021-04-16 2023-03-23 연세대학교 산학협력단 스캔 체인의 자가 테스트를 위한 삽입 노드 결정 방법 및 장치
KR102680120B1 (ko) * 2021-11-29 2024-06-28 연세대학교 산학협력단 컨트롤 포인트의 구동 제어 방법 및 장치
US12130330B2 (en) * 2023-01-25 2024-10-29 Qualcomm Incorporated Integrated circuit including constant-0 flip flops reconfigured to provide observable and controllable test points

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Also Published As

Publication number Publication date
EP0631235B1 (en) 1998-08-12
CA2119226C (en) 1998-08-04
JP3048500B2 (ja) 2000-06-05
US5450414A (en) 1995-09-12
EP0631235A1 (en) 1994-12-28
JPH06331709A (ja) 1994-12-02
CA2119226A1 (en) 1994-11-18
TW245776B (OSRAM) 1995-04-21

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