CA2119226C - Partial-scan built-in self-testing circuit having improved testability - Google Patents

Partial-scan built-in self-testing circuit having improved testability

Info

Publication number
CA2119226C
CA2119226C CA002119226A CA2119226A CA2119226C CA 2119226 C CA2119226 C CA 2119226C CA 002119226 A CA002119226 A CA 002119226A CA 2119226 A CA2119226 A CA 2119226A CA 2119226 C CA2119226 C CA 2119226C
Authority
CA
Canada
Prior art keywords
self
flip
flop
node
controllability
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002119226A
Other languages
English (en)
French (fr)
Other versions
CA2119226A1 (en
Inventor
Chih-Jen Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of CA2119226A1 publication Critical patent/CA2119226A1/en
Application granted granted Critical
Publication of CA2119226C publication Critical patent/CA2119226C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G01R31/318586—Design for test with partial scan or non-scannable parts

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
CA002119226A 1993-05-17 1994-03-16 Partial-scan built-in self-testing circuit having improved testability Expired - Fee Related CA2119226C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US063,191 1993-05-17
US08/063,191 US5450414A (en) 1993-05-17 1993-05-17 Partial-scan built-in self-testing circuit having improved testability

Publications (2)

Publication Number Publication Date
CA2119226A1 CA2119226A1 (en) 1994-11-18
CA2119226C true CA2119226C (en) 1998-08-04

Family

ID=22047570

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002119226A Expired - Fee Related CA2119226C (en) 1993-05-17 1994-03-16 Partial-scan built-in self-testing circuit having improved testability

Country Status (6)

Country Link
US (1) US5450414A (OSRAM)
EP (1) EP0631235B1 (OSRAM)
JP (1) JP3048500B2 (OSRAM)
KR (1) KR0163968B1 (OSRAM)
CA (1) CA2119226C (OSRAM)
TW (1) TW245776B (OSRAM)

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5748497A (en) * 1994-10-31 1998-05-05 Texas Instruments Incorporated System and method for improving fault coverage of an electric circuit
US5831992A (en) * 1995-08-17 1998-11-03 Northern Telecom Limited Methods and apparatus for fault diagnosis in self-testable systems
CA2187466A1 (en) * 1995-10-19 1997-04-20 Kwang-Ting Cheng Method for inserting test points for full- and partial-scan built-in self-testing
US5668816A (en) * 1996-08-19 1997-09-16 International Business Machines Corporation Method and apparatus for injecting errors into an array built-in self-test
KR100206128B1 (ko) * 1996-10-21 1999-07-01 윤종용 선형 궤환 쉬프트레지스터, 다중 입력기호 레지스터 및 이들을 이용한 내장 자기 진단회로
US5691990A (en) * 1996-12-02 1997-11-25 International Business Machines Corporation Hybrid partial scan method
KR100499818B1 (ko) * 1997-01-06 2005-11-22 가부시끼가이샤 히다치 세이사꾸쇼 반도체집적회로검사점의해석방법,해석장치
EP0912904A2 (en) * 1997-04-24 1999-05-06 Koninklijke Philips Electronics N.V. Method for making a digital circuit testable via scan test
WO1998049576A1 (fr) * 1997-04-25 1998-11-05 Hitachi, Ltd. Circuit logique et son procede d'essai
US6256759B1 (en) 1998-06-15 2001-07-03 Agere Systems Inc. Hybrid algorithm for test point selection for scan-based BIST
US6363520B1 (en) 1998-06-16 2002-03-26 Logicvision, Inc. Method for testability analysis and test point insertion at the RT-level of a hardware development language (HDL) specification
SE512916C2 (sv) 1998-07-16 2000-06-05 Ericsson Telefon Ab L M Metod och anordning för feldetektering i digitalt system
US7036060B2 (en) 1998-09-22 2006-04-25 Hitachi, Ltd. Semiconductor integrated circuit and its analyzing method
US6370664B1 (en) 1998-10-29 2002-04-09 Agere Systems Guardian Corp. Method and apparatus for partitioning long scan chains in scan based BIST architecture
US6301688B1 (en) * 1998-11-24 2001-10-09 Agere Systems Optoelectronics Guardian Corp. Insertion of test points in RTL designs
US7281185B2 (en) * 1999-06-08 2007-10-09 Cadence Design (Israel) Ii Ltd. Method and apparatus for maximizing and managing test coverage
US7114111B2 (en) * 1999-06-08 2006-09-26 Cadence Design (Isreal) Ii Ltd. Method and apparatus for maximizing test coverage
US6578167B2 (en) 1999-08-06 2003-06-10 Hewlett-Packard Development Company, L.P. Digital Component test Apparatus, an apparatus for testing electronic assemblies and a method for remotely testing a peripheral device having an electronic assembly
US6463561B1 (en) 1999-09-29 2002-10-08 Agere Systems Guardian Corp. Almost full-scan BIST method and system having higher fault coverage and shorter test application time
US6694466B1 (en) * 1999-10-27 2004-02-17 Agere Systems Inc. Method and system for improving the test quality for scan-based BIST using a general test application scheme
EP1242885B1 (en) * 1999-11-23 2009-10-07 Mentor Graphics Corporation Continuous application and decompression of test patterns to a circuit-under-test
US6557129B1 (en) 1999-11-23 2003-04-29 Janusz Rajski Method and apparatus for selectively compacting test responses
US6874109B1 (en) 1999-11-23 2005-03-29 Janusz Rajski Phase shifter with reduced linear dependency
US8533547B2 (en) 1999-11-23 2013-09-10 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US6353842B1 (en) 1999-11-23 2002-03-05 Janusz Rajski Method for synthesizing linear finite state machines
US9664739B2 (en) 1999-11-23 2017-05-30 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US6684358B1 (en) 1999-11-23 2004-01-27 Janusz Rajski Decompressor/PRPG for applying pseudo-random and deterministic test patterns
US6327687B1 (en) 1999-11-23 2001-12-04 Janusz Rajski Test pattern compression for an integrated circuit test environment
US7493540B1 (en) 1999-11-23 2009-02-17 Jansuz Rajski Continuous application and decompression of test patterns to a circuit-under-test
US9134370B2 (en) 1999-11-23 2015-09-15 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US6745373B2 (en) * 2001-02-20 2004-06-01 International Business Machines Corporation Method for insertion of test points into integrated circuit logic designs
JP4174048B2 (ja) * 2002-09-19 2008-10-29 富士通株式会社 集積回路試験装置および試験方法
US7299391B2 (en) * 2002-10-29 2007-11-20 Faraday Technology Corp. Circuit for control and observation of a scan chain
EP1978446B1 (en) * 2003-02-13 2011-11-02 Mentor Graphics Corporation Compressing test responses using a compactor
US7437640B2 (en) * 2003-02-13 2008-10-14 Janusz Rajski Fault diagnosis of compressed test responses having one or more unknown states
US7509550B2 (en) * 2003-02-13 2009-03-24 Janusz Rajski Fault diagnosis of compressed test responses
US7302624B2 (en) * 2003-02-13 2007-11-27 Janusz Rajski Adaptive fault diagnosis of compressed test responses
JP2005135226A (ja) * 2003-10-31 2005-05-26 Matsushita Electric Ind Co Ltd 半導体集積回路のテスト回路挿入方法及び装置
SG126774A1 (en) * 2005-04-06 2006-11-29 Agilent Technologies Inc Method for determining a set of guard points and asystem for use thereof
US7493434B1 (en) * 2005-05-25 2009-02-17 Dafca, Inc. Determining the value of internal signals in a malfunctioning integrated circuit
JP5136043B2 (ja) * 2007-02-22 2013-02-06 富士通セミコンダクター株式会社 論理回路および記録媒体
JP2008293088A (ja) 2007-05-22 2008-12-04 Nec Electronics Corp 半導体集積回路及びその設計方法
US7882454B2 (en) * 2008-04-28 2011-02-01 International Business Machines Corporation Apparatus and method for improved test controllability and observability of random resistant logic
US8164345B2 (en) * 2008-05-16 2012-04-24 Rutgers, The State University Of New Jersey Spectral and information theoretic method of test point, partial-scan, and full-scan flip-flop insertion to improve integrated circuit testability
JP2011112434A (ja) * 2009-11-25 2011-06-09 Renesas Electronics Corp 論理回路用テストポイント挿入方法、論理回路試験装置
US8819507B2 (en) * 2010-05-10 2014-08-26 Raytheon Company Field programmable gate arrays with built-in self test mechanisms
US8887109B1 (en) * 2013-05-17 2014-11-11 Synopsys, Inc. Sequential logic sensitization from structural description
WO2015080637A1 (en) * 2013-11-28 2015-06-04 Telefonaktiebolaget L M Ericsson (Publ) Testing a feedback shift-register
US10372855B2 (en) * 2014-02-28 2019-08-06 Mentor Graphics Corporation Scan cell selection for partial scan designs
US10527674B2 (en) 2017-08-21 2020-01-07 International Business Machines Corporation Circuit structures to resolve random testability
KR102450484B1 (ko) * 2020-12-18 2022-09-30 연세대학교 산학협력단 테스트 포인트 삽입을 통하여 향상된 검출율을 가지는 고장 검출 방법, 고장 검출 장치 및 가중치 인가 회로
KR102513278B1 (ko) * 2021-04-16 2023-03-23 연세대학교 산학협력단 스캔 체인의 자가 테스트를 위한 삽입 노드 결정 방법 및 장치
KR102680120B1 (ko) * 2021-11-29 2024-06-28 연세대학교 산학협력단 컨트롤 포인트의 구동 제어 방법 및 장치
US12130330B2 (en) * 2023-01-25 2024-10-29 Qualcomm Incorporated Integrated circuit including constant-0 flip flops reconfigured to provide observable and controllable test points

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4225957A (en) * 1978-10-16 1980-09-30 International Business Machines Corporation Testing macros embedded in LSI chips
FR2451672A1 (fr) * 1979-03-15 1980-10-10 Nippon Electric Co Circuit logique integre pour l'execution de tests
US4534028A (en) * 1983-12-01 1985-08-06 Siemens Corporate Research & Support, Inc. Random testing using scan path technique
US5103557A (en) * 1988-05-16 1992-04-14 Leedy Glenn J Making and testing an integrated circuit using high density probe points
US5043986A (en) * 1989-05-18 1991-08-27 At&T Bell Laboratories Method and integrated circuit adapted for partial scan testability
US5132974A (en) * 1989-10-24 1992-07-21 Silc Technologies, Inc. Method and apparatus for designing integrated circuits for testability
JPH03201035A (ja) * 1989-10-24 1991-09-02 Matsushita Electric Ind Co Ltd 検査系列生成方法
US5291495A (en) * 1991-07-12 1994-03-01 Ncr Corporation Method for designing a scan path for a logic circuit and testing of the same

Also Published As

Publication number Publication date
JPH06331709A (ja) 1994-12-02
CA2119226A1 (en) 1994-11-18
TW245776B (OSRAM) 1995-04-21
KR0163968B1 (ko) 1999-03-20
EP0631235A1 (en) 1994-12-28
EP0631235B1 (en) 1998-08-12
JP3048500B2 (ja) 2000-06-05
US5450414A (en) 1995-09-12

Similar Documents

Publication Publication Date Title
CA2119226C (en) Partial-scan built-in self-testing circuit having improved testability
US7610527B2 (en) Test output compaction with improved blocking of unknown values
US7178078B2 (en) Testing apparatus and testing method for an integrated circuit, and integrated circuit
EP1722246B1 (en) Method and apparatus for selectively compacting test responses
Edirisooriya et al. Diagnosis of scan path failures
US10747926B2 (en) Low-power test compression for launch-on-capture transition fault testing
EP1595211B1 (en) Compressing test responses using a compactor
Iyengar et al. Synthesis of pseudo-random pattern testable designs
Pouya et al. Synthesis of zero-aliasing elementary-tree space compactors
US7266746B2 (en) Device and method for testing integrated circuit
Chen et al. A methodology to design efficient BIST test pattern generators
US5828828A (en) Method for inserting test points for full-and-partial-scan built-in self-testing
US6401227B1 (en) Timing fault diagnosis method and apparatus
AlShaibi et al. MFBIST: A BIST method for random pattern resistant circuits
US6728917B2 (en) Sequential test pattern generation using combinational techniques
US6708315B2 (en) Method of design for testability, method of design for integrated circuits and integrated circuits
US20040088626A1 (en) Method and apparatus for determining optimum initial value for test pattern generator
Solana et al. Pase-scan design: A new full-scan structure to reduce test application time
HK1097600B (en) Method and apparatus for selectively compacting test responses

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed