KR0158629B1 - Digital multistage volume control apparatus - Google Patents

Abstract

The present invention relates to a digital volume control device that can adjust volume in multiple stages. More specifically, although the volume is controlled only by 2 dB steps in the related art, a large volume (10 dB step) is achieved by using a simple logic gate in the digital volume control device. The present invention relates to a digital volume control device capable of adjusting a volume in a multi-level configuration of a device that can also be adjusted.

The present invention is one of the functions that can be diversified according to the user's needs. The multiplexer is configured with a simple logic gate so that the volume can be controlled with a large width (10dB steps) in addition to the general volume control (2dB steps).

This effect of the invention is a device that can be widely used in the volume control part for audio products or home appliances with built-in sound devices, especially televisions.

Description

Multi-level digital volume control

1 is a conventional digital volume control device

2 is a digital volume control device capable of adjusting the volume in multiple stages according to an embodiment of the present invention.

3 is a timing diagram for output control data of a 5-bit bidirectional shift register in FIG.

4 is a timing diagram for output control data of a 7-bit bidirectional shift register in FIG.

5 is a circuit diagram of a general bidirectional shift register.

* Explanation of symbols for main parts of the drawings

60: clock synchronization circuit 70: multiplexer circuit

100: bidirectional shift register section 110: attenuation circuit section

The present invention relates to a digital volume control device that can adjust the volume in multiple stages. More specifically, although the conventional volume is controlled only by a predetermined step, the digital volume control device can control the volume by using a simple logic gate in the digital volume control device. The present invention relates to a digital volume control device capable of adjusting a volume in a multi-level configuration.

In the prior art (Toshiba DataBook 1988, model number TC9153AP on page 282), a 7-bit, 6-bit bidirectional shift register, an oscillator, a 7-bit latch circuit, a 6-bit latch Although the circuit, analog switch, array resistor, etc. are configured to perform ideal volume control, the above-described conventional technology has a digital volume control device (single function) that is diversified by increasing user needs. Integrated circuits), but with the development of precise integrated circuit (IC) technology, circuits for diversifying functions can be constructed on a single integrated circuit.

Hereinafter, a conventional digital volume control device will be described with reference to the accompanying drawings.

1 is a conventional digital volume control device (single integrated circuit).

A clock synchronizing circuit 10 which receives an external up signal and a down signal through an OR gate and outputs a clock synchronizing signal by combining a clock pulse with an AND, and inputs an up signal and a down signal from the outside. When the clock synchronizing circuit 10 receives the clock synchronizing signal, the data is shifted from the left to the right when the up signal is input, and the data is moved from the right to the left when the down signal is input. A 5-bit bidirectional shift register 20 for outputting X2, X3, X4, X5 or less, denoted by X1-X5);

Receives the up signal and the down signal from the outside, receives the output control data X5 of the 5-bit bidirectional shift register 20 as the clock signal, and moves the data from the left to the right when the up signal is input, 7-bit bidirectional shift register 30 for outputting control data (represented by Y1, Y2, Y3, Y4, Y5, Y6, Y7 or less, Y1-Y7) to move the data from right to left upon input. Wow,

An attenuation circuit for outputting the analog signal inputted or deduced from the outside by using the output control data (X1-X5, Y1-Y7) of the 5-bit, 7-bit bidirectional shift registers 20 and 30; 40).

The operation of the conventional digital volume control device according to the above configuration is as follows. The 5-bit, 7-bit bidirectional shift registers 20 and 30 have five (2 × 1) multiplexers, five D flip-flops, seven (2 × 1) multiplexers, and seven D flip-flops. The D flip-flop is a combination of the multiplexer D flip-flops, the multiplexer, and the D flip-flop in series.

5 is a general circuit diagram of a 5-bit bidirectional shift register.

Referring to Fig. 5, the moving relationship of data will be described.

When the externally provided up signal (up = 1, down = 0) is input, each multiplexer selects input number 2. Each selected input is then synchronized with the clock to move data from left to right by the D flip-flop. When the down signal is input (UP = 0, DOWN = 1), each multiplexer selects input number 1 and moves the data in the opposite operation, that is, from right to left.

The 7-bit bidirectional shift register 30 also performs the same operation as described above. The difference between the 5-bit bidirectional shift register 20 and the 7-bit bidirectional shift register 30 is that the 5-bit bidirectional shift register 20 moves 5 bits of data left and right, and the 7-bit bidirectional shift register 30 is 7 bits. There is a difference in moving the data from side to side.

In addition, the operation | movement with respect to the whole structure of FIG. 1 is demonstrated.

In FIG. 1, only the case of the 5-bit bidirectional shift register 20 will be described first. When the preset signal is 00100, if a clock pulse synchronized with the up (up = 1, down = 0) signal is applied, the signal is left to right in the order of 00100-00010-0001 until the end of the up signal. When data is moved and down signals (up = 0, down = 1) are applied, data is moved in the right-to-left order, such as 00100-01000-10000, until the down signal ends.

The 7-bit bidirectional shift register 30 receives the output X5 of the 5-bit bidirectional shift register 20 as a clock pulse input, in the same manner as described above. If the initial value is 0010000, the up signal is applied as 0001000-0000100-0000010. The data moves in the order of left to right, and when the down signal is applied, the data moves in the order of right to left such as 0001000-0010000-0100000. The outputs X1-X5 and Y1-Y7 are input to the attenuation circuit 40, and the control data signals X1-X5 and Y1-Y7 input to the attenuation circuit are input to the data latch circuit and the latch circuit. The on / off control of the A switch is controlled by the data input to the on / off control, and the on / off control adjusts the volume of the analog signal input to the attenuation circuit 40 at the rear end by adding or subtracting the array resistance value.

However, the above-described conventional digital volume control device is unable to perform the function of diversification by the increasing user's desire.

For example, when the user attempts to increase or decrease the volume by a large width, the conventional digital volume control device is set to a constant volume width so that the volume control of a larger width than the set is not possible and does not meet the user's desire. There are disadvantages.

Therefore, an object of the present invention is to solve the above disadvantages, by providing a clock pulse directly to the bidirectional shift register for controlling a large volume level by using a simple logic gate can freely adjust the large volume It is to provide a digital volume control device.

The configuration of the present invention for achieving the above object,

A clock synchronizing circuit unit configured to receive an external up signal and a down signal, enable the up down signal as an enable signal for a clock signal, and enable the output signal while the up down signal is input from the outside;

Receives the up signal and the down signal, receives the clock signal, and moves the data from the left to the right when the up signal is input, and outputs the control data by moving the data from the right to the left when the down signal is input. A bidirectional shift register section,

A multiplexer circuit unit controlling the bidirectional shift register unit to output a control data capable of controlling the volume at a large width when an externally provided fast signal is input;

An attenuation circuit unit for adding or subtracting an analog signal through an analog signal input from an external bidirectional shift register using the control data inputted from the bidirectional shift register or under an control of the multiplexer circuit unit when an external mute signal is applied; Is made of.

With the above configuration, the most preferred embodiment which can be easily carried out by those skilled in the art to which the present invention pertains will be described in detail with reference to the accompanying drawings.

2 is a digital volume control device capable of adjusting the volume in multiple stages according to an embodiment of the present invention.

3 is a timing diagram for output control data of a 5-bit bidirectional shift register in FIG.

4 is a timing diagram for output control data of a 7-bit bidirectional shift register in FIG.

As shown in Figure 2, the configuration of the digital volume control device that can adjust the volume in a multi-step according to an embodiment of the present invention,

A clock synchronizing circuit unit 60 which receives an external up signal and a down signal, enables the up down signal as an enable signal for a clock signal, and is enabled while an external up down signal is input, and outputs the clock signal;

When the up signal and the down signal are input from the outside, the clock synchronizing circuit unit 60 receives the clock synchronizing signal, and when the up signal is input, the data is moved from left to right, and when the down signal is input, the data is right to left. A 5-bit bidirectional shift register 80 for outputting the control controllers X1-X5, and an up signal and a down signal from an external source, and output control data of the 5-bit bidirectional shift register 80 X5) is inputted as a clock signal, data is moved from left to right when the up signal is input, and data is moved from right to left when the down signal is input so that the control data (Y1-Y7) are output. A bidirectional shift register section 100 comprising a bit bidirectional shift register 90,

A multiplexer for disabling the clock input of the 5-bit bidirectional shift register and enabling the 7-bit bidirectional shift register when the up signal and the down signal are applied and then the fast signal is applied. The analog signal received from the circuit unit 70 and the externally input analog signal is input to the output control regulators X1-X5 and Y1-Y7 of the 5-bit, 7-bit bidirectional shift registers 80 and 90 as an input. It consists of attenuation circuit unit 110 to add or subtract from the output.

In more detail,

The clock synchronization circuit 60,

An OR gate 61 which receives an up signal (1) and receives a down signal (2) and outputs it (3);

The AND gate 62 receives the output of the OR gate 61 and receives and outputs a clock signal CK.

The multiplexer circuit unit 70,

An AND gate 72 which receives the output 3 of the AND gate 62 (1),

An inverter gate 71 that receives an external fast signal FAST;

An AND gate 73 which receives an output of the inverter gate 71 (2), receives an output control data X5 (1), and outputs the same;

An AND gate 74 that receives the output 3 of the AND gate 62, receives an external fast signal FAST, and outputs the output 3, and

The ore gate 75 receives the output 3 of the AND gate 73, receives the output 3 of the AND gate 74, and receives the output 3 of the AND gate 73.

The bidirectional shift register unit 100 has an external up signal input connected to an up input terminal U, an external down signal input connected to a down input terminal D, and an output 3 of the AND gate 72. Is a 5-bit bidirectional shift register 80 connected to the clock input terminal CK,

The external up signal input is connected to the up input terminal U, the external down signal input is connected to the down input terminal D, and the OR gate 75 and the clock input terminal CK of the multiplexer unit 70 are connected. Consisting of a 7-bit bidirectional shift register 90.

The attenuation circuit unit 110,

The outputs of the muting circuit (X1, X2, X3, X4, X5) are connected to the 2 decibel step (2dB STEP) stage,

The output of the muting circuit (Y1, Y2, Y3, Y4, Y5, Y6, Y7) is connected to the 10 decibel step (10dB STEP) stage,

A terminal for receiving an analog signal (ANALOG IN) and a terminal for outputting the analog signal (ANALOG OUT).

The operation of the digital volume control device incorporating the muting circuit according to the embodiment of the present invention by the above configuration is as follows.

The 5-bit 7-bit bidirectional shift registers 80 and 90 have five (2 × 1) multiplexers, five D flip-flops, seven (2 × 1) multiplexers, and seven D flip-flops. The flip-flops form a combination and consist of a serial arrangement of the multiplexer D flip-flop, multiplexer, and D flip-flop.

5 is a general circuit diagram of a 5-bit bidirectional shift register.

Referring to Fig. 5, the moving relationship of data will be described.

When the externally provided up signal (up = 1, down = 0) is input, each multiplexer selects input number 2. Each selected input is then synchronized with the clock to move data from left to right by the D flip-flop. When the down signal is input (UP = 0, DOWN = 1), each multiplexer selects input number 1 and moves the data in the opposite operation, that is, from right to left.

The 7-bit bidirectional shift register 90 also performs the same operation as described above. The difference between the 5-bit bidirectional shift register 80 and the 7-bit bidirectional shift register 90 is that the 5-bit bidirectional shift register 80 moves 5 bits of data left and right, and the 7-bit bidirectional shift register 90 is 7 bits. There is a difference in moving the data from side to side.

When the up signal (up = 1, down = 0) is input from the outside, each multiplexer selects the second input. Each selected input is then synchronized with the clock to move data from left to right by the D flip-flop. When the down signal is input (UP = 0, DOWN = 1), each multiplexer selects input number 1 and moves the data in the opposite operation, that is, from right to left.

Considering only the case of the first 5-bit bidirectional shift register 90 in FIG. 2, when the preset signal is 00100, if a clock pulse synchronized with the up (up = 1, down = 0) signal is applied, 00100-00010 If the data is moved in the order of left to right as -00001 and the down signal (up = 0, down = 1) is applied, the data is moved in the order of right to left as 00100-01000-10000 .

The 7-bit bidirectional shift register 90 receives the control data of the output X5 of the 5-bit bidirectional register 100 as the input of the clock pulse when the mute signal is not applied, and in the same manner as described above. When the up signal is applied, the data moves in the order of left to right as in 0001000-0000100-0000010, and when the down signal is applied, the data moves in the order of right to left as in 0001000-0010000-0100000. This output (X1-X5) is input to the 2dB step of the attenuation circuit section 110, (Y1-Y7) is input to the 10dB step of the attenuation circuit section 110.

Next, the operation of the multiplexer circuit unit 70 will be described.

When the fast signal FAST is not applied, the output of the inverter becomes 1 to enable the AND gate 72 to supply a clock pulse to the 5-bit bidirectional shift register, and output control data of the 5-bit bidirectional shift register. X5) is enabled and supplied to the clock input of the 7-bit bidirectional shift register to perform the same function as the conventional digital volume controller.

When the fast signal is input after the up signal or the down signal is applied, a signal of 1 is input to the AND gate 74 to enable the AND gate 74, and the output 11 of the inverter gate is Contrary to what is said, it becomes 0 to disable the AND gates 72 and 73. In other words, when the fast signal is not applied, the general operation is performed as described above, and when the fast signal is applied, the operation of the 5-bit bidirectional shift register 80 is stopped and 7 bit is stopped. The bidirectional shift register 90 is operated to allow for large volume control. The output control data Y1-Y7 of the 7-bit bidirectional shift register 90 are input to the 10 dB step of the attenuation circuit unit 110. As such, the control data inputted to the attenuation circuit unit 110 controls the analog signal by 2 dB per step from 0 dB to -66 dB through a latch circuit, an analog switch, an array resistor, etc. in the attenuation circuit unit 110, or If a fast signal is applied from the outside, it is possible to control 10dB per step.

As described above, in the embodiment of the present invention, in the prior art, by adjusting the volume only in 2dB steps, if the user wants a faster volume control, the volume can be changed in 10dB steps, and muting is not necessary without implementing a muting device separately. It is possible to provide a digital volume control device capable of adjusting the volume in multiple stages with an improved effect than the prior art that can fully exhibit the effect of. The effect of this invention can be widely used in the volume control part for an audio product or a product incorporating an audio device, especially a television.

Claims (4)

A clock synchronizing circuit unit configured to receive an external up signal and a down signal and to enable the up-down signal as an enable signal for a clock signal and to enable the output signal while the up-down signal is input from the outside; Bi-directional shift for receiving the clock signal and the down signal, and the data is moved from left to right when the clock signal is input, and when the down signal is input, the data is moved from right to left. A multiplexer circuit for controlling the bidirectional shift register and outputting control data capable of controlling a large volume when a fast signal is input from an external device; and a bidirectional shift register unit for receiving an analog signal input from an external device. Using the control data input from W analogue acceleration signal or an external mute signal is applied when the multiplexer under the control of the subtraction circuit to an analog signal capable of volume control in multiple stages, characterized in that comprising a damping circuit for outputting a digital volume control of the device. The clock synchronizing circuit of claim 1, wherein the clock synchronizing circuit unit receives an up signal, receives a down signal, and outputs a down gate 61 and an output of the down gate 61, and receives a clock signal. Digital volume control device capable of volume control in a multi-step, characterized in that the end gate 62 to output. The multiplexer circuit of claim 1, wherein the multiplexer circuit unit is configured to receive an output of the AND gate 72, which receives the output of the AND gate 62, an inverter gate 71 that receives an external pass signal, and an output of the inverter gate 71. An AND gate 73 for receiving and outputting the output control data X5, an AND gate 74 for receiving an output of the AND gate 62, and receiving and outputting an external fast signal, and an AND gate. A multi-level digital volume control device comprising: an ora gate 75 which receives an output of 73 and receives an output of an AND gate 74. The method of claim 1, wherein the bidirectional shift register unit receives an up signal provided from an external source to an up input terminal, receives an external down signal from a down input terminal, and outputs the AND gate 72 to a clock input terminal. Output control of the 5-bit bi-directional shift register 80, even if the input signal is provided to the external input to the up input terminal, and the down input terminal receives an external down signal from the external input, Data (X5) is a multi-level digital volume control device, characterized in that consisting of a 7-bit bidirectional shift register (80) input to the clock input terminal.