KR0145772B1 - ALIGNMENT-KEY ARRANGING METHOD OF HIGH INTEGRATED SEMICONDUCTOR DEVICEá - Google Patents

Abstract

The present invention relates to a method of arranging an alignment key for aligning a mask and a wafer in performing an exposure process during a process of manufacturing a semiconductor device having a plurality of divided memory cell arrays and peripheral circuits formed at the center of the chip. In this regard, the alignment key is disposed at the center of the chip corresponding to the same distance from the vertices of the chip.

Description

Alignment Key Arrangement of Highly Integrated Semiconductor Devices

1 is a view showing a conventional alignment key arrangement method.

2 is a view showing an alignment key arrangement method according to the present invention.

3 is a view showing alignment key arrangement states according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly to a method of arranging alignment keys in an exposure process.

The semiconductor device is composed of a plurality of insulating layers and conductive layers formed on a wafer, and their patterns are formed by performing exposure and etching processes in accordance with a mask of features. In order to form a layer having a desired pattern, only the layer to be etched in the exposure process should be exposed to the light source. Currently used photo-reticles are equipped with a plurality of chips per reticle and use a step and repeat type aligner. In general, the alignment key of the reticle is placed on a scribe line near the center of the reticle to ensure accurate alignment.

In FIG. 1A, the alignment key 2 is arranged on the scribe brine 3 at the center of one reticle 1, and the plurality of chips 4 are arranged. However, more precise alignment is required because semiconductor devices are increasingly integrated and circuit widths continue to decrease as memory capacity increases. In addition, as the area of the chip gradually increases, it becomes difficult to embed a plurality of chips in one reticle as shown in FIG. 1, so that only one chip is mounted on one reticle 1 as shown in FIG. Therefore, in the configuration as shown in FIG. 1B, the scribe brine 3 containing the alignment key 2 is located at the edge of the reticle 1.

However, it has already been known that the scribebrain on which the alignment keys are to be placed is located at the edge of the lattice, the alignment characteristics are worse than the center position (see US Pat. No. 4,620,785).

Accordingly, an object of the present invention is to provide an alignment key arrangement method having reliable alignment characteristics even with a large chip size.

Another object of the present invention is to provide an alignment key arrangement method having reliable alignment characteristics by mounting a plurality of chips on one reticle even if the chip size is large.

In order to achieve the object of the present invention, the present invention, in the process of manufacturing a semiconductor device having a plurality of divided memory cell array and a peripheral circuit formed in the center portion of the chip in the process of performing the exposure process to align the mask and wafer In order to arrange the alignment key, the alignment key is disposed in the center of the chip corresponding to the same distance from the vertices of the chip.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings related to the present invention, the same reference numerals are used for the same elements.

Referring to FIG. 2, the alignment key 2 is disposed at the center of the chip 4, and the alignment key 2 is spaced apart from the peripheral circuit by a predetermined distance, thereby recognizing the alignment due to the pattern of the peripheral circuit. Eliminate this inaccuracy. When distortion or rotation of the chip 4 is generated about the portion where the alignment key 2 is located, with the alignment key 2 positioned at the center of the chip 4, the chip The most severe misalignment in (4) is the four vertices (h, i, j, k) of the chip (4). Assuming that the width and length of the chip 4 are a and b, respectively, the distance between each vertex from the position of the alignment key 2 is ROOT ((a / 2) EXP2 + (B / 2) EXP2).

Here, when the alignment key 2 is located on either side of the scribe brine 3, it is assumed that the position is X = (a, y) (when the origin on the reticle is h), and it is distorted about this position. Or the worst part of the meeting,

(1) vertex h at y b / 2 and the distance from X = (a, y) to h is

SQRT (aEXP2 + yEXP2) [SQRT (aEXP2 + yEXP2) ROOT ((a / 2) EXP2 + (B / 2) EXP2)).

(2) Vertices h and k when y = b / 2, and the distance from X = (a, h) to h or k is SQRT (aEXP2 + (b / 2) EXP2) [SQRT (aEXP2 + (b / 2) EXP2) ROOT ((a / 2) EXP2 + (B / 2) EXP2))].

(3) For yb / 2, the vertex k, and the distance from X = (a, h) to k is SQRT (aEXP2 + (by) EXP2) [SQRT (aEXP2 + (by) EXP2) ROOT ((a / 2) EXP2 + (B / 2) EXP2))].

The above relations can be obtained even when the alignment key 2 is at another position in FIG. As such, regardless of where the alignment key is placed in the scribebrain, the alignment key is made farther than the position where the alignment is most severe and the position where the alignment key is placed, than the center of the alignment key. It is much more advantageous to place it closer to the center of the chip than to place it on a scribebrain, which reduces the number of rework cycles and the process time.

In arranging the alignment keys, when the cell array structure of the semiconductor memory element is formed in the center of the chip, it is difficult to arrange the alignment keys. However, as shown in FIG. In this case, it is possible to arrange the alignment keys in the above-described manner. Referring to FIG. 3, in FIG. 3A, the memory cell array 5 is divided into four centers of the chip 4, and the peripheral circuits 6 are formed in the remaining areas of the chip. 3b is a case where the memory cell array 5 is divided into left and right about the center of the chip 4, and the peripheral circuit 6 is formed in the remaining area of the chip, and FIG. 3c is the center of the chip 4 It is a case where the peripheral circuit 6 is divided up and down about a part, and the peripheral circuit 6 is arrange | positioned in the remaining area | region of a chip. Since the arrangement of the chip shown in FIG. 3 shows an arrangement method widely used in a recent semiconductor memory device, it can be understood that the alignment key arrangement method according to the present invention can be widely used. In addition, it is possible to further increase the accuracy of the alignment by arranging the keys necessary for alignment inspection instead of the alignment key.

Claims (2)

A method of arranging an alignment key for aligning a mask with a wafer in an exposure process during a process of manufacturing a semiconductor device having a plurality of divided memory cell arrays and peripheral circuits formed in a central portion of the chip, the method comprising: And aligning the alignment key at the center of the chip corresponding to the same distance from vertices. A method of arranging an alignment key for aligning a mask with a wafer in an exposure process during a process of manufacturing a semiconductor device having a plurality of divided memory cell arrays and peripheral circuits formed in a central portion of the chip, the method comprising: And aligning the alignment key at a position separated by a predetermined distance from a central portion of the chip corresponding to the same distance from vertices.