US6566041B2 - Photomask and pattern forming method used in a thermal flow process and semiconductor integrated circuit fabricated using the thermal flow process - Google Patents
Photomask and pattern forming method used in a thermal flow process and semiconductor integrated circuit fabricated using the thermal flow process Download PDFInfo
- Publication number
- US6566041B2 US6566041B2 US09/757,841 US75784101A US6566041B2 US 6566041 B2 US6566041 B2 US 6566041B2 US 75784101 A US75784101 A US 75784101A US 6566041 B2 US6566041 B2 US 6566041B2
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- Prior art keywords
- openings
- resist
- exposure
- photomask
- flow process
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Definitions
- the present invention relates to a photomask used in a thermal flow process, a method of forming patterns used in a thermal flow process, and a semiconductor integrated circuit in which a portion having fine planar shapes is treated by a prescribed process through openings in a resist.
- a resist is applied to the surface of the insulating film that is to undergo processing, and the resist is then exposed using a photomask in which a plurality of exposure openings are formed. The resist is then developed to form openings at the exposed portions, and this resist is used as a mask to etch the insulating film through the openings.
- This type of photolithography is used not only for the formation of through-holes described above but for various other purposes such as introducing impurities into a semiconductor substrate and patterning wiring lines.
- a photomask is formed in which the pattern that is to be exposed is enlarged in all directions, following which the exposure process is carried out with this photomask using reducing optics to expose a pattern of the desired dimensions on the resist.
- FIG. 1 A-FIG. 2C one example of the thermal flow process of the prior art is next described.
- a DRAM Dynamic Random Access Memory
- semiconductor integrated circuit 100 which is the object of processing.
- gate oxide film 102 is formed on the surface of semiconductor substrate 101 , and gate electrodes 103 and 104 of the transistor elements that will serve as memory cells are formed in a prescribed pattern on the surface of this gate oxide film 102 .
- Gate oxide film 102 is partitioned by element isolation regions 105 according to the positions of memory cells, and the space around gate electrodes 103 and 104 is filled with interlayer dielectric film 106 , which is a prescribed layer.
- contact hole 107 of a bit contact is formed from the surface of interlayer dielectric film 106 to the surface of gate oxide film 102 at a position between the pair of gate electrodes 103 and 104 , as shown in FIG. 2 C.
- Photomask 111 in which is formed exposure opening 110 that corresponds to this contact hole 107 , is therefore prepared as shown in FIG. 1 C.
- this photomask 111 is such that shield film 113 is formed on the underside of transparent base member 112 and exposure opening 110 is formed by partially removing this shield film 113 .
- This exposure opening 110 is formed at position that corresponds to contact hole 107 , and its dimensions in all directions are greater than the dimensions of contact hole 107 .
- Resist 115 is then applied to the surface of interlayer dielectric film 106 , which is a prescribed layer of semiconductor integrated circuit 100 , to form a prescribed film thickness as shown in FIG. 1B, and the above-described photomask 111 is arranged parallel to and confronting the surface of resist 115 at a prescribed distance from the surface of resist 115 .
- resist 115 is exposed to light by exposure device (not shown in the figure) through exposure opening 110 of photomask 111 , and as shown in FIG. 2A, this resist 115 is then developed to form opening 116 that corresponds to exposure opening 110 .
- a contact hole is formed in interlayer dielectric film 106 of semiconductor integrated circuit 100 through this opening 116 in resist 115 .
- resist 115 that has been patterned as described hereinabove is heated and softened in a thermal flow process to shrink opening 116 as shown in FIG. 2 B.
- an extremely small diameter contact hole 107 can be formed from the surface of interlayer dielectric film 106 to the surface of gate oxide film 102 by etching interlayer dielectric film 106 of semiconductor integrated circuit 100 through opening 116 in resist 115 .
- Exposure opening 110 of photomask 111 which is used in the exposure process in the above-described thermal flow process, is therefore formed at dimensions that approach the limit dimensions of the exposure process and in a shape that is an enlargement in all directions of opening 116 that has been shrunk by heating resist 115 .
- the shape of an exposure beam that passes through exposure opening 110 is deformed by such factors as diffraction.
- the shape of the exposure of opening 116 in resist 115 is therefore roughly oval in shape even though exposure opening 110 is square, and the shape of opening 116 following the thermal flow process becomes approximately circular.
- exposure opening 110 of photomask 111 is typically formed as a square in order to simplify design and fabrication.
- exposure opening 110 of photomask 111 is formed as a square having sides of length “a”.
- this resist 115 is heated to shrink opening 116 , whereby a process can be performed on interlayer dielectric film 106 at dimensions that are smaller than the exposure limit dimension.
- opening 116 deforms as it shrinks due to the surface tension of this resist 115 . It has been confirmed by the inventors of this invention that this deformation occurs in accordance with the positional relationships between the plurality of openings 116 . Specifically, when shrinking a plurality of openings 116 by heating resist 115 , the degree of shrinkage at each of openings 116 that are close to each other is smaller in the direction between openings 116 while the degree of shrinking is greater in the direction orthogonal to this direction.
- a plurality of contact holes 107 are arranged linearly in a direction that is inclined 45° from the directions of arrangement of the bit lines and word lines.
- Photomask 111 for forming such a plurality of contact holes 107 has a shape in which a plurality of square exposure openings 110 are arranged in a line in a 45° direction, as shown in FIG. 3 A.
- openings 116 of a desired shape in desired positions is problematic due to deformation according to the positional relationship between the plurality of openings 116 , as described in the foregoing explanation, and the proper realization of prescribed fine processing on semiconductor integrated circuit 100 is therefore also problematic.
- a photomask is used in a thermal flow process in which: a photomask is prepared in which a plurality of exposure openings are formed; a resist is applied to the surface of the layer of a semiconductor integrated circuit that is to undergo processing; the resist is patterned by an exposure process through the photomask to form a plurality of openings in the resist that correspond to each of the exposure openings; and the resist in which the patterning has been carried out is heated to cause each of the openings to shrink; wherein at least a portion of the exposure openings among the plurality of exposure openings are formed in a shape that compensates for the anisotropic deformation that occurs in the openings when each of the openings is caused to shrink by heating the patterned resist.
- the thermal flow process that uses the photomask of the present invention
- the resist that is applied to the surface of a layer of a semiconductor integrated circuit that is to undergo processing is patterned by an exposure process by means of the photomask and a plurality of openings are formed in the resist that correspond to the plurality of exposure openings that are formed in the photomask
- these openings are formed in a shape that compensates for the anisotropic deformation that occurs when the resist is heated to cause each of the openings to shrink.
- the resist that has been thus patterned is heated and the openings are caused to shrink, these openings are anisotropically deformed as they shrink.
- the openings attain the proper shape after shrinkage and deformation.
- At least a portion of exposure openings among the plurality of exposure openings may be formed in a shape that is elongated in a direction that is approximately orthogonal to the direction toward other exposure openings that are close. At least a portion of exposure openings among the plurality of exposure openings may also be enlarged in a direction that is approximately orthogonal to the direction toward other exposure openings that are close. The degree of enlargement of said exposure openings becomes smaller as the distance among said other exposure openings that are close becomes larger.
- the plurality of openings that have been formed in this way are caused to shrink by heating the resist, the plurality of openings that neighbor each other attain the proper shape upon shrinking because the degree of shrinkage is smaller in the direction toward other openings while the degree of shrinkage is greater in the direction orthogonal to this direction due to such factors as the surface tension of the resist.
- At least a portion of the exposure openings among the plurality of exposure openings are arranged in lines that are close together, and each of the exposure openings that are arranged in these lines may be enlarged in the direction that is approximately orthogonal to the direction of this arrangement.
- the exposure openings may be formed in a rectangular shape in which the direction of enlargement is the direction in which the long sides extend.
- Each of the exposure openings may be enlarged in substantially all directions, and at least a portion of the exposure openings among the plurality of exposure openings may be formed such that the degree of enlargement is smaller in the direction toward other exposure openings than other directions that are close.
- At least a portion of the exposure openings among the plurality of exposure openings may be formed as rectangles in which the short sides extend in the direction toward other exposure openings that are close and the long sides extend in a direction that is approximately orthogonal to this direction.
- the openings before being caused to shrink by the thermal flow process are circles having a diameter of “a ⁇ b,” but in the present invention, the exposure dimension of the resist openings is made “a ⁇ b” or greater in the direction of enlargement.
- the term “enlargement of exposure openings in the photomask” in the present invention means that, when forming openings of a desired dimension in the resist, the exposure openings are made larger than dimensions that are designed based merely on these openings.
- the diameter of circular openings that are caused to shrink by the thermal flow process as described hereinabove is “a” and the openings are caused to shrink to “1/b” by the thermal flow process
- the openings before being caused to shrink by the thermal flow process are circles of diameter “a ⁇ b.” If the exposure optics are equal power, square exposure openings measuring “a ⁇ b” on each side would be formed in the photomask, but in the present invention, the exposure openings that are formed in the photomask are rectangles in which the short sides are “a ⁇ b” in length and the long sides are longer than “a ⁇ b.”
- “approximately all directions” in the present invention means substantially all directions involved in the formation of the exposure openings and includes 360° of the two-dimensional directions that are parallel to the surface of the photomask, the four directions to the left and right and forward and rear that are parallel to the surface of the photomask, and the two directions that are parallel to the four sides of the exposure openings that are formed in a rectangular shape.
- the pattern forming method is a pattern forming method used in a thermal flow process in which: a resist is applied to a surface of the layers of a semiconductor integrated circuit that is to undergo processing; the resist is patterned to form a plurality of openings in the resist; and the resist that has been patterned is heated to cause each of the openings to shrink; wherein at least a portion of exposure openings among said plurality of exposure openings are formed in shapes so that said openings are caused to become corresponding desired shapes due to anisotropic deformation that occurs in said openings when said resist that has been patterned is heated to cause said openings to shrink.
- the pattern forming method is a pattern forming method used in a thermal flow process in which: a photomask is prepared in which a plurality of exposure openings are formed; a resist is applied to a surface of the layers of a semiconductor integrated circuit that is to undergo processing; this resist is patterned by an exposure process through the photomask to form a plurality of openings in the resist that correspond to the exposure openings; and the patterned resist is heated to cause each of the openings to shrink; wherein the photomask of the present invention is used during the exposure process.
- a prescribed portion of a semiconductor integrated circuit having fine planar shapes is treated by a prescribed process through openings in a resist that have been formed by the method of forming patterns of the above-described invention.
- FIGS. 1A-1C and FIGS. 2A-2C are schematic vertical section frontal views showing a semiconductor integrated circuit that is to undergo processing for explaining an example of a thermal flow process of the prior art
- FIG. 3A is a plan view showing an example of a photomask of the prior art
- FIG. 3B is a plan view showing a resist in which openings have been formed by exposure using the photomask shown in FIG. 3A;
- FIG. 3C is a plan view showing the state of openings that have been caused to shrink by heating the resist shown in FIG. 3B;
- FIG. 4A is a plan view showing one embodiment of the photomask according to the present invention.
- FIG. 4B is a plan view showing a resist in which openings have been formed by exposure using the photomask shown in FIG. 4A;
- FIG. 4C is a plan view showing the state of openings that have been caused to shrink by heating the resist shown in FIG. 4B;
- FIG. 5 is a characteristics chart showing the degree of deformation of the openings caused by heating of the resist
- FIG. 6A is a plan view showing the first modification of the photomask according to the present invention.
- FIG. 6B is a plan view showing the resist in which openings have been formed by exposure using the photomask shown in FIG. 6A;
- FIG. 6C is a plan view showing the state of openings that have been caused to shrink by heating the resist shown in FIG. 6B;
- FIG. 7 is a plan view showing an actual example of the dimensions of each part of a photomask according to the present invention.
- FIG. 8A is a plan view showing a modification of the exposure pattern formed on the resist
- FIG. 8B is a plan view showing the pattern of openings that are formed on the photomask of the prior art.
- FIG. 8C is a plan view showing the pattern of openings that are formed on a photomask of the present invention.
- FIGS. 4A-4C and FIG. 5 An embodiment according to the present invention will be described below with reference to FIGS. 4A-4C and FIG. 5 .
- Components of this embodiment that are identical to components of the above-described example of the prior art are identified by the same term, and detailed explanation is omitted.
- photomask 200 of this embodiment is also used to pattern resist 201 in a thermal flow process, and a plurality of exposure openings 202 are formed corresponding to the processing positions of a semiconductor integrated circuit (not shown in the figure) that is to undergo processing.
- the pattern forming method of this embodiment for example, nine openings 203 arranged in three rows and three columns are formed in resist 201 , which is applied to the surface of semiconductor integrated circuit, as shown in FIG. 4 C.
- the distances between these openings 203 is relatively small in the direction from front to back (vertical direction in the figure) and relatively large in the direction from left to right.
- nine exposure openings 202 are formed on photomask 200 in three rows and three columns that are close to each other in the front and rear directions but distant from each other toward the right and left, as shown in FIG. 4A, but these exposure openings 202 are formed in a shape that compensates for the anisotropic deformation that occurs in openings 203 when resist 201 is heated to cause openings 203 to shrink.
- each of the plurality of exposure openings 202 that are close to each other in the front and rear directions but distant from each other toward the left and right is formed in a rectangular shape, which is a square that has been enlarged toward the right and left.
- each of the plurality of exposure openings 202 that are close to each other toward the front and rear and arranged in lines is enlarged toward the left and right, which are directions orthogonal to the direction of arrangement.
- these exposure openings 202 are formed as rectangles having long sides that extend in the left and right directions, which are the directions of enlargement, and the sides that extend in the front and rear directions toward the other nearby exposure openings 202 are therefore the directions in which the short sides of these rectangles extend.
- each of the plurality of exposure openings 202 of photomask 200 is actually enlarged in almost all directions compared to the dimensions of opening 203 for the exposure process in resist 201 .
- the degree of enlargement of these exposure openings 202 is small in the front and rear directions that extend toward other closely neighboring exposure openings 202 , and exposure openings 202 are thus formed as shapes that are expanded toward the left and right.
- Exposure openings 202 which are arranged both toward the front and rear and toward the right and left of photomask 200 as described in the foregoing explanation, are also close to each other toward the right and left, although not as close as toward the front and rear, and exposure openings 202 are therefore also enlarged toward the front and rear, which is the direction orthogonal to the right and left. As described above, however, the degree of enlargement of exposure openings 202 is great toward the left and right and small toward the front and rear, the degree of enlargement in each direction being inversely proportional to the distance to a neighboring opening in that direction.
- resist 201 is applied to the surface of the semiconductor integrated circuit that is to undergo processing, and this resist 201 is then patterned by means of an exposure process by photomask 200 .
- a plurality of openings 203 corresponding to the plurality of exposure openings 202 of photomask 200 are formed in resist 201 .
- this resist 201 is heated and each of openings 203 is caused to shrink, openings 203 of resist 201 attain a small diameter that is less than the exposure limit dimensions, whereby a desired process can be performed in a fine area of a semiconductor integrated circuit.
- openings 203 in photomask 200 of this embodiment are formed in shapes that compensate for the anisotropic deformation of openings 203 as shown in FIG. 4A
- openings 203 that are formed in resist 201 by an exposure process that uses this photomask 200 are formed in an oval shape that is enlarged in the direction that is substantially orthogonal to the direction toward other openings 203 that are close, as shown in FIG. 4 B.
- openings 203 assume a substantially circular shape as shown in FIG. 4C due to the occurrence of anisotropic deformation according to the positional relation between the openings.
- each of exposure openings 202 is formed as a rectangle in which the right and left directions, which are the directions of chief enlargement, are the directions in which the long sides extend, and the design and fabrication of of the photomask is thus facilitated.
- openings 203 that were formed on resist 201 were arranged in lines extending toward the front and rear
- openings 203 may also arranged linearly in a direction that is at an angle, as in the previously described example of 1 ⁇ 4-pitch DRAM of the prior art.
- Simply adapting the above-described photomask 200 to this type of arrangement means that the exposure openings that were originally square must be enlarged in a direction that extends at an angle. The exposure openings must therefore be enlarged to form a parallelogram or diamond shape, and this complicates the design and fabrication of the photomask.
- a plurality of exposure openings 211 of photomask 210 are formed in rectangular shapes in which the long sides extend in an oblique direction that is orthogonal to direction of arrangement of these openings 211 .
- a plurality of openings 212 are formed as inclined oval shapes in resist 201 as shown in FIG. 6B, and these oval openings 212 are enlarged in directions that are orthogonal to the direction in which the openings are close to each other, whereby these openings 212 become proper circles when caused to shrink by heating resist 201 .
- the inventors of the present invention actually produced photomask 210 on an experimental basis in which openings 212 in resist 201 were arranged in a 45° direction as described in the foregoing explanation.
- the average diameter of openings 212 in resist 201 that were caused to shrink by heating resist 201 was set to 0.15 ⁇ m
- the pitch toward the front and rear as well as to the right and left of the plurality of openings 212 that were arranged in a 45° direction was set to 0.3 ⁇ m.
- openings 211 of photomask 210 were formed in rectangular shapes with short sides of 0.23 ⁇ m and long sides of 0.4 ⁇ m as shown in FIG. 7, and it was confirmed that openings 212 were finally formed having substantially the above-described dimensions.
- photomask 222 in which all of openings 221 can be formed in proper shape assuming three openings 221 having a diameter of 0.2 ⁇ m are arranged in resist 201 in a line at a pitch of 0.35 ⁇ m as shown in FIG. 8 A.
- central exposure openings 223 are preferably formed as rectangles measuring 0.24 ⁇ 0.30 ⁇ m and exposure openings 223 at the two ends are preferably formed as rectangles measuring 0.27 ⁇ 0.30 ⁇ m, as shown in FIG. 8 C.
- the degree of enlargement in the direction of arrangement of exposure openings 223 at both ends is preferably greater than the degree of enlargement of exposure openings 223 in the central area.
- exposure openings 202 of photomask 200 were enlarged in substantially all directions, i.e., toward the front, rear, left and right, with the degree of this enlargement for the front-rear directions differing from that for the left-right directions.
- exposure openings 202 it is also possible for exposure openings 202 to be enlarged in only specific directions.
Abstract
Description
Claims (9)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/341,159 US20030104289A1 (en) | 2000-01-11 | 2003-01-13 | Photomask and pattern forming method used in a thermal flow process and semiconductor integrated circuit fabricated using the thermal flow process |
US10/341,160 US6864021B2 (en) | 2000-01-11 | 2003-01-13 | Photomask and pattern forming method used in a thermal flow process and semiconductor integrated circuit fabricated using the thermal flow process |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000002582A JP3348786B2 (en) | 2000-01-11 | 2000-01-11 | Photomask, pattern forming method, semiconductor integrated circuit |
JP2000-002582 | 2000-01-11 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US10/341,160 Division US6864021B2 (en) | 2000-01-11 | 2003-01-13 | Photomask and pattern forming method used in a thermal flow process and semiconductor integrated circuit fabricated using the thermal flow process |
US10/341,159 Division US20030104289A1 (en) | 2000-01-11 | 2003-01-13 | Photomask and pattern forming method used in a thermal flow process and semiconductor integrated circuit fabricated using the thermal flow process |
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US20010007732A1 US20010007732A1 (en) | 2001-07-12 |
US6566041B2 true US6566041B2 (en) | 2003-05-20 |
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Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
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US09/757,841 Expired - Lifetime US6566041B2 (en) | 2000-01-11 | 2001-01-10 | Photomask and pattern forming method used in a thermal flow process and semiconductor integrated circuit fabricated using the thermal flow process |
US10/341,160 Expired - Lifetime US6864021B2 (en) | 2000-01-11 | 2003-01-13 | Photomask and pattern forming method used in a thermal flow process and semiconductor integrated circuit fabricated using the thermal flow process |
US10/341,159 Abandoned US20030104289A1 (en) | 2000-01-11 | 2003-01-13 | Photomask and pattern forming method used in a thermal flow process and semiconductor integrated circuit fabricated using the thermal flow process |
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Application Number | Title | Priority Date | Filing Date |
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US10/341,160 Expired - Lifetime US6864021B2 (en) | 2000-01-11 | 2003-01-13 | Photomask and pattern forming method used in a thermal flow process and semiconductor integrated circuit fabricated using the thermal flow process |
US10/341,159 Abandoned US20030104289A1 (en) | 2000-01-11 | 2003-01-13 | Photomask and pattern forming method used in a thermal flow process and semiconductor integrated circuit fabricated using the thermal flow process |
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US (3) | US6566041B2 (en) |
JP (1) | JP3348786B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050058914A1 (en) * | 2003-08-07 | 2005-03-17 | Maki Miyazaki | Pattern designing method, photomask manufacturing method, resist pattern forming method and semiconductor device manufacturing method |
US6872510B2 (en) * | 2000-02-15 | 2005-03-29 | Samsung Electronics Co., Ltd. | Photomask having small pitch images of openings for fabricating openings in a semiconductor memory device and a photolithographic method for fabricating the same |
US20070111365A1 (en) * | 2005-11-11 | 2007-05-17 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of microstructure and microelectromechanical system |
US7343666B2 (en) | 2004-06-30 | 2008-03-18 | Hitachi Global Storage Technologies Netherlands B.V. | Methods of making magnetic write heads with use of linewidth shrinkage techniques |
US20100107402A1 (en) * | 2004-06-30 | 2010-05-06 | Hitachi Global Storage Technologies | Methods Of Making Magnetic Write Heads With Use Of A Resist Channel Shrinking Solution Having Corrosion Inhibitors |
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JP2001274062A (en) * | 2000-03-27 | 2001-10-05 | Oki Electric Ind Co Ltd | Forming method of resist pattern and aligner |
JP3787271B2 (en) * | 2000-11-20 | 2006-06-21 | 東京応化工業株式会社 | Fine resist hole pattern forming method |
JP4552326B2 (en) * | 2001-01-17 | 2010-09-29 | ソニー株式会社 | Fine pattern forming method |
EP1434068A3 (en) | 2002-12-02 | 2004-07-28 | Shipley Company, L.L.C. | Methods of forming waveguides that are rounded in cross section and waveguides formed therefrom |
JP4480424B2 (en) * | 2004-03-08 | 2010-06-16 | 富士通マイクロエレクトロニクス株式会社 | Pattern formation method |
US7507661B2 (en) * | 2004-08-11 | 2009-03-24 | Spansion Llc | Method of forming narrowly spaced flash memory contact openings and lithography masks |
JP4907297B2 (en) * | 2005-11-11 | 2012-03-28 | 株式会社半導体エネルギー研究所 | Method for manufacturing microstructure and microelectromechanical device |
JP4597902B2 (en) | 2006-04-06 | 2010-12-15 | Tdk株式会社 | Method for forming resist pattern and method for manufacturing perpendicular magnetic recording head |
US8389402B2 (en) * | 2011-05-26 | 2013-03-05 | Nanya Technology Corporation | Method for via formation in a semiconductor device |
CN103377986B (en) * | 2012-04-17 | 2016-07-06 | 南亚科技股份有限公司 | The manufacture method of contact hole |
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- 2000-01-11 JP JP2000002582A patent/JP3348786B2/en not_active Expired - Fee Related
-
2001
- 2001-01-10 US US09/757,841 patent/US6566041B2/en not_active Expired - Lifetime
-
2003
- 2003-01-13 US US10/341,160 patent/US6864021B2/en not_active Expired - Lifetime
- 2003-01-13 US US10/341,159 patent/US20030104289A1/en not_active Abandoned
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JPH1083087A (en) | 1996-08-23 | 1998-03-31 | Samsung Electron Co Ltd | Formation of resist pattern |
US6265306B1 (en) * | 2000-01-12 | 2001-07-24 | Advanced Micro Devices, Inc. | Resist flow method for defining openings for conductive interconnections in a dielectric layer |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6872510B2 (en) * | 2000-02-15 | 2005-03-29 | Samsung Electronics Co., Ltd. | Photomask having small pitch images of openings for fabricating openings in a semiconductor memory device and a photolithographic method for fabricating the same |
US20050058914A1 (en) * | 2003-08-07 | 2005-03-17 | Maki Miyazaki | Pattern designing method, photomask manufacturing method, resist pattern forming method and semiconductor device manufacturing method |
US20060073425A1 (en) * | 2003-08-07 | 2006-04-06 | Kabushiki Kaisha Toshiba | Pattern designing method, photomask manufacturing method, resist pattern forming method and semiconductor device manufacturing method |
US7343666B2 (en) | 2004-06-30 | 2008-03-18 | Hitachi Global Storage Technologies Netherlands B.V. | Methods of making magnetic write heads with use of linewidth shrinkage techniques |
US20100107402A1 (en) * | 2004-06-30 | 2010-05-06 | Hitachi Global Storage Technologies | Methods Of Making Magnetic Write Heads With Use Of A Resist Channel Shrinking Solution Having Corrosion Inhibitors |
US8230582B2 (en) | 2004-06-30 | 2012-07-31 | HGST Netherlands B.V. | Methods of making magnetic write heads with use of a resist channel shrinking solution having corrosion inhibitors |
US20070111365A1 (en) * | 2005-11-11 | 2007-05-17 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of microstructure and microelectromechanical system |
US7537953B2 (en) | 2005-11-11 | 2009-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of microstructure and microelectromechanical system |
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US20030104290A1 (en) | 2003-06-05 |
US20030104289A1 (en) | 2003-06-05 |
US6864021B2 (en) | 2005-03-08 |
JP2001194769A (en) | 2001-07-19 |
US20010007732A1 (en) | 2001-07-12 |
JP3348786B2 (en) | 2002-11-20 |
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