TW461040B - Method for forming opening in a wafer layer - Google Patents

Method for forming opening in a wafer layer Download PDF

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Publication number
TW461040B
TW461040B TW89125442A TW89125442A TW461040B TW 461040 B TW461040 B TW 461040B TW 89125442 A TW89125442 A TW 89125442A TW 89125442 A TW89125442 A TW 89125442A TW 461040 B TW461040 B TW 461040B
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Taiwan
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layer
photoresist layer
photoresist
substrate
openings
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TW89125442A
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Chinese (zh)
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Jiun-Ren Huang
Yi-Shiung Huang
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United Microelectronics Corp
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Abstract

There is provided a method for forming opening in a wafer layer. At least two patterned photoresist layers are formed on a wafer layer, and the photoresist layers of different layers are used to surround and define a plurality of photoresist openings. Then, the wafer layer is etched to form openings, wherein each photoresist layer includes parallel line figures or rectangle-like bulk figures. When all the figures of each photoresist layer are of parallel line shape, the line figures in at least two photoresist layers are vertical to each other, so as to surround and form an array of photoresist openings. When all the figures of each photoresist layer are of rectangle-like bulk shape, the bulk figures in different photoresist layers are different in positions, so as to surround and define a plurality of photoresist openings.

Description

A7 B7 461040 6766twf. doc/00 8 五、發明說明(L) 本發明是有關一種半導體製程(Semiconductor Process) 中的微影触刻製程(Lithography & Etching Process).,且特 別是有關一種在晶圓層中形成開口(Opening)的方法。 由於半導體製程之尺寸愈來愈小,現行的曝光製程中 常需使用相移式光罩(ghase §hift Mask; PSM)或光學近接 效應修正式光罩(Qptical Proximity Correction(OPC) Mask) 來改善光阻圖案的輪廓。但是,隨著所欲形成之圖案尺寸 漸漸縮減到曝光光源的波長(Wavelength)以下至波長的一 半以上時,光波的繞射效應亦愈發顯著,尤其是對接觸窗 開口(Contact Hole)/介層窗開口(Via Hole)等開口類型的光 阻圖案來說,其輪廓並無法以相移式光罩作有效的改善。 另一方面,由於光學近接效應修正光罩必須對光罩圖 形作一些細微的修正,所以其設計與光罩製作上皆甚爲麻 煩,而且當光阻圖案的圖形間隔(Pitch)過小時,光學近接 效應修正光罩的輔助圖形(Assistant Features)甚至沒有擺放 的空間。因此,微影製程所形成之光阻層開口可能會產生 圓化的形狀,使得蝕刻製程所形成之晶圓層開口亦成爲圓 化的形狀。如果此晶圓層開口係爲接觸窗開口 /介層窗開 口,則稍後將形成之接觸窗/介層窗的形狀、截面積與電 阻皆難以掌控。 本發明提出一種在晶圓層中形成開口的方法,其可用 來形成尺寸介於曝光光源波長之半至波長之間的開口。本 發明係進行至少兩次微影製程以形成至少兩層光阻層,並 藉不同層的光阻層來圍出許多光阻層開口,然後進行蝕刻 3 (請先閲讀背面之注意事項再填寫本頁) 裝 tri-----!線, 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 461040 6766twf. doc/008 五、發明說明(>) (請先閲讀背面之注意事項V填寫本頁) 以在晶圓層中形成開口,其中每一光阻層皆包含平行之線 狀圖形,或近似矩形之塊狀圖形。這些塊狀圖形係由具有 矩形圖案的光罩曝光而得,其係因光波的繞射效應而具有 圓化的四個角落’所以此處稱爲「近似矩形之塊狀圖形」。 當各光阻層中圖形皆爲平行線狀時,則至少有二光阻層中 的線狀圖形互相垂直,並藉此圍出光阻層開口之陣列;當 各光阻層中隱形爲近似矩形之塊狀時,則不同光阻層中之 塊狀圖形的位置相異而圍出光阻層開口,其中每一個塊狀 圖形的四個角落皆位於另一光阻層中之塊狀圖形的上方或 下方,而不會作爲光阻層開口的邊界。 在上述本發明中,各光阻層皆可能是正光阻或負光 阻’但是所有光阻層中只能有一層是正光阻層,否則在第 二層正光阻層進行曝光顯影時,第一層正光阻層即會被除 去。再者,如果此唯一的正光阻層不是最後一層光阻層, 則因正光阻層會在其後之負光阻層曝光時受到照光而產生 光酸’故負光阻層的顯影液必須採用對曝光後之正光阻毫 無影響者。 經濟部智慧財產局員工消費合作社印製 如上所述’本發明的第一種方法係以圖形輪廓良好的 二或多層垂直交錯之線狀圖案來圍出光阻層開口,所以光 阻層開口的角落不會產生圓化的形狀。另外,本發明在採 用多層塊狀光阻圖形來圍出光阻層開口時,由於每一個塊 狀圖形中輪廓形狀較差(圓化)的四個角落皆位於另一光阻 層之塊狀圖形的上方或下方,所以光阻層開口皆係由直線 狀的塊狀圖形邊緣中段所圍出,而不會有圓化的形狀。也 4 本紙張尺度適用中國國冢標準(CNS)A4規;公楚)--:- 6 1 04 Ο Α7 6766twf.doc/008 ____B7______ 五、發明說明()) 就是說’本發明可以使後續蝕刻製所形成之晶圓層開口的 形狀與截面積更易於掌控;而如果所形成之開口係爲接觸 窗開口/介層窗開口,即表示稍後將形成之接觸窗/介層窗 的形狀、截面積與電阻均更容易掌控。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂, 下文特舉二較佳實施例,並配合所附圖式,作詳細說明如 下: 圖式之簡單說明: 第1A-1C圖所繪示爲本發明第一實施例中,以二層線 狀圖案光阻層在絕緣層中形成開口的方法,其中第1C圖 係爲一剖面圖,其所對應之剖面爲第1B僵中直線Ι-Γ所 切出之平面;以及 第2A-2C圖所繪示爲本發明第二實施例中,以二層塊 狀圖案之光阻層在絕緣層中形成開口的方法,其中第2C 圖係爲一剖面圖,其所對應之剖面爲第2B圖中直線Π-ΙΓ 所切出之平面;。 圖式之標號說明: 100、200 :基底 110、210 :絕緣層 120、220 :負光阻層 130、. 230 :正光阻層 140、240 :光阻層開口 150/250 :接觸窗(Contact)開口 /介層窗(Via)開口 Ι-Γ、ΙΙ-ΙΓ :直線 X、Y :座標镡號 第一實施例 請參照第1A圖,首先提供基底100,再於基底100 5 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝·!丨訂--------線 經濟部智慧財產局員工消費合作社印製 461040 6766twf.doc/008 B7 五、發明說明(w) 上形成絕緣層no,此基底100例如是用來製作動態隨機 存取記憶體(Dynamic Random Access Memory,DRAM)的 基底,其上已形成有記憶胞(Memory Cell)之金氧半導體 (MOS),或是更上層需作電性連接的導線。接著進行第一 次微影製程,以在絕緣層110上形成具有一特定圖形間隔 /寬度(Pitch/Size)之平行條狀圖形的負光阻層120,其中所 使用之曝光機台例如爲波長248nm之KrF準分子雷射掃 描器。此負光阻層120之形成步驟如下:首先全面性地覆 蓋一負光阻層(未顯示)於絕緣層110上方,再進行一軟烤 步驟(Soft Bake)以減少此負光阻層中的溶劑量。接著使用 曝光光源與光罩對此負光阻層曝光,再進行一曝光後烘烤 步驟(Post-exposure Bake,PEB),然後使此負光阻層顯影 即可。 經濟部智慧財產局員工消費合作社印製 請參照第1B圖,接著於基底100上形成具有另一特 定圖形間隔/寬度之平行條狀圖形的正光阻層130,其中各 條狀圖形之走向與負光阻層120中的條狀圖形垂直,而圍 出排成二維陣列的光阻層開口 140,其係暴露出絕緣層110 的一部分。此正光阻層130同樣是以248nm之KrF準分 子雷射作爲曝光光源,其圖形間隔a/寬度b爲0.2μπι /0.1 μηι,使得光阻層開口 140的較短(Υ方向)寬度爲0.1 μιη (約波長248nm之半),而此圖形間隔/寬度皆小於負光阻層 120之圖形間隔/寬度。另外,此正光阻層130之形成步驟 與負光阻層120相似,只是此時所欲定義者爲全面覆蓋之 正光阻層而已。另外,由於之前形成的負光阻層120係由 6 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 461040 6766twf.doc/008 A7 B7 五、發明說明(文) 高分子的交鏈(Cross-linking)而形成,故不必擔心其受正 光阻層130之曝光顯影製程的影響。 請參照第1C圖所示之剖面圖,其所對應之剖面爲第 1B圖中直線Ι-Γ所切出之平面。如第ic圖所示,接著以 負光阻層120與正光阻層130 (請見第1B圖)爲罩幕,蝕 刻暴露於光阻層開口 140中的絕緣層11〇,以在絕緣層11〇 中形成接觸窗開口 /介層窗開口 150。 如上所述,本發明第一實施例係使用二次微影製程, 形成輪廓品質良好的二層垂直交錯之平行線狀光阻圖案以 圍出光阻層開口,所以光阻層開口的角落不會產生圓化的 形狀。 此外’由於本發明第一實施例係藉由兩次微影製程所 形成之兩層光阻層來圍出光阻層開口,所以當光阻曆開口 之長寬比(Aspect Ratio,其値爲由上方觀視基底時之光阻 層開口的長度寬度比)不爲1時(第1B圖),或是光阻層開 口在二垂直方向的圖形間隔/寬度不同時(第1B圖),各微 影製程中的曝光條件即可分別調整爲最佳狀態,.從而得到 關鍵尺寸(Critical Dimension,CD)精準的開口。依此類推, 當欲形成之平行條狀圖案光阻層的層數大於二時,亦可分 別調整每一光阻層的曝光條件以得到精確的關鍵尺寸。 第二實施例 請參照第2A圖,首先提供基底200,再於基底200 上形成絕緣層210,此基底2〇〇例如是用來製作動態隨機 7 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -----·--I I I I I,^i I (請先閱讀背面之注§項再填窝本頁) 言· · 經濟部智慧財產局員工消費合作社印製 A7 B7 4 6 1 04 0 6766twf. doc/008 五、發明說明(& ) 存取記憶體(Dynamic Random Access Memory ’ DRAM)的 基底,其上已形成有記憶胞之金氧半導體,或是更上層需 作電性連接的導線。接著進行第一次微影製程,以在絕緣 層210上形成二維塊狀圖形之負光阻層220,這些塊狀圖 形皆是以具有矩形圖形的光罩曝光而得’且因光波之繞射 效應而在其四個角落具有圓化之形狀。此處所使用之曝光 機台爲波長248nm之KrF準分子雷射掃描器’且此負光 阻層220之較短的(Y方向)圖形間隔a/寬度b爲 0.3μιη/0.2μηι。此負光阻層220之形成步驟如下:首先全 面性地覆蓋一負光阻層(未顯示)於絕緣層21〇上方’再進 行一軟烤步驟以減少此負光阻層中的溶劑量。接著使用曝 光光源與光罩對此負光阻層曝光,再進行一曝光後烘烤 (ΡΕΒ)步驟,然後使此負光阻層顯影即可。 請參照第2Β圖,接著於基底200上形成具有二維塊 狀圖形的正光阻層230,其中各塊狀圖形與負光阻層22〇 中的塊狀圖形圍出許多光祖層開口 240’並暴露出絕緣層 210的一部分。此正光阻層230中的塊狀圖形也是以具有 矩形圖形的光罩曝光而得,且因光波之繞射效應而在其四 個角落具有圓化之形狀。 請繼續參照第_2Β圖,正光阻層230與負光阻層220 的Χ/Υ方向圖形間隔/寬度皆相同,但位置不同,即正光 阻層230 (負光阻層220)中每一個塊狀圖形的中心皆位在 負光阻層220 (正光阻層23〇)中四個塊狀圖形的正中央, 使得光阻層開口 240的較短(Υ方向)寬度爲〇·1μηι (約波長 8 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -----;--------r>·裝—— (請先閲讀背面之注意事項^^寫本頁) 訂: --線」 經濟部智慧財產局員工消費合作社印製 461040 6766twf. doc/008 A7 B7 五、發明說明) 248nm之半)(第2A圖)。此外,正光阻層230中每一個塊 (請先閱讀背面之注意事項再填寫本頁) 狀圖形的四個角落皆位在負光阻層220中的四個塊狀圖形 之上,且正光阻層230中的塊狀圖形覆蓋住負光阻層220 中每一個塊狀圖形的四個角落,使得相鄰兩行/列的光阻 層開口 240以錯位之方式排列。另外,.此正光阻層230之 形成步驟與負光阻層220相似,只是此時所欲定義者爲全 面覆蓋之正光阻層而已。 請參照第2C圖所示之剖面圖,其所對應之剖面爲第 2B圖中直線ΙΙ-ΙΓ所切出之平面。如第2C圖所示,接著 以正光阻層230與負光阻層220 (請見第2B圖)爲罩幕, 蝕刻暴露於光阻層開口 240中的絕緣層210,以在絕緣層 210中形成接觸窗開口/介層窗開口 250。 如上所述’在本發明第二實施例中,由於負光阻層220 中每一個塊狀圖形圓化的四個角落皆位於正光阻層230之 塊狀圖形的下方,且正光阻層230中每一個塊狀圖形圓化 的四個角落皆位於負光阻層220中之塊狀圖形的上方,所 以光阻層開口 240皆係由呈直線狀的塊狀圖形邊緣中段所 圍出,而不會具有圓化的形狀。 經濟部智慧財產局員工消費合作社印製 綜上所述’本發明較佳實施例係採用兩層輪廓形狀良 好的光阻層來圍出寬度約爲曝光波長之半的開口,所以開 口形狀可以保持矩形,使得蝕刻後能形成矩形的接觸窗開 口/介層窗開口,進而能夠精確地控制稍後將形成之接觸 窗/介層窗的形狀、截面積與電阻。 除此之外’本發明亦可應用於dram中之溝渠式電 9A7 B7 461040 6766twf. Doc / 00 8 V. Description of the Invention (L) The present invention relates to a lithography and etching process in a Semiconductor Process, and in particular to an on-chip lithography process. Method for forming openings in a circular layer. As the size of semiconductor processes is getting smaller, the current exposure process often requires the use of a phase shift mask (ghase §hift Mask; PSM) or an optical proximity effect correction mask (OPC) Mask to improve light Of resistance pattern. However, as the size of the pattern to be formed gradually decreases to below the wavelength of the exposure light source (Wavelength) to more than half the wavelength, the diffraction effect of the light wave becomes more and more significant, especially for the contact hole / media For a photoresist pattern of an opening type such as a layer hole, the contour cannot be effectively improved by a phase-shifting photomask. On the other hand, because the optical proximity effect correction mask must make some minor corrections to the mask pattern, its design and mask making are very troublesome, and when the pattern pitch of the photoresist pattern is too small, the optical The Assistant Features of the Proximity Correction Mask do not even have room for placement. Therefore, the photoresist layer opening formed by the lithography process may have a rounded shape, so that the wafer layer opening formed by the etching process also becomes a rounded shape. If the wafer layer opening is a contact window / via window opening, the shape, cross-sectional area, and resistance of the contact window / via window to be formed later are difficult to control. The present invention provides a method for forming an opening in a wafer layer, which can be used to form an opening having a size between half and the wavelength of an exposure light source. In the present invention, at least two photolithography processes are performed to form at least two photoresist layers, and many photoresist layer openings are surrounded by different photoresist layers, and then etched. 3 (Please read the precautions on the back before filling This page) is equipped with the tri -----! Line, printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 461040 6766twf. Doc / 008 V. Explanation of the invention (>) (Please read the precautions on the back of the page to fill out this page first) to form openings in the wafer layer, where each photoresist layer contains parallel linear patterns or approximately rectangular block patterns. These block patterns are obtained by exposing a mask with a rectangular pattern. The block patterns have rounded four corners due to the diffraction effect of light waves. Therefore, they are referred to as "approximately rectangular block patterns" here. When the patterns in each photoresist layer are parallel lines, at least two linear patterns in the photoresist layer are perpendicular to each other, thereby surrounding the array of photoresist layer openings; when the photoresist layer is invisible, it is approximately rectangular In the case of a block, the positions of the block patterns in different photoresist layers are different and surround the photoresist layer opening. The four corners of each block pattern are above the block pattern in the other photoresist layer. Or below, rather than as the border of the photoresist layer opening. In the present invention described above, each photoresist layer may be a positive photoresist or a negative photoresist. However, only one of all photoresist layers is a positive photoresist layer. Otherwise, when the second positive photoresist layer is exposed and developed, the first The positive photoresist layer is removed. Furthermore, if the only positive photoresist layer is not the last photoresist layer, the developing solution of the negative photoresist layer must be used because the positive photoresist layer will be exposed to light when the subsequent negative photoresist layer is exposed. Those who have no influence on the positive photoresist after exposure. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the above-mentioned 'The first method of the present invention is to surround the photoresist layer opening with two or more vertical staggered line patterns with good graphic outlines, so Does not produce rounded shapes. In addition, in the present invention, when a multilayer block photoresist pattern is used to surround the photoresist layer opening, the four corners with poor outline shapes (rounded) in each block pattern are located in the block pattern of another photoresist layer. Above or below, the openings of the photoresist layer are all surrounded by the middle of the edge of the linear block pattern, and there will be no rounded shape. 4 This paper size applies the Chinese National Standard (CNS) Standard A4; Gongchu) --- 6 1 04 〇 Α7 6766twf.doc / 008 ____B7______ 5. Description of the invention ()) This means that the present invention can make subsequent etching The shape and cross-sectional area of the wafer layer opening formed by the system are easier to control; if the opening formed is a contact window opening / interstitial window opening, it means that the shape of the contact window / interstitial window to be formed later, Both cross-sectional area and resistance are easier to control. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following describes two preferred embodiments and the accompanying drawings in detail, as follows: Brief description of the drawings: Figures 1A-1C The drawing shows a method for forming openings in an insulating layer with two linear patterned photoresist layers in the first embodiment of the present invention. FIG. 1C is a cross-sectional view, and the corresponding cross-section is 1B. The plane cut by the straight line I-Γ; and FIG. 2A-2C illustrates the method of forming an opening in the insulating layer with a photoresist layer with a two-layer block pattern in the second embodiment of the present invention. The figure is a cross-sectional view, and the corresponding cross-section is the plane cut by the straight line Π-ΙΓ in Fig. 2B; Description of drawing numbers: 100, 200: substrate 110, 210: insulation layer 120, 220: negative photoresist layer 130,. 230: positive photoresist layer 140, 240: photoresist layer opening 150/250: contact window Openings / via openings I-Γ, ΙΙ-ΙΓ: Straight X, Y: Coordinate 镡 For the first embodiment, please refer to Figure 1A, first provide the substrate 100, and then the substrate 100 5 This paper size is applicable to China National Standard (CNS) A4 Specification (210 X 297 mm) (Please read the precautions on the back before filling this page)丨 Order -------- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 461040 6766twf.doc / 008 B7 V. Description of the invention (w) An insulating layer no is formed on the substrate 100, for example, it is used to make dynamic The base of the random random access memory (DRAM) has a metal oxide semiconductor (MOS) of a memory cell formed thereon, or a wire that needs to be electrically connected at an upper layer. Then, the first lithography process is performed to form a negative photoresist layer 120 having a parallel stripe pattern with a specific pattern interval / width (Pitch / Size) on the insulating layer 110. The exposure machine used is, for example, a wavelength 248nm KrF excimer laser scanner. The negative photoresist layer 120 is formed as follows: firstly, a negative photoresist layer (not shown) is completely covered on the insulating layer 110, and then a soft bake step is performed to reduce the negative photoresist layer in the negative photoresist layer. Amount of solvent. Then use an exposure light source and a photomask to expose the negative photoresist layer, and then perform a post-exposure bake (PEB) step, and then develop the negative photoresist layer. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to FIG. 1B, and then form a positive photoresist layer 130 having a parallel bar pattern with another specific pattern interval / width on the substrate 100. The stripe pattern in the photoresist layer 120 is vertical, and the photoresist layer openings 140 arranged in a two-dimensional array surround a part of the insulation layer 110. This positive photoresist layer 130 also uses a 248nm KrF excimer laser as an exposure light source, and its pattern interval a / width b is 0.2 μm / 0.1 μηι, so that the short (Υ direction) width of the photoresist layer opening 140 is 0.1 μιη (About half of the wavelength of 248nm), and the pattern interval / width is smaller than the pattern interval / width of the negative photoresist layer 120. In addition, the formation steps of the positive photoresist layer 130 are similar to the negative photoresist layer 120, except that the one to be defined at this time is the positive photoresist layer that covers the entire area. In addition, since the previously formed negative photoresist layer 120 is made of 6 papers, the Chinese national standard (CNS) A4 specification (210 X 297 mm) is applicable. 461040 6766twf.doc / 008 A7 B7 V. Description of the invention (text) Polymer Is formed by cross-linking, so there is no need to worry about it being affected by the exposure and development process of the positive photoresist layer 130. Please refer to the cross-sectional view shown in FIG. 1C, and the corresponding cross-section is the plane cut by the straight line I-Γ in FIG. 1B. As shown in FIG. Ic, the negative photoresist layer 120 and the positive photoresist layer 130 (see FIG. 1B) are then used as a mask to etch the insulating layer 11 exposed in the photoresist layer opening 140, so that the insulating layer 11 The contact window opening / interstitial window opening 150 is formed in 〇. As described above, the first embodiment of the present invention uses a secondary lithography process to form a two-layer vertical staggered parallel linear photoresist pattern with good contour quality to surround the photoresist layer opening, so the corners of the photoresist layer opening will not Produces a rounded shape. In addition, since the first embodiment of the present invention uses two photoresist layers formed by two lithography processes to surround the photoresist layer opening, when the photoresist passes through the opening aspect ratio (Aspect Ratio, the reason is When viewing the substrate from above, the length-width ratio of the photoresist layer opening is not 1 (Figure 1B), or when the pattern spacing / width of the photoresist layer opening in the two vertical directions are different (Figure 1B), each micro The exposure conditions in the film production process can be individually adjusted to the best state, so as to obtain a critical opening (Critical Dimension, CD) accurate opening. By analogy, when the number of layers of the parallel stripe pattern photoresist layer to be formed is greater than two, the exposure conditions of each photoresist layer can also be adjusted to obtain accurate critical dimensions. For the second embodiment, please refer to FIG. 2A. First, a substrate 200 is provided, and then an insulating layer 210 is formed on the substrate 200. This substrate 200 is used to make dynamic random 7 paper sizes, which are applicable to the Chinese National Standard (CNS) A4 specifications. (210 X 297 mm) ----- · --IIIII, ^ i I (Please read the note § on the back before filling in this page) Words · · Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 4 6 1 04 0 6766twf. Doc / 008 5. & Description of the substrate of the Dynamic Random Access Memory 'DRAM, on which a gold-oxide semiconductor with memory cells has been formed, or the upper layer requires Conductor for electrical connection. Then, the first lithography process is performed to form a two-dimensional block-shaped negative photoresist layer 220 on the insulating layer 210. These block-shaped patterns are obtained by exposing a photomask with a rectangular pattern, and are caused by light waves. The radiation effect has rounded shapes at its four corners. The exposure machine used here is a KrF excimer laser scanner 'with a wavelength of 248 nm, and the short (Y-direction) pattern interval a / width b of this negative photoresist layer 220 is 0.3 μm / 0.2 μm. The steps of forming the negative photoresist layer 220 are as follows: First, a negative photoresist layer (not shown) is completely covered on the insulating layer 21, and then a soft baking step is performed to reduce the amount of solvent in the negative photoresist layer. Then use an exposure light source and a photomask to expose this negative photoresist layer, and then perform a post-exposure baking (PEB) step, and then develop the negative photoresist layer. Referring to FIG. 2B, a positive photoresist layer 230 having a two-dimensional block pattern is then formed on the substrate 200, wherein each block pattern and the block pattern in the negative photoresist layer 22o enclose a plurality of light progenitor layer openings 240 '. A part of the insulating layer 210 is exposed. The block pattern in the positive photoresist layer 230 is also obtained by exposing with a mask having a rectangular pattern, and has a rounded shape at its four corners due to the diffraction effect of light waves. Please continue to refer to FIG. 2B. The X / Υ pattern spacing / width of the positive photoresist layer 230 and the negative photoresist layer 220 are the same, but the positions are different, that is, each block in the positive photoresist layer 230 (negative photoresist layer 220). The center of the shape pattern is located at the center of the four block patterns in the negative photoresist layer 220 (positive photoresist layer 23), so that the short (Υ direction) width of the photoresist layer opening 240 is 0.1 μm (approximate wavelength). 8 This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) -----; -------- r > · Packing—— (Please read the precautions on the back first ^^ (Write this page) Order: --- line Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 461040 6766twf. Doc / 008 A7 B7 V. Description of the invention) (half of 248nm) (picture 2A). In addition, the four corners of each block in the positive photoresist layer 230 (please read the precautions on the back before filling this page) are located on the four block patterns in the negative photoresist layer 220, and the positive photoresist The block pattern in the layer 230 covers the four corners of each block pattern in the negative photoresist layer 220, so that the adjacent photoresist layer openings 240 in two adjacent rows / columns are arranged in a misaligned manner. In addition, the formation steps of the positive photoresist layer 230 are similar to those of the negative photoresist layer 220, except that the one to be defined at this time is a positive photoresist layer that is completely covered. Please refer to the cross-sectional view shown in FIG. 2C, and the corresponding cross-section is the plane cut by the straight line II-IΓ in FIG. 2B. As shown in FIG. 2C, the positive photoresist layer 230 and the negative photoresist layer 220 (see FIG. 2B) are then used as a mask to etch the insulating layer 210 exposed in the photoresist layer opening 240 so that A contact window opening / interstitial window opening 250 is formed. As described above, in the second embodiment of the present invention, since the four corners of each block pattern rounded in the negative photoresist layer 220 are located under the block pattern of the positive photoresist layer 230, and in the positive photoresist layer 230, The four corners of each block pattern round are located above the block pattern in the negative photoresist layer 220, so the photoresist layer openings 240 are all surrounded by the middle of the edge of the linear block pattern without Will have a rounded shape. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In summary, the preferred embodiment of the present invention uses two photoresist layers with good contours to enclose an opening with a width of about half the exposure wavelength, so the shape of the opening can be maintained. The rectangle makes it possible to form a rectangular contact window / interstitial window opening after etching, so as to accurately control the shape, cross-sectional area, and resistance of the contact window / interstitial window to be formed later. In addition, the invention can also be applied to trench-type electricity in dram 9

本紙張尺度適用中國國家標準(CNS)A4T規格(210 X 297公H 4 6 1 04 Ο 6766twf. doc/008 B7 五、發明說明(¾ ) 容器(Trench Capacitor)的製作上,這是因爲溝渠式電容器 (Trench Capacitor)之下電極形成方法係先在節點接觸窗上 方形成絕緣層’再於絕緣層中形成暴露出節點接觸窗的開 口,以作爲稍後將形成之電谷器下電極的模板,其跑/接觸 窗開口 /介層窗開口之形成與排列方式非常相似。 雖然本發明已以一較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 神和範圍內,當可作各種之更動與潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 _______.___— II ^ i — ; i . (請先閲讀背面之注意事項V#寫本頁) 訂----------線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐〉This paper size applies to China National Standard (CNS) A4T specifications (210 X 297 male H 4 6 1 04 〇 6766twf. Doc / 008 B7 V. Description of the invention (¾) Trench Capacitor) This is because of the trench type The method of forming an electrode under a capacitor (Trench Capacitor) is to first form an insulating layer above the node contact window, and then form an opening in the insulating layer that exposes the node contact window as a template for the lower electrode of the valleyr to be formed later. The formation and arrangement of the running / contact window opening / interstitial window opening are very similar. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art will not depart from it. Within the spirit and scope of the present invention, various modifications and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. _______.___— II ^ i —; i. (Please First read the notes on the back V # write this page) Order ---------- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with China National Standard (CNS) A4 (210 X 297) Mm>

Claims (1)

461040 6766twf.doc/008 A8 B8 C8 D8 六、申請專利範圍 1. 一種在晶圓層中形成開口的方法,適用於一基底, 該基底上已形成有一晶圓層,且該方法包括下列步驟: 先後於該基底上形成圖案化之至少二光阻層,其中每 一該些光阻層中皆具有平行之複數條線狀圖形,且該些光 阻層中至少有一層中的該些線狀圖形與其他該些光阻層中 的該些線狀圖形垂直,而在該晶圓層上圍出複數個光阻層 開口;以及 以該些光阻層爲罩幕,蝕刻暴露於該些光阻層開口中 的該晶圓層,而形成複數個開口。 2. 如申請專利範圍第1項所述之方法,其中形成圖案 化之該些光阻層的複數次微影製程中所使用之曝光光源皆 具有相同之一特定波長,且該些開口之寬度介於該特定波 長之半與該特定波長之間。 3. 如申請專利範圍第1項所述之方法,其中該些光阻 層之圖形間隔/寬度(Pitch/Size)不盡相同,且形成每一該些 光阻層時之曝光條件係依其本身之圖形間隔/寬度作調 整。 經濟部智慧財產局員工消費合作社印製 4. 如申請專利範圍第1項所述之方法,其中形成任一 該些光阻層於該基底上的方法,包括下列步驟: 全面性地覆蓋一光阻層於該基底上; 進行一軟烤步驟以減少該光阻層中的溶劑量; 使用一曝光光源與一光罩對該光阻層曝光; 進行一曝光後烘烤步驟;以及 使該光阻層顯影。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297^^57 經濟部智慧財產局員工消費合作社印製 6 10 4 0 A8 B8 C8 6766twf.doc/008 D8 六、申請專利範圍 5. —種在晶圓層中形成開口的方法,適用於一基底, 該基底上已形成有一晶圓層,且該方法包括下列步驟: 形成圖案化之一第一光阻層於該晶圓層上,該第一光 阻層具有互相平行之複數條第一線狀圖形; 形成圖案化之一第二光阻層於該晶圓層與該第一光阻 層上,該第二光阻層具有互相平行之複數條第二線狀圖 形,該些第二線狀圖形之走向係與該些第一線狀圖形垂 直,而在該晶圓層上圍出複數個光阻層開口;以及 以該第一光阻層與該第二光阻層爲罩幕,飩刻暴露於 該些光阻層開口中的該晶圓層,以形成複數個開口。 6. 如申請專利範圍第5項所述之方法,其中形成圖案 化之該第一光阻層及該第二光阻層的兩次微影製程中所使 用之曝光光源具有相同之一特定波長,且該些開口之寬度 介於該特定波長之半與該特定波長之間。 7. 如申請專利範圍第5項所述之方法,其中該基底係 爲製作動態隨機存取記憶體之基底,該基底上已形成有複 數個金氧半導體,且該晶圓層係爲一絕緣層,而該些開口 係作爲複數個接觸窗開口。 8. 如申請專利範圍第5項所述之方法,其中該基底係 爲製作動態隨機存取記憶體之基底,該基底上已形成有欲 作電性連接之複數條導線,且該晶圓層係爲一絕緣層,而 該些開口係作爲複數個介層窗開口。 9. 如申請專利範圍第5項所述之方法,其中該基底係 爲製作動態隨機存取記憶體之基底,該基底上已形成有複 --------j I I-----I-----訂·!-----綾* (請先閱讀背面之注音?事項本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 1 6 104 0 as g 6766twf.doc/008 D8 六、申請專利範圍 數個節點接觸窗,且該晶圓層係爲一絕緣層,其中每一該 些開口係將該些節點接觸窗之一暴露出來,且該些開口係 作爲稍後將形成之複數個電容器下電極的模板。 10. 如申請專利範圍第5項所述之方法,其中在圖案化 該第二光阻層時所進行之一顯影製程中,該第一光阻層不 受到影響,且該第一光阻層/該第二光阻層之型態爲負光 阻/負光阻、負光阻/正光阻、正光阻/負光阻三種組合之一。 11. 如申請專利範圍第5項所述之方法,其中該第一光 阻層中具有一第一圖形間隔/寬度(Pitch/Size),該第二光阻 層中具有一第二圖形間隔/寬度,該第一圖形間隔/寬度不 等於該第二圖形間隔/寬度,且形成該第一光阻層與該第 二光阻層時之曝光條件係分別依該第一圖形間隔/寬度與 該第二圖形間隔/寬度作調整。 12. 如申請專利範圍第5項所述之方法,其中該第一光 阻層中具有一第一圖形寬度/間隔,且該第二光阻層中具 有一第二圖形寬度/間隔,而該第一圖形寬度/間隔等於該 第二圖形寬度/間隔。 13. —種在晶圓層中形成開口的方法,適用於一基底’ 該基底上已形成有一晶圓層,且該方法包括下列步驟: 形成圖案化之一第一光阻層於該晶圓層上,該第一光 阻層中具有複數個第一塊狀圖形,且係由具有矩形圖形之 一第一光罩而得; 形成圖案化之一第二光阻層於該晶圓層與該第一光阻 層上,該第二光阻層具有複數個第二塊狀圖形,且係由具 (請先閱讀背面之注意事項寫本頁) !裝 -SJ _線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 461040 C8 6766twf.doc/008 D8 六、申請專利範圍 有矩形圖形之一第二光罩而得,該些第二塊狀圖形與該些 第一塊狀圖形圍出複數個光阻層開口,其中每一該些第二 塊狀圖形的四個角落皆位在該些第一塊狀圖形之上,且該 些第二塊狀圖形係覆蓋住每一該些第一塊狀圖形的四個角 落;以及 以該第一光阻層與該第二光阻層爲罩幕,蝕刻暴露於 該些光阻層開口中的該晶圓層,以形成複數個開口。 14. 如申請專利範圍第13項所述之方法,其中形成圖 案化之該第一光阻層及該第二光阻層的過程中所使用之曝 光光源具有相同之一特定波長,且該些開口之寬度介於該 特定波長之半與該特定波長之間。 15. 如申請專利範圍第13項所述之方法,其中該些第 一塊狀圖形在二垂直方向上排成一第一二維陣列,且該些 第二塊狀圖形在該二垂直方向上排成一第二二維陣列,而 每一該些第一塊狀圖形皆位在相鄰的四個第二塊狀圖形之 間,且每一該些第二塊狀圖形皆位在相鄰的四個第一塊狀 圖形之間。 16. 如申請專利範圍第15項所述之方法,其中該基底 係爲製作動態隨機存取記憶體之基底,該基底上已形成有 複數個金氧半導體,且該晶圓層係爲一絕緣層,而該些開 口係作爲複數個接觸窗開口。 17. 如申請專利範圍第15項所述之方法,其中該基底 係爲製作動態隨機存取記憶體之基底,該基底上已形成有 欲作電性連接之複數條導線,且該晶圓層係爲一絕緣層, 14 ------I-----I i -11 (請先閱讀背面之注音5事項寫本頁) 訂· 線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 4 6 1 04 0 as C8 6766twf. doc/008 D8 六、申請專利範圍 而該些開口係作爲複數個介層窗開口。 18. 如申請專利範圍第15項所述之方法,其中該基底 係爲製作動態隨機存取記憶體之基底,該基底上方已形成 有複數個節點接觸窗,且該晶圓層係爲一絕緣層,其中每 一該些開口係將該些節點接觸窗之一暴露出來,且該些開 口係作爲稍後將形成之複數個電容器下電極的模板。 19. 如申請專利範圍第15項所述之方法,其中每一該 些第一塊狀圖形與每一該些第二塊狀圖形的大小皆相同, 且每一該些第一塊狀圖形之中心位置皆在相鄰之四個第二 塊狀圖形的正中央,而每一該些第二塊狀圖形之中心位置 皆在相鄰之四個第一塊狀圖形的正中央。 20. 如申請專利範圍第13項所述之方法,其中在圖案 化該第二光阻層時所進行之一顯影製程中,該第一光阻層 不受到影響,且該第一光阻層/該第二光阻層之型態爲負 光阻/負光阻、負光阻/正光阻、正光阻/負光阻三種組合之 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)461040 6766twf.doc / 008 A8 B8 C8 D8 6. Scope of patent application 1. A method for forming an opening in a wafer layer is applicable to a substrate, a wafer layer has been formed on the substrate, and the method includes the following steps: A patterned at least two photoresist layers are successively formed on the substrate, wherein each of the photoresist layers has a plurality of parallel linear patterns, and at least one of the photoresist layers has the linear shapes. The pattern is perpendicular to the linear patterns in the other photoresist layers, and a plurality of photoresist layer openings are surrounded on the wafer layer; and the photoresist layers are used as a mask to expose the light by etching. The wafer layer in the resist opening forms a plurality of openings. 2. The method according to item 1 of the scope of patent application, wherein the exposure light sources used in the multiple lithography processes for forming the patterned photoresist layers have the same specific wavelength, and the widths of the openings Between half of the specific wavelength and the specific wavelength. 3. The method according to item 1 of the scope of patent application, wherein the pattern interval / width (Pitch / Size) of the photoresist layers is different, and the exposure conditions when forming each of the photoresist layers are based on it. Adjust the interval / width of the graphics itself. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4. The method described in item 1 of the scope of patent application, wherein the method of forming any of these photoresist layers on the substrate includes the following steps: Comprehensively covering a light A resist layer on the substrate; performing a soft baking step to reduce the amount of solvent in the photoresist layer; using an exposure light source and a photomask to expose the photoresist layer; performing a post-exposure baking step; and making the light Resistive layer development. This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 ^^ 57 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6 10 4 0 A8 B8 C8 6766twf.doc / 008 D8 VI. Scope of patent application 5. — A method for forming an opening in a wafer layer is applicable to a substrate on which a wafer layer has been formed, and the method includes the following steps: forming a patterned first photoresist layer on the wafer layer, The first photoresist layer has a plurality of first linear patterns parallel to each other; a patterned second photoresist layer is formed on the wafer layer and the first photoresist layer, and the second photoresist layer has mutual A plurality of parallel second linear patterns, the directions of the second linear patterns are perpendicular to the first linear patterns, and a plurality of photoresist layer openings are enclosed on the wafer layer; and A photoresist layer and the second photoresist layer are masks, and the wafer layer exposed in the openings of the photoresist layers is engraved to form a plurality of openings. 6. As described in item 5 of the scope of patent application Method, in which patterned first photoresist layer and second photoresist are formed The exposure light source used in the two lithography processes has the same specific wavelength, and the width of the openings is between half of the specific wavelength and the specific wavelength. 7. As described in item 5 of the scope of patent application In the method, the substrate is a substrate for making a dynamic random access memory, a plurality of metal-oxide semiconductors have been formed on the substrate, the wafer layer is an insulating layer, and the openings are used as a plurality of contacts. The window opening. 8. The method as described in item 5 of the scope of patent application, wherein the substrate is a substrate for making a dynamic random access memory, and a plurality of wires for electrical connection have been formed on the substrate, and The wafer layer is an insulating layer, and the openings are used as a plurality of interstitial window openings. 9. The method according to item 5 of the patent application scope, wherein the substrate is a substrate for making a dynamic random access memory , There is a complex -------- j I I ----- I ----- ordered !! ----- 绫 * (please read the note on the back first? Page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 1 6 104 0 as g 6766twf.doc / 008 D8 6. There are several node contact windows in the scope of patent application, and the wafer layer is an insulation layer, and each of these openings exposes one of the node contact windows. And the openings serve as a template for a plurality of capacitor lower electrodes that will be formed later. 10. The method as described in item 5 of the scope of patent application, wherein one of the steps is performed when the second photoresist layer is patterned. During the development process, the first photoresist layer is not affected, and the types of the first photoresist layer / the second photoresist layer are negative photoresist / negative photoresist, negative photoresist / positive photoresist, and positive photoresist / One of three combinations of negative photoresistance. 11. The method according to item 5 of the scope of patent application, wherein the first photoresist layer has a first pattern interval / width (Pitch / Size), and the second photoresist layer has a second pattern interval / Width, the first pattern interval / width is not equal to the second pattern interval / width, and the exposure conditions when forming the first photoresist layer and the second photoresist layer are based on the first pattern interval / width and the The second graphic interval / width is adjusted. 12. The method according to item 5 of the patent application, wherein the first photoresist layer has a first pattern width / space and the second photoresist layer has a second pattern width / space, and the The first pattern width / interval is equal to the second pattern width / interval. 13. —A method for forming an opening in a wafer layer, applicable to a substrate 'A wafer layer has been formed on the substrate, and the method includes the following steps: forming a patterned first photoresist layer on the wafer On the layer, the first photoresist layer has a plurality of first block patterns, and is obtained from a first photomask having a rectangular pattern; a patterned second photoresist layer is formed on the wafer layer and On the first photoresist layer, the second photoresist layer has a plurality of second block-shaped figures, and is provided by (please read the precautions on the back first to write this page)! -SJ _ 线 · Ministry of Economic Affairs Intellectual Property The paper size printed by the Bureau ’s Consumer Cooperative is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 461040 C8 6766twf.doc / 008 D8 6. The scope of patent application is obtained from a second photomask with a rectangular figure. The second block patterns and the first block patterns surround a plurality of photoresist layer openings, and four corners of each of the second block patterns are located above the first block patterns. , And the second block graphics cover each of the first blocks Pattern corners off; and in the first photoresist layer and the second photoresist layer as a mask, etching the exposed layer of the wafer to the plurality of openings in the photoresist layer to form a plurality of openings. 14. The method according to item 13 of the scope of patent application, wherein the exposure light sources used in forming the patterned first photoresist layer and the second photoresist layer have the same specific wavelength, and these The width of the opening is between half of the specific wavelength and the specific wavelength. 15. The method according to item 13 of the scope of patent application, wherein the first block-shaped figures are arranged in a first two-dimensional array in two vertical directions, and the second block-shaped figures are in the two vertical directions. Arranged in a second two-dimensional array, and each of the first block-shaped figures is located between four adjacent second block-shaped figures, and each of the second block-shaped figures is located adjacent to each other Between the four first blocky graphics. 16. The method according to item 15 of the scope of the patent application, wherein the substrate is a substrate for making a dynamic random access memory, a plurality of metal-oxide semiconductors have been formed on the substrate, and the wafer layer is an insulator Layer, and the openings serve as a plurality of contact window openings. 17. The method according to item 15 of the scope of patent application, wherein the substrate is a substrate for making a dynamic random access memory, a plurality of wires to be electrically connected have been formed on the substrate, and the wafer layer It is an insulation layer, 14 ------ I ----- I i -11 (Please read the note on the back 5 items to write this page) Order · Thread · Printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 4 6 1 04 0 as C8 6766twf. Doc / 008 D8 6. The scope of patent application and these openings are used as a plurality of interlayer window openings. 18. The method according to item 15 of the scope of patent application, wherein the substrate is a substrate for making dynamic random access memory, a plurality of node contact windows have been formed above the substrate, and the wafer layer is an insulator Layer, each of the openings exposes one of the node contact windows, and the openings serve as a template for a plurality of capacitor lower electrodes to be formed later. 19. The method according to item 15 of the scope of patent application, wherein each of the first block-like figures and each of the second block-like figures have the same size, and each of the first block-like figures has the same size. The center positions are all in the middle of the four adjacent second block patterns, and the center positions of each of the second block patterns are in the middle of the four first block patterns. 20. The method according to item 13 of the patent application, wherein in a developing process performed when the second photoresist layer is patterned, the first photoresist layer is not affected, and the first photoresist layer / The type of the second photoresist layer is negative photoresistance / negative photoresistance, negative photoresistance / positive photoresistance, positive photoresistance / negative photoresistance, and three types of combinations. Printed on paper standards for China National Standard (CNS) A4 specification (210 X 297 mm)
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