r Λ 3262 3 五、發明說明（/ ) 技術領域： 本發明疋關於一種積體電路(丨ntegrated Circuits ;丨(^ 之導電層的製造方法，特別是指在導電層微影 (photolithography)過程中，能減少寬導線之間短路問題 光罩佈局(丨ayout)方式。r Λ 3262 3 V. Description of the invention (/) Technical field: The present invention relates to a method for manufacturing a conductive layer of integrated circuits (丨 integrated Circuits; 丨 (^), especially during the process of photolithography of the conductive layer. , Can reduce the short-circuit problem between wide wires.
A7 B7 發明背景： 按，在積體電路的製程技術中，必須在晶圓上刻劃各 種圖案，以製備半導體元件，此刻劃圖案的技術便是微影 (lithography)技術，所謂的微影技術是將光罩上的圖案投射 到晶圓上，隨著積體電路的集積密度增加，光罩的解析度 就變得越來越重要，由其是在元件結構日益趨向小型化的 今日，如何準確地製造出所需的光罩圖案以及在晶圓表面 曝出光罩圖案，就變成積體電路工業一個十分重要的課題 微影技術的一大瓶頸就是如何於曝光和對準過程中精 確地控制和監測線寬的臨界尺寸(critica丨dimension ; CD)，傳統的光罩製作，係利用電子束在光罩石英基板表 面的鉻(Cr)膜製定出事先設計好的佈局圖案，每—層次光 罩上的佈局圖案一般都是採用相同臨界尺寸，然而，因為 光學近接(optical proximity)現象影響’在不同特徵尺寸或 密度的圖案交界處就會產生圖案扭曲，這也就是所謂的微 負載現象(micro-loading effect)，此圖案必須作適度的修 正’才能減少設計的佈局圖案與轉移至晶圓表面圖案的臨 界尺寸偏差(CD variation)。 私紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公t ) (請先閲讀背面之注意事項再填寫本頁) 裝--------訂---------< 經濟部智慧財產局員工消費合作社印製 p d 3 2 6 2 3 A? __;_B7 _—__ 五、發明說明（〆） 習知針對不同密度圖案的一種修正方法是在密度較小 的空擴區’額外的擺上一些假圖案(dummy pattern)，請參 閱曰本NEC公司的美國專利第5,598,010 號 ’Semiconductor integrated circuit device having dummy pattern effective against micro loading effect”，如此光罩上的圖案分佈較為均句，就可以減輕微 負載現象造成的臨界尺寸偏差了。 但是’此種方式並無法適用在含有不同特徵尺寸的圖 案上，特別是線寬特別的上層金屬線(電源線或地線），請 參閱圖一 ’以一寬度為ΙΟμιτί的金屬線而言，每一條金屬線 上又有許多尺寸較小的介層孔(Vja)，兩條金屬線之間的距 離必須由設計準則的〇·4μΓΤΐ加寬到約〇_7μΓΠ才行，不然就 會曝不開而造成金屬線短路的問題，然而，這又會對集積 密度產生負面的影響。 因此’本發明提供一種積體電路寬金屬線的光罩佈局 方法’能夠徹底改善上述之缺點，產生高品質的積體電 路。 發明之概述： 本發明之主要目的為φς供一種積體電路寬金屬線的光 罩佈局方法’能釣有效地縮短金屬線之間的距離，達到高 集積密度的功效。 本發明之次要目的為提供一種積體電路寬金屬線的光 罩佈局方法，能夠徹底改善微影不良所造成金屬線短路的 問題，產生高品質的積體電路。 ____3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------^--------訂---------嗜- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 f f4326 2 3 Α _____Β7_____ 五、發明說明（5 ) 本發明之另一目的為提供—種積體電路寬金屬線的光 罩佈局方法，可以利用現有的微影設備及較為嚴苛的設計 準則下，即達到改善積體電路集積密度的功效。 本發明之再一目的為提供一種製程簡單且具有高度實 用性的製程方法，可以適用於不同型態的硬式幕罩材質之 上。 本發明係利用以下的佈局方式，來達成上述之種種目 的，可以將兩條寬金屬線相臨的部份設計成拉鍊狀，將介 層孔兩兩交錯的排列，在有介層孔(via)的區域保持原本的 位置延伸出一定距離包住介層孔(via)，在沒有介層孔(Vja) 的區域則向内縮’如此一來，兩條金屬線之間的距離自然 加寬’也就不會有習知微負載現象(micro-loading effect)所 產生的短路問題了，另一方面，本發明也可以將兩條寬金 屬線相臨的部份設計成如相對應的鋸齒狀，此時，介層孔 之間的金屬線距離雖然並未增加，但此鋸齒狀的圖案受到 金屬圓化現象(metal rounding effect)的影響，會曝成向内 縮的圓弧狀’仍能達到解決習知微負載現象阼匕「〇_丨〇3(；)丨叩 effect)所產生短路問題之功效。 總之’本發明之特徵係在於兩條寬金屬線相臨的部份 成凹凸的交錯排列，此凹凸的交錯排列可以為任何形狀如 正方形、長方形、圓弧狀或是波浪(wave)狀，本發明所述 寬金屬線的佈局方法於焉完成。 本紙張尺度適用中國國篆標準（CNS)M規格（21G x 297公餐） ------------^--------訂-------！線 _ (請先閱讀背面之注意事項再填寫本頁) 广 4 32 62 3 A7 經濟部智慧財產局員工消費合作社印^ίA7 B7 Background of the invention: According to the process technology of integrated circuits, various patterns must be scribed on the wafer to prepare semiconductor elements. The technology of patterning at this moment is the lithography technology, the so-called lithography The technology is to project the pattern on the photomask onto the wafer. As the integration density of the integrated circuit increases, the resolution of the photomask becomes more and more important. Since the component structure is increasingly miniaturized, How to accurately produce the required mask pattern and expose the mask pattern on the wafer surface has become a very important subject in the integrated circuit industry. A major bottleneck in lithography technology is how to accurately in the exposure and alignment process Control and monitor the critical dimension of line width (critica 丨 dimension; CD). The traditional photomask is made by using a chromium (Cr) film on the surface of the quartz substrate of the photomask to make a pre-designed layout pattern. The layout patterns on the photomask generally use the same critical size. However, the optical proximity phenomenon affects' at the junction of the patterns with different feature sizes or densities. Will produce a pattern distortion, which is the so-called micro-loading phenomenon (micro-loading effect), this pattern must be made modest correction 'in order to reduce design layout pattern and transferred to the wafer surface pattern critical dimension variation (CD variation). Private paper size applies to China National Standard (CNS) A4 specification (210 x 297 g t) (Please read the precautions on the back before filling this page) -< Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs pd 3 2 6 2 3 A? __; _ B7 _—__ V. Description of the Invention (〆) A correction method for different density patterns is known in the lower density. The "empty expansion area" is additionally placed with some dummy patterns, please refer to US Patent No. 5,598,010 of the NEC Corporation, "Semiconductor integrated circuit device having dummy pattern effective against micro loading effect", so the pattern distribution on the photomask A more uniform sentence can reduce the critical dimensional deviation caused by the micro-load phenomenon. However, 'this method cannot be applied to patterns containing different characteristic sizes, especially upper metal wires (power wires or ground wires) with special line widths. Please refer to Figure 1 '. For a metal line with a width of 10μιτί, each metal line has many smaller vias (Vja). The distance between the two metal lines must be determined by design guidelines. The width of 0.4 μΓΤΐ is only widened to about 0_7 μΓΠ, otherwise it will not be exposed and the metal wire will be short-circuited. However, this will negatively affect the accumulation density. Therefore, the present invention provides a integrated circuit The mask layout method of wide metal lines can thoroughly improve the above-mentioned disadvantages and produce high-quality integrated circuits. Summary of the invention: The main purpose of the present invention is to provide a mask layout method of wide metal lines for integrated circuits. The fishing effectively shortens the distance between the metal wires and achieves the effect of high accumulation density. A secondary object of the present invention is to provide a photomask layout method for a wide metal wire of an integrated circuit, which can completely improve the short circuit of the metal wire caused by poor lithography. Problems, resulting in high-quality integrated circuits. __3 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------------ ^ ------ --Order --------- Addiction- (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs f f4326 2 3 Α _____ Β7 _____ V. Description of the invention (5) Another object of the present invention is Provided—A photomask layout method for a wide metal line of an integrated circuit can use the existing lithographic equipment and more stringent design criteria to achieve the effect of improving the integrated density of the integrated circuit. Another object of the present invention is to provide A simple and highly practical manufacturing method can be applied to different types of hard curtain materials. The present invention uses the following layout methods to achieve the above-mentioned various purposes. The two adjacent wide metal wires can be designed in a zipper shape, and the interlayer holes are arranged in a staggered manner. The area in) extends to a certain distance to enclose the via, and in the area without Vja, it shrinks inwardly. As a result, the distance between the two metal lines naturally widens 'There will be no short-circuit problem caused by the conventional micro-loading effect. On the other hand, the present invention can also design the adjacent parts of two wide metal wires as corresponding sawtooth At this time, although the distance of the metal lines between the vias of the interlayer is not increased, the jagged pattern is affected by the metal rounding effect, and will be exposed in a circular arc shape that shrinks inwardly. It can achieve the effect of solving the short-circuit problem caused by the conventional micro-load phenomenon "0_ 丨 〇3 (;) 丨 叩 effect". In short, the feature of the present invention is that the portion where two wide metal lines are adjacent is uneven. The staggered arrangement of the bumps can be No matter how the shape is square, rectangular, arc or wave, the method of layout of the wide metal wire according to the present invention is completed in 焉. This paper size is applicable to China National Standard (CNS) M specification (21G x 297) Meal) ------------ ^ -------- Order -------! Line_ (Please read the precautions on the back before filling out this page) Canton 4 32 62 3 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ ί
五、發明說明（if ) 圖式的簡要說明： 圖一為習知技藝的寬金屬線光罩佈局圖。 圖二為本發明實施例的寬金屬線光罩佈局圖。 圖二為本發明實施例寬金屬線於顯影後的上視圖。 圖號說明： 11-寬金屬線 15-介層孔 25-金屬線邊緣的佈局 31-寬金屬線 35-顯影後的金屬線邊緣 36,介層孔 發明之詳細說明： 本發明是有關於光罩製作時一種積體電路寬金屬線的 光罩佈局方法，在詳細說明中是運用具體實施例說明本發 明的原則與精神。 首先，請參閱圖一，為一按照傳統的積體電路設計準 則（design rule)之佈局圖，圖中有三條寬金屬線i1a、 11b、11c在金屬層間介電層(IMD)13的表面，寬金屬線上 有著許多介層孔(via)15穿過金屬層間介電層(|MD)i3與下 一層的金屬連接。所述寬金屬線上的尺寸遠大於所述介層 孔(via)，為了要確保在微影時不受到微負載現象(micr〇_ loading effect)的影響而有曝不開的情況發生，兩條金屬線 之間的距離必須加大才行，以一寬度為1〇μηι的金屬線而 ____S 13-金屬層間介電層 21,寬金屬線 26-介層孔 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） _<請先閱讀背面之注意事項再填寫本頁) 裝 訂---------線 經濟部智慧財產局員工消費合作社印製 Γ r4 32 6 2 - ' A7 *** : ---—2Z__——__ 五、發明說明（/) 言’兩條金祕之_雜必須由設計判卜般金屬線距 到約〇.7μΠΊ才足夠’如此一來就會增加了積 體電路兀件的面積，進而增加生產成本。 接箸’請參關二及圖三，為本發明寬金屬線的光罩 佈局方法較佳實施例的詳細說明。如圖二所示，可以將寬 金屬線21a、21b相臨的部份設計成如左半部的拉鍊狀 25a ’將介層孔26兩兩交錯的排列，在有介層孔_25的 區域保持原本的位置延伸出一定距離包住介層孔(vja)，在 沒有介層孔(via)25的區域則向内縮，如此一來，兩條金屬 線之間的距離自然加寬’也就不會有習知微負載現象 (micro-loading effect)所產生的短路問題了。 另一方面，本發明也可以圖二右半邊的佈局來操作， 將兩條寬金屬線21b、21c相臨的部份設計成如相對應的 鋸齒狀25b，此時，介層孔26之間的金屬線距離雖然並未 增加，但此鋸齒狀的圖案受到金屬圓化現象㈨咖 rounding effect)的影響，會曝成向内縮的圓弧狀，仍能達 到解決習知微負載現象(micro-loading effect)所產生短路問 題之功效。本發明之特徵係在於兩條寬金屬線相臨的部份 成凹凸的交錯排列，此凹凸的交錯排列可以為任何形狀如 正方形、長方形、圓弧狀或是波浪(wave)狀，當然如圖二 所示的正方形是比較容易由設計軟體(EDA)中自動化得 到。 ' 請參閱圖三，為本發明實施例的光罩微影之後的寬金 屬線上視圖。可以很明顯的看出，對於三條寬金屬線 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） ------------I---- (請先閱讀背面之注意事項再填寫本頁) A7 五、發明說明（h) 31a、31b、31c而言，無論是左半部拉鍊狀35a或是右半 部鋸齒狀35b的圖案，由於受到金屬圓化現象的影響，都 會自然曝成向内縮的圓弧狀，同時介層孔36亦變成圓 形。因此，利用本發明的光罩佈局方式，可以採取較嚴苛 的設計準則，以一寬度為ΙΟμητι的金屬線而言，兩條金屬 線之間的距離可以由原本的〇·7μηι所短為約0.4μΓη即可， 就不會有習知微負載現象(micro-丨oading effect)所產生的短 路問題了，在大幅降低了生產成本的同時也確保的積體電 路產品的良率及可靠性。 上述說明係以較佳實施例來闡述本發明，而非限制本 發明’並且熟知半導體技藝之人士皆能明暸，適當而作些 微的改變及調整，仍將不失本發明之要義所在，亦不脫離 本發明之精神和範圍。 -------------1--------訂---------.線 ·(請先03-讀背面之注意事項再填寫本頁) 經'濟部智慧財產局員工消費合作社印製 本紙張尺度ίδ財 i ®^iV(CNS)A4 (210 x 297V. Brief description of the invention (if) diagrams: Figure 1 is a layout diagram of a wide metal wire mask of a conventional technique. FIG. 2 is a layout diagram of a wide metal line photomask according to an embodiment of the present invention. FIG. 2 is a top view of a wide metal wire after development according to an embodiment of the present invention. Description of figure number: 11-wide metal line 15-interlayer hole 25-layout of metal line edge 31-wide metal line 35-developed metal line edge 36, detailed description of the invention of the interlayer hole: The present invention relates to light A mask layout method for integrated circuit wide metal lines when a mask is manufactured. In the detailed description, specific embodiments are used to illustrate the principles and spirit of the present invention. First, please refer to FIG. 1, which is a layout diagram according to a conventional integrated circuit design rule. There are three wide metal lines i1a, 11b, and 11c on the surface of the metal interlayer dielectric layer (IMD) 13. The wide metal line has a number of vias (via) 15 that pass through the interlayer dielectric layer (| MD) i3 and are connected to the metal of the next layer. The size of the wide metal line is much larger than the via. In order to ensure that it is not affected by the microloading effect (micr0_ loading effect) during lithography, it cannot be exposed. Two The distance between the metal wires must be increased. With a metal wire with a width of 10 μηι, ____S 13-metal interlayer dielectric layer 21, wide metal wire 26-interlayer holes. This paper applies Chinese national standards ( CNS) A4 specification (210 X 297 mm) _ < Please read the notes on the back before filling out this page) Binding --------- Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economics Γ r4 32 6 2-'A7 ***: ---— 2Z __——__ V. Description of the invention (/) The words' two gold secrets _ must be designed by a judgement-like metal line spacing to about 0.7μΠΊ is enough' so This will increase the area of the integrated circuit components, thereby increasing production costs. Please refer to the second step and the third step for a detailed description of a preferred embodiment of a mask layout method for a wide metal wire according to the present invention. As shown in Figure 2, the adjacent parts of the wide metal wires 21a and 21b can be designed like a zipper shape 25a on the left half. The interlayer holes 26 are arranged in a staggered manner. In the area with interlayer holes _25, Keep the original position to extend a certain distance to enclose the via hole (vja), and in the area without via hole (via) 25, it will shrink inward. In this way, the distance between the two metal lines naturally widens. There will be no short-circuit problems caused by the conventional micro-loading effect. On the other hand, the present invention can also be operated with the layout of the right half of FIG. 2. The adjacent portions of the two wide metal lines 21 b and 21 c are designed to correspond to the corresponding zigzag shape 25 b. At this time, between the interlayer holes 26 Although the distance between the metal lines does not increase, the jagged pattern is affected by the rounding effect of the metal, and it will be exposed to an inwardly-arc shape, which can still solve the conventional micro-load phenomenon (micro -loading effect). The feature of the present invention is that the adjacent parts of two wide metal lines are staggered and arranged in an uneven manner. The staggered arrangement of the unevenness can be any shape such as a square, a rectangle, an arc, or a wave. Of course, as shown in FIG. The square shown in Figure 2 is relatively easy to automate in design software (EDA). 'Please refer to FIG. 3, which is a wide metal line view after the photolithography of the embodiment of the present invention. It can be clearly seen that the paper size of the three wide metal wires applies the Chinese National Standard (CNS) A4 specification (21〇X 297 public love) ------------ I ---- ( (Please read the notes on the back before filling this page) A7 V. Description of the invention (h) For 31a, 31b, 31c, whether it is the pattern of the zigzag 35a on the left half or the zigzag 35b on the right half, due to the metal The effect of the rounding phenomenon will be naturally exposed into a circular arc shape that shrinks inward, and the interstitial hole 36 also becomes circular. Therefore, by using the photomask layout method of the present invention, more stringent design criteria can be adopted. For a metal wire with a width of 10 μητι, the distance between two metal wires can be shortened by approximately 0.7 μm 0.4μΓη is sufficient, and there will be no short-circuit problem caused by the known micro-oading effect. While greatly reducing the production cost, it also ensures the yield and reliability of integrated circuit products. The above description is to illustrate the present invention with preferred embodiments, but not to limit the present invention, and those skilled in the art of semiconductors will understand that making appropriate changes and adjustments will still not lose the essence of the present invention, nor will it Depart from the spirit and scope of the present invention. ------------- 1 -------- Order ---------. Line · (Please 03-read the notes on the back before filling this page) Printed on a paper scale by the Consumer Cooperatives of the Ministry of Economic Affairs and Intellectual Property Bureau ίδ 财 i ® ^ iV (CNS) A4 (210 x 297