KR0126636B1 - Fine patterning method of semiconductor device - Google Patents
Fine patterning method of semiconductor deviceInfo
- Publication number
- KR0126636B1 KR0126636B1 KR1019940014571A KR19940014571A KR0126636B1 KR 0126636 B1 KR0126636 B1 KR 0126636B1 KR 1019940014571 A KR1019940014571 A KR 1019940014571A KR 19940014571 A KR19940014571 A KR 19940014571A KR 0126636 B1 KR0126636 B1 KR 0126636B1
- Authority
- KR
- South Korea
- Prior art keywords
- pattern
- line width
- semiconductor device
- mask
- region
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000000059 patterning Methods 0.000 title abstract 2
- 230000002093 peripheral effect Effects 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 238000001459 lithography Methods 0.000 abstract description 5
- 239000002184 metal Substances 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Semiconductor Memories (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
Description
제 1 도는 디램의 주요 부분의 배치를 도시한 도면.1 shows the layout of the main parts of the DRAM.
제 2 도는 종래의 기술로 디램의 메탈라인을 동일한 선폭으로 형성한 마스크.2 is a mask in which the metal lines of the DRAM are formed in the same line width according to the related art.
제 3 도는 본 발명에 와해 디램의 메탈라인의 선폭을 단차가 달라지는 지역별로 다르게 형성한 마스크.3 is a mask in which the line width of the metal line of the DRAM according to the present invention is differently formed for each region where the step is different.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 메모리셀 2 : 워드라인 스트래핑1: memory cell 2: word line strapping
3 : 디코더 4 : 센스 앰프3: decoder 4: sense amplifier
5 : 메탈라인5: metal line
본 발명은 반도체소자의 패턴 형성방법에 관한 것으로, 특히 고집적 반도체소자에서 패턴을 리소그라피공정으로 형성할 때 셀지역과 주변회로지역의 단차로 인하여 패턴선폭이 달라지는 것을 해결하기 위한 반도체소자의 패턴 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a pattern of a semiconductor device. In particular, a method of forming a pattern of a semiconductor device for solving a pattern line width change due to a step difference between a cell region and a peripheral circuit region when a pattern is formed by a lithography process in a highly integrated semiconductor device. It is about.
반도체소자 제조시 후반부 공정으로 가면서 만차(topology)가 셀지역과 주변회로 지역간에 심하게 발생하여 리소그라피공정의 마진확보에 매우 어려운 문제가 있다. 즉, 서로 단차가 다른 지역에서 동일한 선폭을 갖는 마스크로 패턴을 형성할 경우 감광막패턴의 크기가 달라지는 문제가 있다.As semiconductor devices are manufactured in the latter process, topologies are severely generated between the cell region and the peripheral circuit region, which makes it difficult to secure a margin of the lithography process. That is, when the pattern is formed with a mask having the same line width in areas where the steps are different from each other, the size of the photoresist pattern is different.
제 1 도 디램의 주요부분의 배치를 도시한 도면으로서, 메모리 셀(1), 워드라인 스트래핑(2), 디코더(3), 센스앰프(4)가 각각 기판 상에 배치되는 위치를 도시한다.FIG. 1 is a diagram showing the arrangement of main parts of the DRAM, showing the positions where the memory cell 1, the word line strapping 2, the decoder 3, and the sense amplifier 4 are disposed on the substrate, respectively.
제 2 도는 메모리셀(1), 워드라인 스트래핑(2), 메모리셀(1) 상부에 메탈라인(5)이 형성되는 것을 도시한 도면으로서, 종래에는 상기 메탈라인(5)의 선폭을 동일하게 마스크에 형성하여 사용하였다.FIG. 2 is a view illustrating a metal line 5 formed on a memory cell 1, a word line strapping 2, and an upper portion of the memory cell 1. Conventionally, the line widths of the metal lines 5 are the same. It formed in the mask and used.
그러나, 상기의 메모리셀과 주변회로지역(예를 들어 센스 앰프 또는 워드라인 스트래핑, 디코더지역) 간에는 단차가 심하게 발생한다. 즉, 메모리셀지역은 단차가 높과, 주변회로 지역은 단차가 낮아서 메모리셀 지역에 메탈라인의 패턴이 정상적으로 형성될 때 주변회로 지역은 노광에너자양이 상대적으로 작게 도달하여 메탈라인의 마스크로 사용되는 감광막의 선폭이 넓어지거나, 스컴(scum)이나 브릿지(bridge)성의 감광막이 남는 문제가 발생한다.However, a significant step is generated between the memory cell and the peripheral circuit area (for example, sense amplifier, word line strapping, and decoder area). That is, when the memory cell region has a high step and the peripheral circuit region has a low step, when the metal line pattern is normally formed in the memory cell region, the exposure energy amount reaches a relatively small amount and is used as a mask for the metal line. A problem arises in that the line width of the photoresist film becomes wider or a scum or bridge photoresist film remains.
따라서, 본 발명은 상기한 문제점을 해결하기 위하여 단차가 높은 지역과 단차가 낮은 지역 간에 마스크의 패턴선폭을 다르게 하여 일정한 노광에너지에 대하여 동일한 패턴선폭을 얻도록 하는 반도체소자의 패턴형성방법을 그 목적이 있다.Accordingly, an object of the present invention is to provide a pattern forming method of a semiconductor device in which a pattern line width of a mask is different between a region having a high step and a region having a low step to obtain the same pattern line width for a constant exposure energy. There is this.
본 발명에 의하면, 반도체소자의 패턴 제조방법에 있어서, 기판 상에 패턴을 형성할 때 단차가 높은 지역이나, 단차가 낮은 지역에 노광에너지양이 균일하게 도달되도록 하기 위하여 단차가 낮은 지역에서는 마스크의 패턴선폭(d)은 작게 하고, 단차가 높은 지역에서는 마스크의 패턴선폭(d)을 일정하게 유지하도록 된 마스크를 사용하여 패턴을 형성하는 것을 특징으로 한다.According to the present invention, in the method of manufacturing a pattern of a semiconductor device, when forming a pattern on a substrate, the mask is applied in a region having a high step, or in a region having a low step so that the amount of exposure energy is uniformly reached in a region having a low step. The pattern line width d is made small, and a pattern is formed by using a mask which keeps the pattern line width d of a mask constant in a region where the step height is high.
이하, 본 발명을 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.
제 3 도는 본 발명에 의해 패턴을 형성할 때 단차가 낮은 지역 예를 들어 워드라인 스트래핑(2) 지역에서의 마스크의 패턴선폭(d')은 작게하여 스페이서를 크게 하고, 단차가 높은 지역에 예를 들어 메모리셀(1) 지역에는 패턴선폭(d)을 그대로 유지하도록 마스크를 형성한 것이다.3 shows the pattern line width d 'of the mask in a region having a low level, for example, in the region of the word line strapping 2, when the pattern is formed according to the present invention, so that the spacer is made large, and a region having a high level is formed. For example, a mask is formed in the region of the memory cell 1 to maintain the pattern line width d.
즉, 마스크 내의 단차가 높은 메모리셀과 단차가 낮은 주변회로 지역 간에 선폭 디자인을 달리하여 리소그라피공정의 마진을 확보하는 것이다. 예를 들어 노광에너지양의 전달이 상대적으로 많은 단차가 높은 자역은 디자인을 동일 선폭 개념으로 하고, 상대적으로 노광에너지양의 전달이 적은 단차가 낮은 지역은 패턴선폭 스페이스를 넓게 디자인하여 노광에너지양이 많아 지도록 하는 것이다.That is, the margin of lithography process is secured by varying the line width design between the memory cell having a high step height and the peripheral circuit area having a low step height. For example, a magnetic field with a high level of step difference, which has a relatively large amount of exposure energy transfer, has a design with the same line width concept, and an area with a low level where there is a small amount of exposure energy transfer has a wide pattern line width space, thereby increasing the amount of exposure energy. It is to increase.
본 발명에 의하면, 리소그라피공정시 상기한 마스크를 이용하여 메탈 또는 도전층 패턴을 형성하면 단차의 차이로 인하여 발생되는 패턴 선폭의 크기가 달라지는 등의 문제점을 해결할 수 있다.According to the present invention, when the metal or the conductive layer pattern is formed using the mask during the lithography process, problems such as the size of the pattern line width generated due to the difference in the step may be solved.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940014571A KR0126636B1 (en) | 1994-06-24 | 1994-06-24 | Fine patterning method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940014571A KR0126636B1 (en) | 1994-06-24 | 1994-06-24 | Fine patterning method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960002589A KR960002589A (en) | 1996-01-26 |
| KR0126636B1 true KR0126636B1 (en) | 1998-04-02 |
Family
ID=19386197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940014571A KR0126636B1 (en) | 1994-06-24 | 1994-06-24 | Fine patterning method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0126636B1 (en) |
-
1994
- 1994-06-24 KR KR1019940014571A patent/KR0126636B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960002589A (en) | 1996-01-26 |
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