KR0135889Y1 - 복합형 반도체 패키지 - Google Patents

복합형 반도체 패키지 Download PDF

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KR0135889Y1
KR0135889Y1 KR2019950042010U KR19950042010U KR0135889Y1 KR 0135889 Y1 KR0135889 Y1 KR 0135889Y1 KR 2019950042010 U KR2019950042010 U KR 2019950042010U KR 19950042010 U KR19950042010 U KR 19950042010U KR 0135889 Y1 KR0135889 Y1 KR 0135889Y1
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chip
semiconductor package
package
lead
type semiconductor
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KR970047004U (ko
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오재성
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김주용
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 고안은 반도체 패키지에 관한 것으로, 특히 칩온 리드형 반도체 패키지와 리드온 칩형 반도체 패키지를 복합시켜 반도체 패키지를 제작한 것으로, 패키지의 집적도를 높일 수 있고, 비메모리 분야에서도 각기 다른 특성의 칩을 한 패키지에 내장할 수 있도록 한 것을 특징으로 하는 복합형 반도체 패키지에 관한 것이다.

Description

복합형 반도체 패키지
제1도(a)는 일반적인 칩온 리드형 반도체 패키지의 단면도.
(b)는 일반적인 리드온 칩형 반도체 패키지의 단면도.
제2도(a)는 본 고안 반도체용 패키지의 단면도.
(b)는 본 고안 반도체용 패키지의 요부 평면도이다.
* 도면의 주요부분에 대한 부호의 설명
10 : 리드프레임 11,12 : 칩
13,14 : 접착용 테이프 15,16 : 와이어
본 고안은 반도체 패키지에 관한 것으로, 특히 칩온 리드형 반도체 패키지와 리드온 칩형 반도체 패키지를 복합시켜 한개의 리드프레임에 반도체 패키지를 제작한 것으로, 패키지의 집적도를 높일 수 있고, 비메모리 분야에서도 각기 다른 특성의 칩을 한 패키지에 내장할 수 있도록 한 것을 특징으로 하는 복합형 반도체 패키지에 관한 것이다.
현재 양산되는 반도체 패키지 제품들은, 제1도(a)와 같이 칩(1)을 다이패들(4)상에 고정시키고, 칩(1)과 내부리드(2)는 와이어본딩(3)으로 연결되며, 칩(1)과 다이패들(4)은 접착제(6)로 부착한후 에폭시 수지로(5) 몰딩작업으로 제작하는 칩온 리드 반도체 패키지와; 제1도(b)와 같이, 버스바(7) 및 내부리드(2)를 갖는 리드프레임 저면에 테이프(8)를 사용하여 칩(1)을 어테치하고, 와이어(3)로 와이어 본딩하며 몰딩수지(5)로 패키지를 몰딩시켜 제작하는 리드온 칩 패키지들이 주종을 이루고 있다.
그러나 상기와 같이 구성하는 일반적인 반도체 패키지들은 리드프레임과 칩 및 와이어등의 두께가 어느정도 유지되어야 하기 때문에 칩의 고집적화 될수록 한계점에 도달할 수 밖에 없는 문제점이 있다.
즉, 현재 패키지는 패키지의 두께를 계속 낮추어 가는 방향으로 진행되고 있는데, 패키지를 구성하는 주요부품들을 실장한 상태에서 패키지의 두께를 낮추는데는 기술적으로 많은 어려움이 뒤따르고 있는 실정이다.
본 고안은 이러한 문제를 해결코자 하는 것으로, 상기 칩온 리드형 패키지와 리드온 칩형 패키지를 한개의 패키지에 복합시켜 칩의 집적도를 높이도록함을 특징으로 한다.
즉, 한개의 리드프레임 상하에 접착용 테이프를 부착하고, 리드프레임 상하면에 칩을 탑제하며, 상부는 칩온 리드형으로 형성하고, 하부는 리드온 칩형으로 형성토록 한 것이다.
이하 도면을 참조로 상세히 설명하면 다음과 같다.
제2도(a,b)는 본 고안의 단면도 및 평면도로써, 한개의 리드프레임(10) 상하에 접착용 테이프(13,14)를 부착하고, 리드프레임(10) 상하면에 칩(11,12)을 탑제하며, 리드프레임(10)의 공통지점에 와이어 본딩(15,16)이 이루어지도록 구성한다.
상기와 같이 구성하는 본 고안은 리드프레임(10)의 상하면에 접착용 테이프(13,14)를 부착한후 칩(11,12)를 탑제시킨다. 이때 탑부분의 테이프(13)와 칩(11)은 보텀부분의 테이프(14)와 칩(12)에 비해 작은 크기로 실장토록 하며, 리드프레임(10)의 일정한 지점에 동시에 와이어(15,16)로 본딩한다.
상기에서 보텀부분에 비해 탑부분을 작은 크기의 칩(11)으로 실장하는 이유는 보텀부분의 와이어본딩 작업을 순조롭게 진행시키기 위해서이다.
즉, 리드프레임(10)의 동일한 지점으로 와이어 본딩하기 위해서는 보텀부위의 본딩패드(11-1)가 일정한 길이만큼 외부로 돌출되어 있어야 가능하기 때문이다.
상기의 공정이 끝나면 몰딩수지(17)로 패키지를 몰딩시키고 포밍하여 패키지를 완성한다.
상술한 바와같이 본 고안은 칩온 리드형 반도체 패키지와 리드온 칩형 반도체 패키지를 복합시켜 반도체 패키지를 제작함으로, 패키지의 집적도를 높일 수 있고, 비메모리 분야에서도 각기 다른 특성의 칩을 한 패키지에 내장할 수 있다.

Claims (1)

  1. 반도체 패키지에 있어서, 한개의 리드프레임 상하에 접착용 테이프를 부착하고, 리드프레임 상하면에 칩을 탑제하며, 리드프레임의 공통지점에 와이어 본딩이 이루어지도록 구성함을 특징으로 하는 복합형 반도체 패키지.
KR2019950042010U 1995-12-15 1995-12-15 복합형 반도체 패키지 KR0135889Y1 (ko)

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KR0135889Y1 true KR0135889Y1 (ko) 1999-02-18

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