KR0128227Y1 - Ceramic leadless chip carrier - Google Patents

Ceramic leadless chip carrier

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Publication number
KR0128227Y1
KR0128227Y1 KR2019950008121U KR19950008121U KR0128227Y1 KR 0128227 Y1 KR0128227 Y1 KR 0128227Y1 KR 2019950008121 U KR2019950008121 U KR 2019950008121U KR 19950008121 U KR19950008121 U KR 19950008121U KR 0128227 Y1 KR0128227 Y1 KR 0128227Y1
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KR
South Korea
Prior art keywords
package
semiconductor
pattern
metal
cavity
Prior art date
Application number
KR2019950008121U
Other languages
Korean (ko)
Other versions
KR960035636U (en
Inventor
안영준
Original Assignee
문정환
엘지반도체주식회사
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Application filed by 문정환, 엘지반도체주식회사 filed Critical 문정환
Priority to KR2019950008121U priority Critical patent/KR0128227Y1/en
Publication of KR960035636U publication Critical patent/KR960035636U/en
Application granted granted Critical
Publication of KR0128227Y1 publication Critical patent/KR0128227Y1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Connecting Device With Holders (AREA)

Abstract

본 고안은 반도체 시엘시시(Ceramic Leadless Chip Carrier) 패키지에 관한 것으로, 패키지 몸체(10)의 상부 캐비티(11)에 부착된 반도체 칩(12)과, 상기 칩(12)과 금속 와이어(14)에 의해 전기적으로 연결되어 있으며 몸체(10)의 내부에 내설된 패턴 금속(13)과, 상기 캐비티(11)의 상부에 부착되어 있는 캡(15)로 구성되어 있는 반도체 시엘시시 패키지에 있어서, 상기 몸체(10)의 내부에 내설된 패턴 금속(13)이 상, 하 2열로 다수개 형성되도록 하고, 그 패턴 금속(13)에 연장되도록 몸체(10)의 외측 상, 하면에 상, 하측 접속부(13a)(13a')를 형성되도록 하여, 외부와 전기적인 접속을 2배로 할 수 있도록 구성함으로써, 다핀 구조를 갖도록 한 것이다.The present invention relates to a semiconductor leadless chip carrier package, the semiconductor chip 12 attached to the upper cavity 11 of the package body 10, the chip 12 and the metal wire 14 In the semiconductor Cielsi package is composed of a pattern metal 13, which is electrically connected by the internal structure of the body 10, and a cap 15 attached to the upper portion of the cavity 11, Upper and lower connecting portions on the outer and upper surfaces of the body 10 to form a plurality of pattern metal 13 in the interior of the body 10 in upper and lower two rows, and extends to the pattern metal 13. By forming (13a) and (13a ') so as to double the electrical connection with the outside, it has a multi-pin structure.

Description

반도체 시엘시시(CLCC) 패키지Semiconductor Ciel Packages (CLCC)

제1도는 종래 반도체 시엘시시 패키지의 구성을 보인 평면도.1 is a plan view showing a configuration of a conventional semiconductor Csi package.

제2도는 제1도의 A-A'선 단면도.2 is a cross-sectional view taken along the line AA ′ of FIG. 1.

제3도는 종래 반도체 시엘시시 패키지가 소켓에 삽입되어 있는 상태를 보인 단면도.3 is a cross-sectional view showing a state in which a conventional semiconductor CSI package is inserted into a socket.

제4도는 종래 반도체 시엘시시 패키지가 피시비(PCB)에 부착되어 있는 상태를 보인 단면도.4 is a cross-sectional view showing a state in which a conventional semiconductor CSI package is attached to a PCB.

제5도는 본 고안 반도체 시엘시시 패키지의 구성을 보인 평면도.5 is a plan view showing the configuration of the semiconductor CSI package of the present invention.

제6도는 제5도의 A-A'선 단면도.6 is a cross-sectional view taken along the line AA ′ of FIG. 5.

제7도는 본 고안 반도체 시엘시시 패키지의 구성을 보인 저면도.Figure 7 is a bottom view showing the configuration of the inventive semiconductor Cielsi package.

제8도는 제5도의 B방향에서 본 상태도.8 is a state diagram seen in the direction B of FIG.

제9도는 본 고안 반도체 시엘시시 패키지가 소켓에 삽입되어 있는 상태를 보인 단면도.9 is a cross-sectional view showing a state in which the inventive semiconductor Cielsi package is inserted into a socket.

제10도는 본 고안 반도체 시엘시시 패키지가 피시비(PCB)에 부착되어 있는 상태를 보인 단면도.FIG. 10 is a cross-sectional view showing a state in which a semiconductor CLS package of the present invention is attached to a PCB.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 몸체 11 : 칩10 body 11 chip

12 : 캐비티 13 : 패턴 금속12: cavity 13: pattern metal

14 : 금속 와이어 15 : 캡14 metal wire 15 cap

13a,13a' : 상, 하측 접속부13a, 13a ': upper and lower connection

본 고안은 반도체 시엘시시(Ceramic Leadless Chip Carrier) 패키지에 관한 것으로, 특히 패키지의 내부에 형성되어 있는 패턴 금속의 수를 기존 보다 2배가 되도록 하여 다핀 구조를 갖을 수 있도록 한 반도체 시엘시시 패키지에 관한 것이다.The present invention relates to a semiconductor leadless chip carrier package, and more particularly, to a semiconductor cielci package in which the number of pattern metals formed inside the package is doubled than before. It is about.

제1도는 종래 시엘시시 패키지의 구성을 보인 평면도이고, 제2도는 제1도의 A-A' 선 단면도로서, 이에 도시된 바와 같이, 종래의 패키지는 패키지 몸체(1)의 내부 중간부에 형성된 캐비티(2)에 반도체 칩(3)이 부착되어 있고, 이 반도체 칩(3)은 몸체(1)의 내부에 내설되어 있는 패턴 금속(4)과 금속 와이어(5)에 의해 전기적으로 연결되어 있으며, 상기 캐비티(2)의 상부는 캡(6)이 부착되어 있는 구조로 되어 있다.FIG. 1 is a plan view showing the structure of a conventional CLS package, and FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1. As shown in the drawing, a conventional package includes a cavity formed in an inner middle portion of a package body 1. The semiconductor chip 3 is attached to 2), and the semiconductor chip 3 is electrically connected by the patterned metal 4 and the metal wire 5 which are inherent in the body 1, The upper part of the cavity 2 has a structure in which the cap 6 is attached.

또한, 몸체(1)의 외부 4면에는 상, 하로 결합홈(1a)이 형성되어 있으며, 그 결합홈(1a)을 따라 몸체(1)의 내부에 내설되어 있는 패턴 금속(4)이 연장 형성되어 있는 것이다.In addition, the outer four surfaces of the body (1) is formed with a coupling groove (1a) up and down, the pattern metal (4) which is built in the interior of the body (1) along the coupling groove (1a) is formed to extend It is.

상기와 같이 구성되어 있는 종래의 시엘시시 패키지는 제3도와 같이 패키지 몸체(1)를 소켓에 결합하여 몸체(1)의 외부 결합홈(1a)에 형성되어 있는 패턴 금속(4)과 소켓의 소켓 리드를 접속하여 사용하는 것이다.Conventional Cielsi package is configured as described above is to connect the package body 1 to the socket as shown in Figure 3 of the pattern metal (4) and the socket formed in the outer coupling groove (1a) of the body (1) It is used by connecting socket lead.

또한, 제4도와 같이 피시비(PCB)의 패턴에 시엘시시 패키지를 납땜으로 실장하여 사용하는 것이다.In addition, as shown in FIG. 4, the CLS package is soldered to and used in the PCB pattern.

그러나, 상기와 같은 종래의 시엘시시 패키지는 최근의 반도체 추세인 다핀구조를 갖지 못하는 문제점이 있었다.However, the conventional Csi package as described above has a problem that does not have a multi-pin structure which is a recent semiconductor trend.

이를 감안하여 안출한 본 고안의 목적은 시엘시시 패키지 몸체의 내부에 내설되는 패턴 금속을 상, 하 2열로 내설하여 기존의 시엘시시 패키지보다 2배의 패턴 금속을 갖을 수 있는 반도체 시엘시시 패키지를 제공함에 있다.In view of this, the object of the present invention is to fabricate a semiconductor metal in the Cielsi package body in two columns, the upper and lower columns of the semiconductor Cielsi can have twice the pattern metal than the existing Cielsi package In providing the package.

상기와 같은 본 고안의 목적을 달성하기 위하여 패키지 몸체의 상부 캐비티에 반도체 칩이 부착되어 있고, 그 반도체 칩의 상부가 캡으로 복개되어 있는 반도체 시엘시시 패키지에 있어서, 상기 몸체의 내부에 패턴 금속을 상, 하 2열로 수개 형성하고, 그 상, 하의 패턴 금속에 연장되어 패키지의 상, 하측에 위치되는 피시비에 접속되도록 각각 패키지 몸체의 외측 상, 하면에 노출되도록 상, 하측 접속부를 형성하며, 상기 패턴 금속과 반도체 칩을 금속 와이어로 연결하여 외부와 전기적으로 연결되도록 구성한 것을 특징으로 하는 반도체 시엘시시 패키지가 제공된다.In order to achieve the object of the present invention as described above, a semiconductor chip is attached to the upper cavity of the package body and the upper portion of the semiconductor chip is covered with a cap, the pattern metal inside the body A plurality of upper and lower rows are formed, and upper and lower connection portions are formed so as to be exposed to the upper and lower surfaces of the package body so as to extend to upper and lower pattern metals and to be connected to the PCB placed on the upper and lower sides of the package. Provided is a semiconductor CLS package, wherein the pattern metal and the semiconductor chip are connected by a metal wire to be electrically connected to the outside.

이하, 상기와 같은 본 고안의 시엘시시 패키지를 첨부된 도면에 의거하여 보다 상세히 설명한다.Hereinafter, the Cielsi package of the present invention as described above will be described in more detail based on the accompanying drawings.

제5도 내지 제8도는 본 고안에 의한 반도체 시엘시시 패키지를 보인 것으로서, 이에 도시된 바와같이, 본 고안은 몸체(10)의 내부 중간부에 형성된 캐비티(11)에 반도체 칩(12)이 부착되어 있고, 이 반도체 칩(12)은 몸체(10)의 내부에 내설되어 있는 패턴 금속(13)과 금속 와이어(14)에 의해 전기적으로 연결되어 있으며, 상기 캐비티(11)의 상부에는 캡(15)이 부착되어 있는 구조는 종래와 동일하다.5 to 8 illustrate a semiconductor CSI package according to the present invention, as shown in the present invention, the present invention shows that the semiconductor chip 12 is formed in a cavity 11 formed in an inner middle portion of the body 10. The semiconductor chip 12 is electrically connected by a pattern metal 13 and a metal wire 14 in the interior of the body 10, and a cap () is formed on the upper portion of the cavity 11. The structure to which 15) is attached is the same as before.

여기서 본 고안은 몸체(10)의 내부에 설치되는 패턴 금속(13)을 상, 하 2열로 다수개 내설하여 기존의 시엘시시 패키지 보다 2배의 패턴 금속(13) 갖을 수 있도록 하였을 뿐만 아니라, 그 상, 하의 패턴 금속(13)에 연장되어 패키지의 상, 하측에 위치되는 피시비에 접속되도록 각각 패키지 몸체(10)의 외측 상, 하면에 노출되도록 상,하측 접속부(13a)(13a')를 형성하여서 구성된다.Here, the present invention not only has a plurality of pattern metals 13 installed inside the body 10 in two rows in the upper and lower rows, so that the pattern metals 13 can be twice as large as the conventional CLS package. The upper and lower connecting portions 13a and 13a 'extend to the upper and lower pattern metals 13 so as to be exposed to the upper and lower surfaces of the package body 10 so as to be connected to the PCBs positioned on the upper and lower sides of the package. It is formed by forming.

또한, 몸체(10)의 외부 4면에는 상, 하로 결합홈(10a)이 형성되어 있으며, 그 결합홈(10a)을 따라 몸체(10)의 내부에 내설되어 있는 패턴 금속(13)이 연장 형성되어 있는 것이다.In addition, the outer four surfaces of the body 10 is formed with a coupling groove 10a up and down, and the pattern metal 13 formed in the interior of the body 10 is extended along the coupling groove 10a. It is.

상기와 같이 구성되는 본 고안의 시엘시시 패키지는 제9도와 같이 패키지 몸체(10)를 소켓 리드가 상, 하 2열로 설치되어 있는 소켓에 결합하여 패키지 몸체(10)의 결합홈(10a)에 형성되어 있는 패턴 금속(13)과 소켓 리드가 전기적으로 접속하도록 하여 사용하며, 제10도와 같이 상, 하의 피시비(PCB) 패턴에 본 고안 시엘시시 패키지의 상, 하 패턴 금속(13)의 상, 하측 접속부(13a)(13a')를 납땜으로 연결하여 사용하는 것이다.Cielsi package of the present invention is configured as described above in the coupling groove 10a of the package body 10 by coupling the package body 10 to the socket, the socket lead is installed in two rows, up and down as shown in FIG. The formed pattern metal 13 and the socket lead are electrically connected to each other, and the upper and lower pattern metals 13 of the present invention CSI package are formed on the upper and lower PCB patterns as shown in FIG. Lower connection portions 13a and 13a 'are connected by soldering.

이상에서 상세히 설명한 바와 같이 본 고안의 반도체 시엘시시 패키지는 패키지 몸체에 내설되는 패턴 금속을 상, 하 2열로 다수개 형성하고, 외부와의 전기적 접속을 2배가 되도록 함으로써, 다핀구조를 갖을 수 있도록 한 것이다.As described in detail above, the semiconductor CSI package of the present invention is formed by forming a plurality of pattern metals in the package body in two rows, up and down, and doubling the electrical connection to the outside, so as to have a multi-pin structure. It is.

Claims (1)

패키지 몸체의 상부 캐비티에 반도체 칩이 부착되어 있고, 그 반도체 칩의 상부가 캡으로 복개되어 있는 반도체 시엘시시 패키지에 있어서, 상기 몸체의 내부에 패턴 금속을 상, 하 2열로 수개 형성하고, 그 상, 하의 패턴 금속에 연장되어 패키지의 상, 하측에 위치되는 피시비에 접속되도록 각각 패키지 몸체의 외측 상, 하면에 노출되도록 상, 하측 접속부를 형성하며, 상기 패턴 금속과 반도체 칩을 금속 와이어로 연결하여 외부와 전기적으로 연결되도록 구성한 것을 특징으로 하는 반도체 시엘시시 패키지.In a semiconductor CSI package in which a semiconductor chip is attached to an upper cavity of a package body and the upper part of the semiconductor chip is covered with a cap, a plurality of pattern metals are formed in the upper and lower two rows inside the body. Upper and lower connecting portions are formed to extend to upper and lower pattern metals and to be exposed to upper and lower surfaces of the package body, respectively, so as to be connected to the PCBs positioned on the upper and lower sides of the package. The semiconductor Cielsi package, characterized in that configured to be electrically connected to the outside.
KR2019950008121U 1995-04-20 1995-04-20 Ceramic leadless chip carrier KR0128227Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019950008121U KR0128227Y1 (en) 1995-04-20 1995-04-20 Ceramic leadless chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019950008121U KR0128227Y1 (en) 1995-04-20 1995-04-20 Ceramic leadless chip carrier

Publications (2)

Publication Number Publication Date
KR960035636U KR960035636U (en) 1996-11-21
KR0128227Y1 true KR0128227Y1 (en) 1998-10-15

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KR2019950008121U KR0128227Y1 (en) 1995-04-20 1995-04-20 Ceramic leadless chip carrier

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