KR0128064B1 - Function array sequencing for vlsi test system - Google Patents

Abstract

None.

Description

Functional Array Sequencing System and VLSI Inspection Methods for VLSI Inspection Systems

1 is a functional system diagram of a tester of the prior art.

2 is a schematic diagram illustrating one embodiment of the present invention.

3 shows a hardware setup addressing procedure.

4 illustrates a hardware addressing procedure.

5 is a diagram illustrating a state of using a quad digital to analog converter for hardware control.

FIG. 6 is a diagram illustrating a test function separation state using three setup address registers. FIG.

7 shows a memory configuration

* Explanation of symbols for main parts of the drawings

11,21: CPU 13,24: Program Memory

R1-Rn: Programming Register F1-Fn: Hardware Function Generator

22: Function Array Sequencing (FAS) Controller T1-Tn: Test Setup Memory

TM1-TMn: Test Setup Register

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a system for inspecting VLSI (ultra-scale semiconductor integrated circuit) devices. Prior art checkers typically include a processor that loads the hardware programming for each device to be checked into a programming register. Each time a device is tested, the programming register of each device under test must be reprogrammed. Reprogramming is time consuming, reducing the device inspection rate as it is inspected. During typical VLSI test program execution, the device under test actually runs (tested) only for 10-50% of the test time. The remaining 90-50% of the test time represents the test program execution overhead associated with the tester (the time to load the test program into the programming register). Most of the overhead corresponds to the time required to program inspection system hardware functions related to the various inspection condition setups typically required to inspect VLSI devices.

During the inspection process, it is common to perform various types of DC parametric inspection as well as to change parameters such as supply voltage, signal switching reference level and operating frequency. Each inspection condition change and each parametric inspection type may require significant reprogramming of the inspector hardware. The amount of inspector hardware required to inspect a device is basically proportional to the pin count of the device. Therefore, in VLSI devices, a large number of pins typically increases the amount of testers that are programmed, causing the problem of test program execution overhead.

In conventional testers, hardware functions are programmed through a register loaded by a hardware controller. These registers are typically addressed as if they were memory locations in the controller's address space. Each hardware function in the checker is assigned a specific address corresponding to a programming register. In order to initialize the tester for a particular test setup, each hardware register associated with the test must be written. Due to the limited data transfer bandwidth associated with the hardware controller and data bus, the transfer of test setup information to hardware registers represents a bottleneck at the time of execution of the test program.

The present invention replaces random access memory which acts as a hardware programming registerfile of the tester. When the test program is initially called, the memory is loaded with information corresponding to all the test setups required for the test program. That is, the test program information is stored in the bulk memory of the hardware controller, and this information is not transferred to the hardware register through the bottleneck during the test program execution. Is loaded into hardware memory. When the test program is executed, the hardware controller only needs to point to a specific test program address, thereby allowing all hardware functions to be programmed simultaneously. The present invention shows a technological advance over the prior art tester, in which the programming information must be communicated through the bottleneck every time the program is cycled as well as when the hardware configuration changes within the program. do.

The hardware controller must be able to select each hardware programming memory individually to initially load the setup information. This allows control of each function when the variables are used to program specific setup changes. In addition, the controller can collectively address the memory to achieve programming of the functional group simultaneously. The actual execution of the hardware programming memory can be modified to use a quad digital to analog converter device. The setup address bus can be divided into functional groups to extend the flexibility of the inspection system. For example, pin electronics (donation and AC test interfaces with the device under test), DC test subsystem, and relay matrix (which define the signal path between the pin and function under test) are 3 Can be separated and controlled into two setup address registers. This allows the system to change one group of inspector functions without affecting other groups, thus maintaining a setup or function set. If a particular test setup involves only one pin electronics change, there is no need to waste additional setup locations within the DC subsystem or relay matrix.

The present invention can greatly simplify the inspection procedure from the prior art tester, shorten the test program execution time, and increase the tester yield. Hereinafter, with reference to the accompanying drawings will be described in detail the technical advances, objects and advantages of the present invention. 1 is a functional system diagram of a tester of the prior art. The tester includes a CPU 11, a program memory 13 and a data / address bus 12 which connects the CPU 11 to a number of programming registers R1 to Rn. Each programming register R1... Rn is connected to a respective hardware function generator F1-Fn. The test setup to be used is in the program memory 13. When each check is performed, the CPU 11 programs each program register R1 to Rn via the data / address bus 12. Since each program register R1 to Rn must be programmed separately each time a particular check is made, a significant amount of time is spent programming each hardware function generator to perform a check that can last only a few microns. This limits the number of devices that can be checked within a certain time. 2 shows a preferred embodiment of the present invention.

The basic system includes a CPU 21, a program memory 24, a function array sequencing (FAS) controller 22 which is a smart direct memory access (DMA) controller, a plurality of test setup memories (T1 to T). Tn) and a plurality of hardware function generators F1 to Fn. The function of the FAS controller may, in some embodiments, be performed by the CPU depending on the performance characteristics of the CPU. Before the first test execution or when the test program is initially loaded, the CPU 21 checks the test program stored in the program memory 24 (or in the network to which the test system is connected) and checks the test setup memory registers TMI to TMn. Load inside). Each test memory TMn includes a plurality of positions T1 to Tn, which each store function values related to different test programs or procedures.

After the corresponding function value is loaded at each test memory location, a simple operation is performed in which the hardware controller (or CPU) 22 addresses the test memory point TMn suitable for programming the associated hardware function generator Fn. . This procedure is shown in FIG. 3 shows a number of test setup memories, a hardware function generator Fn and an address bus line 23.

When the system is initially programmed, the function values associated with each test program or procedure are loaded into the corresponding positions T1 to Tn in the test setup memories TM1 to TMn. The program is indexed into each register and loads the relevant function values of all the check procedures. Once this is accomplished, the system is programmed for all the tests performed on each device under test, with each test being executed in rapid succession without having to interrupt the test for the next test or load of the procedure. A possible implementation procedure of sequencing through the inspection process and enabling each inspection setup register is shown in FIG.

The FAS controller must be able to collectively address the memory locations T1 to Tn of each check memory TMn to achieve the programming of the functional group simultaneously. This is accomplished by the FAS controller sending over the bus 23 the FAS address of each test setup data to be used for a particular test. The address register specifies a register Tn of each test memory TMn that contains the program / procedure to be used for the next test.

The address of the register is contained within the most significant bit of the data word sent by the FAS controller. The address decode register receives the least significant bit of the data word and, with all line selections, is properly NAND so that a properly addressed register Tn can program the corresponding hardware function generator.

The addressing of each memory can change the parameters and / or programming of each hardware function generator. Since most checker hardware function generators (Fn) are programmed using a digital-to-analog converter (DAC), it is convenient and cost effective to use a quad DAC package. An execution state using the quad DAC is shown in FIG. Each DAC supplies four pins of the device under test for specific functionality.

5 shows the state of use of a quad DAC for converting digitally encoded information into an analog signal used in a hard pan function generator. The FAS address bus is used to determine which program / procedure setup will be used. Channel and function selection is quickly established to program many function groups simultaneously. The register TM may be, for example, 16K x 12 random access memory (RAM).

Therefore, three 64K RAMs can be used for all 256 setups, and 16 functions / setups can be used for four pins of the device under test. The RAM is addressed to determine which program / procedure is selected and sent to the DAC. Channel selection selects one of the four channels (A-D) corresponding to the four pins of the device under test.

As described, the function selection may select one or more DACs out of the 16 DACs. By using the selection circuit shown in FIG. 5, each appropriate hardware function can be easily programmed. 6 shows that functional groups can be partitioned to extend the flexibility of the system. The address bus is divided so that one branch of the bus addresses the pin electronics, functionality, and AC interface to the device under test.

The second branch of the address bus is interfaced with relay metrics that route the signal between the tester and the device under test, and the third branch is interfaced with the DC inspection subsystem. By using separate branches, the FAS system can change one group of inspector functions without affecting the other, thus preserving the setup or function set.

For example, if a particular test setup involves a change in pin electronics only, there is no need to waste additional setup locations in the DC subsystem or relay matrix. FIG. 7 shows the memory Tm of FIG. 6 in more detail.

Each memory (Tm) can contain up to 256 setups or 16 functions per pin. Each channel is connected to one input (A-D) of each DAC. The sixteen functions control the DAC as shown by function (DAC) selection (F1 through F16).

Claims (14)

A test apparatus for inspecting a large-scale semiconductor integrated circuit having a hardware function generator programmed through a register loaded by a hardware controller, each hardware function having a specific address corresponding to the program register, wherein the random access memory comprises: a random access memory; And a hardware function generator programmed simultaneously with addressing logic controlled by the hardware controller to program all hardware functions simultaneously by specifying a specific test setup address when the test is executed. An inspection system for inspecting ultra-scale semiconductor integrated circuits, wherein inspection setup programming is loaded for all inspections to be performed prior to the inspection execution. 2. The inspection system of claim 1, comprising address logic circuitry within the hardware controller to address hardware programming memory locations collectively, in groups, and individually. 2. The inspection system of claim 1 wherein programming of all hardware functions is performed separately. 2. The inspection system of claim 1, wherein programming of all of the hardware function generators is performed individually as the inspection proceeds to allow for repeated changes of some functions. 2. The inspection system of claim 1, wherein the setup address bus is divided into functional groups. 2. The functional group of claim 1, wherein the functional group includes a pin function and an AC test interface with the device under test, a DC test subsystem, and a relay matrix forming a signal path between the tester and the device under test. An inspection system for inspecting superscale semiconductor integrated circuits. 2. The superscale semiconductor of claim 1, wherein the inspection system includes three setup address registers that enable the hardware controller to change one group of inspection functions without affecting another group. Inspection system for inspecting integrated circuits. In a test system for testing a large scale semiconductor integrated circuit having a hardware function generator programmed through a register loaded by a hardware controller, each hardware function having a specific address corresponding to that programming register, the random access memory. A hardware function generator programmed to simulate a desired hardware function and an addressing logic bus divided into functional groups controlled by the hardware controller to specify a specific test setup address when a test is executed. By which common test setup programming for some tests to be performed before the program test execution is loaded simultaneously with all other memories. Inspection system. 9. The inspection system of claim 8 wherein the hardware controller comprises addressing logic circuitry for individually selecting each hardware programming memory to initially load setup information. 10. The inspection system of claim 8, further comprising a setup address bus divided into functional groups. 11. The apparatus of claim 10, wherein the functional group comprises a functional and AC test interface with the device under test, a DC test subsystem, and a relay matrix to form a signal path between the tester and the device under test. An inspection system for inspecting ultra-scale semiconductor integrated circuits. A method for testing large scale semiconductor integrated circuits in which hardware function generators are programmed through a register loaded by a hardware controller, each hardware function being assigned a specific address corresponding to the program register, wherein the test is performed prior to performing the test. Loading information corresponding to all test setups required for the program into a program register, and specifying a specific test setup address in each program register to program the hardware function and change the test function as the test proceeds. Ultra-scale semiconductor integrated circuit inspection method which specifies that thing. 13. The method of claim 12, wherein specifying a particular test setup address comprises specifying a register of a functional group to change a program of only selected registers. 14. The invitation system of claim 13, wherein the functional group comprises a function with the device under test and an AC test interface, a DC test subsystem and a relay matrix for routing the signal between the tester and the device under test. Scale semiconductor integrated circuit inspection method.

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