KR0126655B1 - Metalizing method of semiconductor device - Google Patents

Metalizing method of semiconductor device

Info

Publication number
KR0126655B1
KR0126655B1 KR1019930026084A KR930026084A KR0126655B1 KR 0126655 B1 KR0126655 B1 KR 0126655B1 KR 1019930026084 A KR1019930026084 A KR 1019930026084A KR 930026084 A KR930026084 A KR 930026084A KR 0126655 B1 KR0126655 B1 KR 0126655B1
Authority
KR
South Korea
Prior art keywords
layer
pattern
forming
metal
metal layer
Prior art date
Application number
KR1019930026084A
Other languages
Korean (ko)
Inventor
김진웅
박찬동
Original Assignee
김주용
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업주식회사 filed Critical 김주용
Priority to KR1019930026084A priority Critical patent/KR0126655B1/en
Application granted granted Critical
Publication of KR0126655B1 publication Critical patent/KR0126655B1/en

Links

Abstract

A forming method of metal wires is provided to improve an yield. The method comprises the steps of: depositing a metal layer(2) on a silicon substrate(1); removing a native oxide formed on the metal layer(2); sequentially depositing a lower photo-resist(3), a middle layer(4) and an upper photo-resist; forming an upper PR pattern(5) by exposing and developing; forming a middle-layer pattern(11) using the upper PR pattern(5) as a mask; forming a lower PR pattern(9) using the middle-layer pattern(11) as a mask and forming a metal wire(20) by etching the exposed metal layer(2) using the lower PR pattern(9) as a mask. Thereby, it is possible to easily form metal wires having a high yield.

Description

금속배선 형성방법Metal wiring formation method

제 1a 도 내지 제 1c 도는 종래기술에 의한 금속배선 형성공정을 도시한 단면도.1A to 1C are cross-sectional views showing a metal wiring forming process according to the prior art.

제 2a 도 및 제 2c 도는 본 발명에 의한 금속배선 형성공정을 도시한 단면도.2A and 2C are cross-sectional views showing a metal wiring forming process according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 절연막 2,17 : 금속층1 Insulation film 2,17 Metal layer

3 : 하층감광막 4 : 중간층3: lower photosensitive film 4: intermediate layer

5 : 상층감광막패턴 7 : 자연산화막5: upper photoresist pattern 7: natural oxide film

9,13 : 하층감광막패턴 11,19 : 중간층패턴9,13: lower layer photoresist pattern 11,19: middle layer pattern

15 : 리프팅된 하층감광막패턴 20 : 금속배선15: Lifted lower layer photoresist pattern 20: Metal wiring

본 발명은 금속배선 형성방법에 관한 것으로, 금속 3층 감광막(TLR : tri-layer-resist, 이하에서 TLR이라 함)공정에 의한 패턴 형성시, 금속층 상부의 자연산화막을 제거하기 위하여 불소를 포함한 용액처리 및 용매처리를 한 다음, HMDS 처리를 한 후에 TLR을 증착함으로써, 하층감광막의 리프팅(lifting)을 억제하여 소자의 수율을 향상시키는 기술이다.The present invention relates to a method for forming metal wiring, a solution containing fluorine to remove the natural oxide film on the upper metal layer during the pattern formation by a metal tri-layer photoresist (TLR: tri-layer-resist, hereinafter referred to as TLR) process After the treatment and the solvent treatment, and after the HMDS treatment, the TLR is deposited to suppress the lifting of the lower photoresist film, thereby improving the yield of the device.

종래기술은 산화막 상부에 금속층을 형성한 다음, 금속배선을 형성할때, 금속층 상부에 HMDS(Hexa-Methyl-Di-Silazane, 이하에서 HMDS라 함)처리후에 TLR 공정에 사용되는 하층감광막을 도포하고 중간층과 상층감광막을 도포한 다음, 리소그래피 기술로써 상층감광막패턴을 형성한다. 그리고, TLR 식각공정을 실시한다. 상기 식각공정에서 100:1와 bOE(buffer oxide ecthant, 이하에서 bOE라 함)를 사용하여 중간층을 제거한다. 이때, 금속층의 최상부에 있는 자연산화막이 리프팅되어 소자의 수율을 저하시킨다.In the prior art, a metal layer is formed on an oxide film, and then a metal layer is formed, and then a lower photoresist film used in a TLR process is applied to the metal layer after HMDS (Hxa-Methyl-Di-Silazane). After applying the intermediate layer and the upper photosensitive film, an upper photosensitive film pattern is formed by lithography. Then, a TLR etching process is performed. In the etching process, the intermediate layer is removed using 100: 1 and bOE (buffer oxide ecthant, hereinafter referred to as bOE). At this time, the native oxide film on the top of the metal layer is lifted to lower the yield of the device.

상기 종래기술에 의하여 발생하는 문제점을 제 la 도 내지 제 lc 도를 참고로 하여 상세히 설명하기로 한다.Problems caused by the prior art will be described in detail with reference to FIGS. La to lc.

제 1a 도는 실리콘기판(10)의 상부에 절연막(1), 예를들어 산화막을 형성하고, 그 상부에 금속층(2), 예를들어 Ti, TiN, al 합금 및 코팅반사막 TiN이 적충된 구조로 형성하고 그 상부에 하층감광막(3), 중간층(4) 및 상층감광막(도시안됨)으로 형성되는 TLR을 도포하고 노광 및 현상공정으로 상층감광막패턴(5)을 형성한 것을 도시한 단면도이다. 여기서, 주시할 점은 금속층(2)의 최상부에는 TiN이 공기중에서 산화하여 자연산화막(7)이 성장된 상태에서 하층감광막(3)을 도포하는데 이 자연산화막(7)은 공기중의 산소와 반응하는 시간에 따라 그 성장두께가 다르다. 상기 하층감광막(3)이 점착성을 향상시키기 위하여 상기 금속층(2)을 HMDS 처리를 한 다음, 하층감광막(3)을 도포한다. 이때, 상기 중간층(4)으로는 에스오지(SOG:spin on glass, 이하에서 SOG이라 함)를 사용한다.FIG. 1A is a structure in which an insulating film 1, for example, an oxide film is formed on the silicon substrate 10, and a metal layer 2, for example, Ti, TiN, an al alloy, and a coating reflecting film TiN is deposited thereon. It is a cross-sectional view showing that a TLR formed of a lower photosensitive film 3, an intermediate layer 4, and an upper photosensitive film (not shown) is applied to the upper layer, and the upper photosensitive film pattern 5 is formed by an exposure and development process. Here, it should be noted that the upper photosensitive layer 3 is applied to the top of the metal layer 2 in a state where TiN is oxidized in the air and the natural oxide film 7 is grown. The natural oxide film 7 reacts with oxygen in the air. The growth thickness depends on the time it takes. In order to improve the adhesion of the lower layer photosensitive film 3, the metal layer 2 is subjected to an HMDS treatment, and then the lower layer photosensitive film 3 is applied. In this case, as the intermediate layer 4, SG (SOG: spin on glass, hereinafter referred to as SOG) is used.

제 1b 도는 상기 TLR을 상층감광막패턴(5)을 마스크로 하여 중간층(4)을 식각하여 중간층패턴(11)을 형성한 후, 상기 중간층패턴(11)을 마스크로 하여 노출된 하층감광막(3)을 식각하여 하층감광막패턴(9)을 형성한 것을 도시한 단면도이다.1B illustrates the intermediate layer pattern 11 formed by etching the intermediate layer 4 using the upper layer photoresist pattern 5 as the mask, and then exposing the lower layer photosensitive layer 3 exposed using the intermediate layer pattern 11 as a mask. Is a cross-sectional view showing that the lower photosensitive film pattern 9 is formed by etching.

제 1c 도는 상기 중간층패턴(11)을 습식방법으로 제거한 것을 도시한 단면도로서, 100:1의 BOE를 사용하여 블규칙적으로 중간층패턴(11)을 제거할때, 노출된 자연산화막(7)과 동시에 제거되는데 자연산화막(7)이 두껍게 성장한 곳에서는 자연산화막(7)이 움푹파이게 되어 하부감광막패턴(9)의 리프팅현상이 일어난다.FIG. 1C is a cross-sectional view showing the removal of the intermediate layer pattern 11 by a wet method. Simultaneously removing the intermediate layer pattern 11 using a BOE of 100: 1 simultaneously with the exposed natural oxide film 7 Where the natural oxide film 7 is thickly removed, the natural oxide film 7 is pitted and the lower photoresist pattern 9 is lifted.

상기 공정후, 노출된 금속층(2)을 식각하여 금속배선을 형성한다. 이때, 하부감광막패턴(9)이 리프팅된 곳에서는 금속배선이 형성되지 않게 된다.After the process, the exposed metal layer 2 is etched to form metal wiring. At this time, the metal wiring is not formed where the lower photoresist pattern 9 is lifted.

따라서, 본 발명에서는 금속표면의 상부에 중간층패턴을 제거할때 자연산화막이 함께 제거되기 때문에 상기 문제가 발생되므로 하층감광막의 도포전에 자연산화막을 제거하는 표면처리를 실시하여 중간층 제거시 발생하는 하층감광막의 리프팅을 해결하여 금속배선을 형성함으로써, 높은 수율을 갖는 소자를 생산하는데 그 목적이 있다.Therefore, in the present invention, since the above problem occurs because the natural oxide film is removed together when the intermediate layer pattern is removed on the upper surface of the metal surface, the lower photosensitive film generated when the intermediate layer is removed by performing a surface treatment to remove the natural oxide film before applying the lower photosensitive film. The purpose is to produce a device having a high yield by forming a metal wiring by solving the lifting of.

이상의 목적을 달성하기 위한 본 발명의 특징은, 실리콘기판의 상부에 금속층을 증착하는 공정과, 금속층이 대기층에 노출될때 성장된 자연산화막을 제거하는 공정과, 상기 금속층 상부에 하층감광막, 중간층 및 상층감광막을 적층하고, 노광 및 현상공정으로 상층감광막패턴을 형성하는 공정과, 상기 상층감광막패턴을 마스크로 하여 중간층패턴을 형성하고 그 하부의 노출된 하층감광막을 식각하여 하층감광막패턴을 형성하는 공정과, 상기 하층감광막패턴을 마스크로 하여 노출된 금속층을 식각하여 금속배선을 형성하는 공정을 포함하는데 있다.Features of the present invention for achieving the above object, the process of depositing a metal layer on top of the silicon substrate, the process of removing the natural oxide film grown when the metal layer is exposed to the atmospheric layer, and the lower photosensitive film, the intermediate layer and the upper layer on the metal layer Forming a lower layer photoresist pattern by laminating a photoresist layer, forming an upper photoresist pattern by an exposure and development process, forming an intermediate layer pattern using the upper photoresist pattern as a mask, and etching the exposed lower layer photoresist underneath; And etching the exposed metal layer using the lower photoresist pattern as a mask to form metal wiring.

이하, 첨부된 도면을 참고로 하여 본 발명에 의한 금속배선 형성방법을 상세히 설명하기로 한다.Hereinafter, a metal wiring forming method according to the present invention will be described in detail with reference to the accompanying drawings.

제 2a 도 및 제 2c 도는 본 발명의 실시예에 의한 금속배선 형성공정을 도시한 단면도이다.2A and 2C are cross-sectional views showing a metal wiring forming process according to an embodiment of the present invention.

제 2a 도는 실리콘기판(10)의 상부에 산화막(1) 및 금속층(2)을 증착하고, 그 상부에 하층감광막(3), 중간층(4) 및 상층감광막으로 형성되는 TLR을 도포하고 노광 및 현상공정으로 상층감광막패턴(5)을 형성한 것을 도시한 단면도이다. 이때, 금속층(2)은 Ti, TiN, al 합금 및 코팅반사막으로 TiN이 적층된 것이며, 상기 금속층(2) 상부에 하층감광막(3)을 도포하기전에 불소(F)를 포함하고 100:1의 BOE를 이용하여 습식방법으로 금속층(2)의 상부에 있는 코팅반사막 상부에 대기중에서 성장하여 존재하는 자연산화막(도시안됨)을 제거하고, 남아있는 자연산화막이나 이물질, 예를들어 ACT-690C 또는 ACT-CMI 용매에서 세척하여 제거한 다음, 하층감광막의 점착성을 높이기 위하여 HMDS 처리를 한 다음, 하층감광막(3)을 도포한 것이다. 이때, 용매처리시 공정은 80℃(20') 및 50℃(5')의 두 단계에서 실시한다. 그리고, 상기 중간층(4)으로는 SOG를 사용한다.In FIG. 2A, an oxide film 1 and a metal layer 2 are deposited on the silicon substrate 10, and a TLR formed of a lower photosensitive film 3, an intermediate layer 4, and an upper photosensitive film is coated on the upper surface of the silicon substrate 10, and exposed and developed. It is sectional drawing which shows that the upper photosensitive film pattern 5 was formed by the process. At this time, the metal layer (2) is a Ti, TiN, al alloy and TiN is laminated with a coating reflection film, and includes fluorine (F) before applying the lower photosensitive film (3) on the metal layer (2) of 100: 1 BOE is used to remove the remaining natural oxide film (not shown) by growing in the air on top of the coating reflective film on the upper part of the metal layer 2 by a wet method, and remaining natural oxide film or foreign material such as ACT-690C or ACT It is removed by washing with a CMI solvent, and then treated with HMDS to increase the adhesion of the lower layer photoresist film, and then the lower layer photoresist film 3 is applied. At this time, the solvent treatment process is carried out in two steps of 80 ℃ (20 ') and 50 ℃ (5'). As the intermediate layer 4, SOG is used.

제 2b 도는 상기 상층감광막패턴(5)을 마스크로 하여 중간층패턴(11)을 형성하고, 상기 중간층패턴(11)을 마스크로 하여 하층감광막(3)을 건식식각하여 하층감광막패턴(9)을 형성한 것을 도시한 단면도이다.In FIG. 2B, an intermediate layer pattern 11 is formed using the upper photoresist pattern 5 as a mask, and a lower layer photoresist pattern 3 is formed by dry etching the lower photosensitive layer 3 using the intermediate layer pattern 11 as a mask. It is sectional drawing which showed.

제 2c 도는 상기 중간층패턴(1l)을 습식방법으로 제거하고 하층감광막패턴(9)을 마스크로 하여 노출된 금속층(2)을 식각하여 금속배선(20)을 형성한 다음, 상부의 하층감광막패턴(9)을 제거한 것을 도시한 단면도이다.In FIG. 2C, the intermediate layer pattern 1l is removed by a wet method, and the exposed metal layer 2 is etched using the lower layer photoresist pattern 9 as a mask to form a metal wiring 20, and then the upper layer photoresist pattern ( 9 is a cross-sectional view showing the removal.

상기한 본 발명에 의하면, 하층감광막패턴의 리프팅을 발생시키는 요인이 되는 금속층 상부에 성장된 자연산화막을 TLR을 도포하기 전에 제거함으로써, 하층감광막패턴의 리프팅 발생을 방지하여 정상적인 패턴을 형성할 수 있다.According to the present invention described above, by removing the natural oxide film grown on the upper metal layer, which causes the lifting of the lower layer photoresist pattern, before applying the TLR, it is possible to prevent the occurrence of the lower layer photoresist pattern to form a normal pattern. .

Claims (2)

금속배선 형성방법에 있어서, 실리콘기판의 상부에 금속층을 증착하는 공정과, 금속층이 대기중에 노출될때 성장된 자연산화막을 BOE 용액에서 제거한 다음, 세정 공정을 이물질을 제거하는 공정과, 상기 금속층의 표면을 HMDS 처리를 한다음, 상기 금속층 상부에 하층감광막, 중간층 및 상층감광막을 적층하고, 노광 및 현상공정으로 상층감광막패턴을 형성하는 공정과, 상기 상층감광막패턴을 마스크로 하여 중간층패턴을 형성하고 그 하부의 노출된 하층감광막을 식각하여 하층감광막패턴을 형성하는 공정과, 상기 하층감광막패턴을 마스크로 하여 노출된 금속층을 식각하여 금속배선을 형성하는 공정을 포함하는 금속배선 형성방법.A method of forming a metal wiring, comprising: depositing a metal layer on an upper surface of a silicon substrate; removing a natural oxide film grown when the metal layer is exposed to air; and removing a foreign substance from a BOE solution; After the HMDS treatment, a lower photoresist film, an intermediate layer, and an upper photoresist film are laminated on the metal layer, and an upper photoresist film pattern is formed by an exposure and development process, and an intermediate layer pattern is formed by using the upper photoresist film pattern as a mask. And forming a lower layer photoresist pattern by etching the exposed lower layer photoresist film below, and forming a metal wiring by etching the exposed metal layer using the lower layer photoresist pattern as a mask. 제 1 항에 있어서, 상기 금속층은 Ti, TiN, Al 및 TiN으로 적층된 구조를 갖는 것을 특징으로 하는 금속배선 형성방법.The method of claim 1, wherein the metal layer has a stacked structure of Ti, TiN, Al, and TiN.
KR1019930026084A 1993-12-01 1993-12-01 Metalizing method of semiconductor device KR0126655B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930026084A KR0126655B1 (en) 1993-12-01 1993-12-01 Metalizing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930026084A KR0126655B1 (en) 1993-12-01 1993-12-01 Metalizing method of semiconductor device

Publications (1)

Publication Number Publication Date
KR0126655B1 true KR0126655B1 (en) 1998-04-02

Family

ID=19369588

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930026084A KR0126655B1 (en) 1993-12-01 1993-12-01 Metalizing method of semiconductor device

Country Status (1)

Country Link
KR (1) KR0126655B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100443521B1 (en) * 1996-10-30 2004-10-14 주식회사 하이닉스반도체 Method for manufacturing a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100443521B1 (en) * 1996-10-30 2004-10-14 주식회사 하이닉스반도체 Method for manufacturing a semiconductor device

Similar Documents

Publication Publication Date Title
JPH0345895B2 (en)
US6251804B1 (en) Method for enhancing adhesion of photo-resist to silicon nitride surfaces
KR0126655B1 (en) Metalizing method of semiconductor device
US5930647A (en) Methods of forming field oxide and active area regions on a semiconductive substrate
US6150215A (en) Avoiding abnormal capacitor formation by an offline edge-bead rinsing (EBR)
KR100197538B1 (en) Forming method for metal wiring in semiconductor device
KR930008845B1 (en) Device for seprating method of semiconductor apparatus
JPS594027A (en) Manufacture of semiconductor device
KR900001058B1 (en) Formation method of electrode patern by lift-off
KR0165759B1 (en) Method of forming metal pattern of mos transistor
KR960014056B1 (en) Pattern forming method of potosensitive film
KR0147488B1 (en) Method for forming contact hole
KR100370121B1 (en) Method for simplifying processes in semiconductor device
KR19990011634A (en) Pattern Forming Method Using Anti-Reflection Film of Semiconductor Device
CN117233889A (en) Method for forming silicon optical device
KR960008563B1 (en) Fine contact hall forming method of semiconductor using double spacer
KR0166028B1 (en) Manufacturing methd of semiconductor device
KR100333370B1 (en) Method for manufacturing semiconductor device
JPS59926A (en) Method for selective etching of aluminum film
KR100252759B1 (en) Method for forming semiconductor device
KR960008095B1 (en) Method of micro patterning using organo arc layer
KR960013140B1 (en) Fabricating method of semiconductor device
KR930008128B1 (en) Method for preparation of semiconductor
KR920002028B1 (en) Lift-off process using by-product
KR100235936B1 (en) Method for manufacturing resist pattern

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100920

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee