KR0120104B1 - Method for fabricating charge storage electrode of capacitor - Google Patents
Method for fabricating charge storage electrode of capacitorInfo
- Publication number
- KR0120104B1 KR0120104B1 KR1019930031161A KR930031161A KR0120104B1 KR 0120104 B1 KR0120104 B1 KR 0120104B1 KR 1019930031161 A KR1019930031161 A KR 1019930031161A KR 930031161 A KR930031161 A KR 930031161A KR 0120104 B1 KR0120104 B1 KR 0120104B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- charge storage
- storage electrode
- polysilicon
- oxide film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000003990 capacitor Substances 0.000 title claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 44
- 229920005591 polysilicon Polymers 0.000 claims abstract description 44
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 9
- 150000004767 nitrides Chemical class 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 3
- 229910017855 NH 4 F Inorganic materials 0.000 claims description 2
- 229910021642 ultra pure water Inorganic materials 0.000 claims description 2
- 239000012498 ultrapure water Substances 0.000 claims description 2
- 239000011259 mixed solution Substances 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000000243 solution Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
제1a도 내지 제1e도는 본 발명에 따른 캐패시터의 전하저장전극 형성방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1A to 1E are cross-sectional views of devices sequentially shown to explain a method of forming a charge storage electrode of a capacitor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 필드 산화막1: silicon substrate 2: field oxide film
3 : 게이트 산화막 4 : 게이트 전극3: gate oxide film 4: gate electrode
5 : 절연막 6 : 불순물 이온 주입 영역5 insulating film 6 impurity ion implantation region
7 : 스페이서 산화막 8 : 절화막7: spacer oxide film 8: cut film
9 : 제1폴리실리콘막 10 : 제1절연용 산화막9: first polysilicon film 10: first insulating oxide film
11 : 제2폴리실리콘막 12 : 평탄화된 산화막11: second polysilicon film 12: planarized oxide film
13 : 제3폴리실리콘막 14 : 제2절연용 산화막13: third polysilicon film 14: second insulating oxide film
15 : 감광막15 photosensitive film
본 발명은 캐패시터의 전하저장전극 형성방법에 관한 것으로, 특히 제1, 제2 및 제3폴리실시콘으로 전하저장전극을 형성하되, 제1폴리실리콘과 제2폴리실리콘은 전하저장전극 콘택 부위에서 접속되어 일정 간격 이격된 분지(branch)를 이루고, 제3폴리실리콘은 제2폴리실리콘의 측단부에서 수직으로 측벽을 이루도록 형성하여 제한된 면적하에서 유효 표면적을 증대시킬 수 있는 수직 구조 캐패시터의 전하저장전극을 형성하는 방법에 관한 것이다.The present invention relates to a method of forming a charge storage electrode of a capacitor, and in particular, the charge storage electrode is formed of the first, second and third polysilicon, wherein the first polysilicon and the second polysilicon are formed at the contact portion of the charge storage electrode. The third polysilicon is connected to form a branch spaced at regular intervals, and the third polysilicon is formed to form sidewalls vertically at the side ends of the second polysilicon, thereby increasing the effective surface area under a limited area charge storage electrode of the vertical capacitor. It relates to a method of forming a.
일반적으로 반도체 소자가 고집적화됨에 따라 셀 면적은 급격하게 축소되고, 셀 면적의 축소에도 불구하고 소자의 동작에 필요한 셀당 일정 용량 이상의 캐패시터 용량을 확보해야 한다.In general, as semiconductor devices are highly integrated, the cell area is drastically reduced, and despite the reduction in cell area, it is necessary to secure a capacitor capacity more than a predetermined capacity per cell required for the operation of the device.
이를 해결하기 위해서 여러 가지 3차원의 전하저장전극이 제시되고 있으며, 보다 유용한 구조 및 보다 단순화된 공정으로 전하저장전극을 형성하기 위해 계속 연구되고 있다.In order to solve this problem, various three-dimensional charge storage electrodes have been proposed and continue to be studied to form charge storage electrodes with more useful structures and simpler processes.
따라서, 본 발명은 반도체 소자의 고집적화에 적합하도록 제한된 면적하에서 유효 표면적을 극대화할 수 있는 수직 구조의 캐패시터의 전하저장전극을 형성하는 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of forming a charge storage electrode of a capacitor having a vertical structure capable of maximizing an effective surface area under a limited area suitable for high integration of a semiconductor device.
상술한 목적을 달성하기 위한 본 발명은 실리콘 기판 상에 필드 산화막, 게이트 산화막, 게이트 전극, 절연막, 불순물 이온 주입 영역 및 스페이서 산화막을 순차적으로 형성하여 트랜지스터를 구성하는 단계와, 전체 구조 상부에 질화막을 증착한 후 사진 식각 방법으로 상기 질화막의 선택된 영역을 제거하는 단계와, 전체 구조 상부에 도핑된 전하저장전극용 제1폴리실리콘막 및 제1절연용 산화막을 순차적으로 형성하는 단계와, 전하저장전극 콘택 마스크를 이용하여 상기 제1절연용 산화막 및 제1폴리실리콘막의 선택된 영역을 식각하여 실리콘 기판의 불순물 이온 주입 영역과 연통되는 콘택홀을 형성하는 단계와, 상기 콘택홀을 통해 불순물 이온 주입 영역과 접촉되도록 도핑된 전하저장전극용 제2폴리실리콘막을 형성하는 단계와, 전체 구조 상부에 평탄화된 산화막을 두껍게 형성하고 전하저장전극 마스크보다 작은 크기의 마스크를 이용하여 전하저장전극 영역 내부에 상기 평탄화된 산화막을 패턴화하는 단계와, 전체 구조 상부에 도핑된 전하저장전극용 제3폴리실리콘막 및 제2절연용 산화막을 형성하는 단계와, 전체 구조 상부에 감광막을 도포한 후 중심 부분에 창이 열린 전하저장전극 마스크를 이용하여 감광막을 패턴화하는 단계와, 상기 패턴화된 감광막을 이용한 건식 식각 공정으로 노출된 부위의 제2절연용 산화막, 제3폴리실리콘막 및 제2폴리실리콘막을 순차적으로 제거하는 단계와, 상기 패턴화된 감광막을 소정의 오븐에서 플로우시킨 후 상기 플로우된 감광막을 이용한 건식 식각 공정으로 제2절연용 산화막, 평탄화된 산화막 및 제1절연용 산화막을 완전히 제거하여, 제1, 제2 및 제3폴리실리콘막으로된 수직 구조의 전하저장전극을 형성하는 단계로 이루어진 것을 특징으로 한다.According to the present invention, a transistor is formed by sequentially forming a field oxide film, a gate oxide film, a gate electrode, an insulating film, an impurity ion implantation region, and a spacer oxide film on a silicon substrate, and forming a nitride film over the entire structure. Removing the selected region of the nitride layer by a photolithography method after the deposition; sequentially forming a doped first polysilicon layer for the charge storage electrode and an oxide layer for the first insulation; Etching a selected region of the first insulating oxide film and the first polysilicon film using a contact mask to form a contact hole in communication with the impurity ion implantation region of the silicon substrate, and forming an impurity ion implantation region through the contact hole; Forming a second polysilicon film for the charge storage electrode doped to be in contact with the upper portion of the entire structure; Forming a planarized oxide film on the substrate and patterning the planarized oxide film inside the charge storage electrode region using a mask having a size smaller than that of the charge storage electrode mask, and a third poly doped charge charge electrode on the entire structure. Forming a silicon film and a second insulating oxide film, applying a photoresist film over the entire structure, and patterning the photoresist film using a charge storage electrode mask with a window open in a central portion thereof, and using the patterned photoresist film. Sequentially removing the second insulating oxide film, the third polysilicon film, and the second polysilicon film of the exposed portions by the dry etching process; and flowing the patterned photoresist film in a predetermined oven, and then flowing the flow The dry etching process was used to completely remove the second insulating oxide film, the planarized oxide film, and the first insulating oxide film. Forming a charge storage electrode of the vertical structure made of a third polysilicon film.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1a도에 도시된 바와 같이 실리콘 기판(1) 상에 필드 산화막(2), 게이트 산화막(3), 게이트 전극(4), 절연막(5), 불순물 이온 주입 영역(6) 및 스페이서 산화막(7)을 순차적으로 형성하여 트랜지스터를 구성한다. 전체 구조 상부에 질화막(8)을 증착한 후 사진 식각 방법으로 질화막(8)의 선택된 영역을 제거한다.As shown in FIG. 1A, the field oxide film 2, the gate oxide film 3, the gate electrode 4, the insulating film 5, the impurity ion implantation region 6, and the spacer oxide film 7 are formed on the silicon substrate 1. ) Are sequentially formed to form a transistor. After the nitride film 8 is deposited over the entire structure, the selected region of the nitride film 8 is removed by a photolithography method.
제1b도에 도시된 바와 같이 전체 구조 상부에 도핑된 전하저장전극용 제1폴리실리콘막(9) 및 제1절연용 산화막(10)을 순차적으로 형성한다. 전하저장전극 콘택 마스크를 이용하여 제1절연용 산화막(10) 및 제1폴리실리콘막(9)의 선택된 영역을 식각하여 실리콘 기판(1)의 불순물 이온 주입 영역(6)과 연통되는 콘택홀을 형성한다. 형성된 콘택홀을 통해 불순물 이온 주입 영역(6)과 접촉되도록 도핑된 전하저장전극용 제2폴리실리콘막(11)을 형성한다.As shown in FIG. 1B, the first polysilicon film 9 for the charge storage electrode and the first insulating oxide film 10 are sequentially formed on the entire structure. The contact hole communicating with the impurity ion implantation region 6 of the silicon substrate 1 is etched by etching selected regions of the first insulating oxide film 10 and the first polysilicon film 9 using the charge storage electrode contact mask. Form. The second polysilicon film 11 for the charge storage electrode is doped to be in contact with the impurity ion implantation region 6 through the formed contact hole.
제1c도에 도시된 바와 같이 전체 구조 상부에 평탄화된 산화막(12)을 두껍게 형성하고, 전하저장전극 마스크보다 작은 크기의 마스크를 이용하여 전하저장전극 영역 내부에 평탄화된 산화막(12)을 패턴화한다. 전체 구조 상부에 도핑된 전하저장전극용 제3폴리실리콘막(13)을 형성한 후 그 상부에 제2절연용 산화막(14)을 형성한다. 전체 구조 상부에 감광막(15)을 도포한 후 중심 부분에 창(window)이 열린 전하저장전극 마스크를 이용하여 감광막(15)을 패턴화한다. 패턴화된 감광막(15)을 이용한 건식 식각 공정으로 노출된 제2절연용 산화막(14), 제3폴리실리콘막(13) 및 제2폴리실리콘막(11)을 순차적으로 제거한다.As shown in FIG. 1C, the planarized oxide film 12 is thickly formed on the entire structure, and the planarized oxide film 12 is patterned inside the charge storage electrode region using a mask having a size smaller than that of the charge storage electrode mask. do. After forming the doped third polysilicon film 13 for the charge storage electrode on the entire structure, the second insulating oxide film 14 is formed on the doped third polysilicon film 13. After the photoresist film 15 is applied over the entire structure, the photoresist film 15 is patterned by using a charge storage electrode mask having a window open at the center portion. The second insulating oxide film 14, the third polysilicon film 13, and the second polysilicon film 11 exposed by the dry etching process using the patterned photosensitive film 15 are sequentially removed.
제1d도에 도시된 바와 같이 패턴화된 감광막(15)을 소정의 오븐에서 약 130∼200℃ 온도로 가열하여 감광막(15)을 플로우(flow)시킨다. 플로우된 감광막(15)을 이용한 건식 식각 공정으로 제1절연용 산화막(10) 및 제1폴리실리콘막(9)을 식각한다. 이때, 질화막(8)은 식각 정지층으로 작용한다.As shown in FIG. 1D, the patterned photosensitive film 15 is heated to a temperature of about 130 to 200 ° C. in a predetermined oven to flow the photosensitive film 15. The first insulating oxide film 10 and the first polysilicon film 9 are etched by a dry etching process using the flow photosensitive film 15. At this time, the nitride film 8 serves as an etch stop layer.
제1e도는 플로우된 감광막(15)을 제거한 후 습식 식각 공정으로 제2절연용 산화막(14), 평탄화된 산화막(12) 및 제1절연용 산화막(10)을 완전히 제거하여 제1, 제2 및 제3폴리실리콘막(9,11,13)으로된 수직 구조의 전하저장전극을 형성한 상태의 단면도이다.In FIG. 1E, the second photoresist oxide film 14, the planarized oxide film 12, and the first insulation oxide film 10 are completely removed by the wet etching process after the flow of the photosensitive film 15 is removed. A cross-sectional view of a state in which charge storage electrodes having a vertical structure made of third polysilicon films 9, 11, and 13 are formed.
상기한 본 발명에서 감광막의 플로우 상태에 따라 하부의 전하저장전극(제1폴리실리콘막)과 상부의 전하저장전극(제2 및 제3폴리실리콘막)의 폭의 차이가 결정되며, 통상적으로 하부의 전하저장전극의 폭이 크다. 그리고 감광막을 플로우할 때 Deep-UV를 사용할 수 있다. 또한 습식 식각 공정시 사용되는 용액은 HF와 초순수(DI)가 소정 비율로 혼합된 식각 용액 또는 HF와 NH4F가 소정 비율로 혼합된 식각 용액을 사용한다.In the present invention, the difference between the width of the lower charge storage electrode (first polysilicon film) and the upper charge storage electrode (second and third polysilicon film) is determined according to the flow state of the photosensitive film. The width of the charge storage electrode is large. And deep-UV can be used to flow the photoresist. In addition, the solution used in the wet etching process may use an etching solution in which HF and ultrapure water (DI) are mixed at a predetermined ratio, or an etching solution in which HF and NH 4 F are mixed at a predetermined ratio.
상술한 바와 같이 본 발명은 제한된 면적하에서 유효 표면적을 극대화시킨 전하저장전극을 형성함으로써 충분한 캐패시터의 용량을 확보할 수 있어 반도체 소자의 고집적화에 기여할 수 있다.As described above, the present invention can secure a sufficient capacitor capacity by forming a charge storage electrode maximizing an effective surface area under a limited area, thereby contributing to high integration of semiconductor devices.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930031161A KR0120104B1 (en) | 1993-12-30 | 1993-12-30 | Method for fabricating charge storage electrode of capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930031161A KR0120104B1 (en) | 1993-12-30 | 1993-12-30 | Method for fabricating charge storage electrode of capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950021580A KR950021580A (en) | 1995-07-26 |
| KR0120104B1 true KR0120104B1 (en) | 1997-10-27 |
Family
ID=19374173
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930031161A KR0120104B1 (en) | 1993-12-30 | 1993-12-30 | Method for fabricating charge storage electrode of capacitor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0120104B1 (en) |
-
1993
- 1993-12-30 KR KR1019930031161A patent/KR0120104B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR950021580A (en) | 1995-07-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5763312A (en) | Method of fabricating LDD spacers in MOS devices with double spacers and device manufactured thereby | |
| KR950010078A (en) | Manufacturing Method of Semiconductor Memory Device | |
| JP3897934B2 (en) | Contact hole manufacturing method of semiconductor device | |
| KR100319283B1 (en) | Manufacturing method of semiconductor device | |
| KR0151196B1 (en) | Manufacture of semiconductor memory device | |
| KR20000021503A (en) | Method for manufacturing flash memory device | |
| KR0120104B1 (en) | Method for fabricating charge storage electrode of capacitor | |
| KR0119963B1 (en) | Fabricating method of charge storage electrode of capacitor | |
| KR100304946B1 (en) | Method for manufacturing semiconductor device | |
| KR0122752B1 (en) | Contact hole formation method of semiconductor element | |
| US5691221A (en) | Method for manufacturing semiconductor memory device having a stacked capacitor | |
| KR100218311B1 (en) | Element isolation structure of semiconductor device and method for manufacturing the same | |
| KR960006716B1 (en) | Semiconductor integrated circuit device fabrication process | |
| KR0119962B1 (en) | Fabricating method for capacitor of semiconductor device | |
| KR100252924B1 (en) | Method for forming contact of semiconductor device | |
| KR100250735B1 (en) | Method for fabricating a storage node of capacitor | |
| KR0166839B1 (en) | Semiconductor memory process | |
| KR100338090B1 (en) | Method for manufacturing semiconductor device | |
| KR100235895B1 (en) | Manufacturing method of capacitor charge storage electrode | |
| KR100250749B1 (en) | Method for fabricating a storage node of capacitor | |
| KR100370158B1 (en) | method for fabricating dual gate electrode in semiconductor device | |
| KR100256239B1 (en) | Method of forming storage node in semiconductor device | |
| KR930007756B1 (en) | Manufacturing method of self-alignment contact | |
| KR0136920B1 (en) | Manufacturing method of semiconductor device | |
| KR19980037651A (en) | Pad of semiconductor memory device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20050721 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |