JPWO2024128072A5 - - Google Patents

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JPWO2024128072A5
JPWO2024128072A5 JP2024564305A JP2024564305A JPWO2024128072A5 JP WO2024128072 A5 JPWO2024128072 A5 JP WO2024128072A5 JP 2024564305 A JP2024564305 A JP 2024564305A JP 2024564305 A JP2024564305 A JP 2024564305A JP WO2024128072 A5 JPWO2024128072 A5 JP WO2024128072A5
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Japan
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region
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gate wiring
semiconductor substrate
carbon
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JP2024564305A
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JPWO2024128072A1 (https=
JP7831641B2 (ja
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Priority claimed from PCT/JP2023/043492 external-priority patent/WO2024128072A1/ja
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Publication of JPWO2024128072A5 publication Critical patent/JPWO2024128072A5/ja
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JP2024564305A 2022-12-13 2023-12-05 半導体装置および半導体装置の製造方法 Active JP7831641B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2022198955 2022-12-13
JP2022198955 2022-12-13
PCT/JP2023/043492 WO2024128072A1 (ja) 2022-12-13 2023-12-05 半導体装置および半導体装置の製造方法

Publications (3)

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JPWO2024128072A1 JPWO2024128072A1 (https=) 2024-06-20
JPWO2024128072A5 true JPWO2024128072A5 (https=) 2025-03-10
JP7831641B2 JP7831641B2 (ja) 2026-03-17

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JP2024564305A Active JP7831641B2 (ja) 2022-12-13 2023-12-05 半導体装置および半導体装置の製造方法

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US (1) US20250126878A1 (https=)
JP (1) JP7831641B2 (https=)
CN (1) CN119452751A (https=)
DE (1) DE112023002207T5 (https=)
WO (1) WO2024128072A1 (https=)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9252292B2 (en) 2013-09-16 2016-02-02 Infineon Technologies Ag Semiconductor device and a method for forming a semiconductor device
DE102014116666B4 (de) 2014-11-14 2022-04-21 Infineon Technologies Ag Ein Verfahren zum Bilden eines Halbleiterbauelements
WO2016204227A1 (ja) * 2015-06-17 2016-12-22 富士電機株式会社 半導体装置および半導体装置の製造方法
DE112019001738B4 (de) * 2018-11-16 2024-10-10 Fuji Electric Co., Ltd. Halbleitervorrichtung und herstellungsverfahren
JP7215599B2 (ja) * 2019-12-18 2023-01-31 富士電機株式会社 半導体装置および半導体装置の製造方法
WO2022107727A1 (ja) * 2020-11-17 2022-05-27 富士電機株式会社 半導体装置

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