JPWO2023127725A1 - - Google Patents

Info

Publication number
JPWO2023127725A1
JPWO2023127725A1 JP2023570960A JP2023570960A JPWO2023127725A1 JP WO2023127725 A1 JPWO2023127725 A1 JP WO2023127725A1 JP 2023570960 A JP2023570960 A JP 2023570960A JP 2023570960 A JP2023570960 A JP 2023570960A JP WO2023127725 A1 JPWO2023127725 A1 JP WO2023127725A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2023570960A
Other languages
Japanese (ja)
Other versions
JP7784446B2 (ja
JPWO2023127725A5 (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2023127725A1 publication Critical patent/JPWO2023127725A1/ja
Publication of JPWO2023127725A5 publication Critical patent/JPWO2023127725A5/ja
Application granted granted Critical
Publication of JP7784446B2 publication Critical patent/JP7784446B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0271Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0058Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69Insulating materials thereof
    • H10W70/698Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06Thermal details
    • H05K2201/068Thermal details wherein the coefficient of thermal expansion is important
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10439Position of a single component
    • H05K2201/10462Flat component oriented parallel to the PCB surface
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)
JP2023570960A 2021-12-28 2022-12-23 スティフナ付き配線基板 Active JP7784446B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2021214992 2021-12-28
JP2021214992 2021-12-28
PCT/JP2022/047631 WO2023127725A1 (ja) 2021-12-28 2022-12-23 スティフナ付き配線基板

Publications (3)

Publication Number Publication Date
JPWO2023127725A1 true JPWO2023127725A1 (https=) 2023-07-06
JPWO2023127725A5 JPWO2023127725A5 (https=) 2024-09-03
JP7784446B2 JP7784446B2 (ja) 2025-12-11

Family

ID=86999232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023570960A Active JP7784446B2 (ja) 2021-12-28 2022-12-23 スティフナ付き配線基板

Country Status (6)

Country Link
US (1) US20250106984A1 (https=)
JP (1) JP7784446B2 (https=)
KR (1) KR20240108500A (https=)
CN (1) CN118414891A (https=)
TW (1) TWI854415B (https=)
WO (1) WO2023127725A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025243527A1 (ja) * 2024-05-24 2025-11-27 株式会社レゾナック 半導体装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001110926A (ja) * 1999-10-13 2001-04-20 Nec Corp フリップチップパッケージ
US6472762B1 (en) * 2001-08-31 2002-10-29 Lsi Logic Corporation Enhanced laminate flipchip package using a high CTE heatspreader
JP2005217003A (ja) * 2004-01-28 2005-08-11 Kyocera Corp 半導体素子収納用パッケージ
JP2005340596A (ja) * 2004-05-28 2005-12-08 Toppan Printing Co Ltd 複合スティフナー及びそれを取り付けた半導体装置用基板並びに半導体装置
WO2006087769A1 (ja) * 2005-02-15 2006-08-24 Fujitsu Limited パッケージ実装モジュールおよびパッケージ基板モジュール
JP2013026633A (ja) * 2011-07-14 2013-02-04 Toshiba Corp テレビジョン受像機、及び電子機器
US20200013732A1 (en) * 2018-02-26 2020-01-09 International Business Machines Corporation Laminated stiffener to control the warpage of electronic chip carriers

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004356569A (ja) * 2003-05-30 2004-12-16 Shinko Electric Ind Co Ltd 半導体装置用パッケージ
JP5284235B2 (ja) * 2008-09-29 2013-09-11 日本特殊陶業株式会社 半導体パッケージ
JP5350829B2 (ja) 2009-02-16 2013-11-27 日本特殊陶業株式会社 補強材付き配線基板の製造方法、補強材付き配線基板用の配線基板
MY209993A (en) 2019-02-04 2025-08-19 Sony Interactive Entertainment Inc Electronic apparatus, semiconductor device, insulating sheet, and method for manufacturing semiconductor device
JP7351107B2 (ja) 2019-06-06 2023-09-27 凸版印刷株式会社 配線基板及び配線基板の製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001110926A (ja) * 1999-10-13 2001-04-20 Nec Corp フリップチップパッケージ
US6472762B1 (en) * 2001-08-31 2002-10-29 Lsi Logic Corporation Enhanced laminate flipchip package using a high CTE heatspreader
JP2005217003A (ja) * 2004-01-28 2005-08-11 Kyocera Corp 半導体素子収納用パッケージ
JP2005340596A (ja) * 2004-05-28 2005-12-08 Toppan Printing Co Ltd 複合スティフナー及びそれを取り付けた半導体装置用基板並びに半導体装置
WO2006087769A1 (ja) * 2005-02-15 2006-08-24 Fujitsu Limited パッケージ実装モジュールおよびパッケージ基板モジュール
JP2013026633A (ja) * 2011-07-14 2013-02-04 Toshiba Corp テレビジョン受像機、及び電子機器
US20200013732A1 (en) * 2018-02-26 2020-01-09 International Business Machines Corporation Laminated stiffener to control the warpage of electronic chip carriers

Also Published As

Publication number Publication date
TW202335541A (zh) 2023-09-01
US20250106984A1 (en) 2025-03-27
JP7784446B2 (ja) 2025-12-11
WO2023127725A1 (ja) 2023-07-06
CN118414891A (zh) 2024-07-30
TWI854415B (zh) 2024-09-01
KR20240108500A (ko) 2024-07-09

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