JPWO2022030651A1 - - Google Patents

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Publication number
JPWO2022030651A1
JPWO2022030651A1 JP2022541771A JP2022541771A JPWO2022030651A1 JP WO2022030651 A1 JPWO2022030651 A1 JP WO2022030651A1 JP 2022541771 A JP2022541771 A JP 2022541771A JP 2022541771 A JP2022541771 A JP 2022541771A JP WO2022030651 A1 JPWO2022030651 A1 JP WO2022030651A1
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JP
Japan
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JP2022541771A
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Japanese (ja)
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JP7823290B2 (ja
JPWO2022030651A5 (https=
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/202—FETs having static field-induced regions, e.g. static-induction transistors [SIT] or permeable base transistors [PBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H10D30/635—Vertical IGFETs having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/875—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being semiconductor metal oxide, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
JP2022541771A 2020-08-07 2021-08-10 半導体素子および半導体装置 Active JP7823290B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2020134996 2020-08-07
JP2020134996 2020-08-07
PCT/JP2021/029578 WO2022030651A1 (ja) 2020-08-07 2021-08-10 半導体素子および半導体装置

Publications (3)

Publication Number Publication Date
JPWO2022030651A1 true JPWO2022030651A1 (https=) 2022-02-10
JPWO2022030651A5 JPWO2022030651A5 (https=) 2023-04-25
JP7823290B2 JP7823290B2 (ja) 2026-03-04

Family

ID=80117487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022541771A Active JP7823290B2 (ja) 2020-08-07 2021-08-10 半導体素子および半導体装置

Country Status (5)

Country Link
US (1) US20230290888A1 (https=)
JP (1) JP7823290B2 (https=)
CN (1) CN116114061A (https=)
TW (1) TWI907475B (https=)
WO (1) WO2022030651A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023144454A (ja) * 2022-03-28 2023-10-11 株式会社 日立パワーデバイス 半導体装置、半導体装置および電力変換装置
TWI878836B (zh) * 2022-04-27 2025-04-01 日商村田製作所股份有限公司 半導體裝置
US20250098199A1 (en) * 2023-09-20 2025-03-20 Wolfspeed, Inc. Corrosion Resistant Metal Structures for Wide Bandgap Semiconductor Devices

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007165690A (ja) * 2005-12-15 2007-06-28 Fuji Electric Holdings Co Ltd ヒートスプレッダと金属板との接合方法
JP2020107636A (ja) * 2018-12-26 2020-07-09 株式会社Flosfia 結晶性酸化物膜

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6259138B1 (en) * 1998-12-18 2001-07-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having multilayered gate electrode and impurity regions overlapping therewith
JP4645406B2 (ja) * 2005-10-13 2011-03-09 富士電機システムズ株式会社 半導体装置
JP3862737B1 (ja) * 2005-10-18 2006-12-27 栄樹 津島 クラッド材およびその製造方法、クラッド材の成型方法、クラッド材を用いた放熱基板
KR20120032258A (ko) * 2010-09-28 2012-04-05 삼성엘이디 주식회사 질화갈륨계 반도체소자 및 그 제조방법
CN103078040B (zh) * 2011-08-22 2016-12-21 Lg伊诺特有限公司 发光器件封装件和光装置
KR102290801B1 (ko) * 2013-06-21 2021-08-17 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작 방법
JP6330220B2 (ja) * 2014-03-27 2018-05-30 株式会社Ｊｏｌｅｄ 表示装置、電子機器および基板
EP2942804B1 (en) * 2014-05-08 2017-07-12 Flosfia Inc. Crystalline multilayer structure and semiconductor device
JP6652342B2 (ja) * 2014-08-08 2020-02-19 株式会社半導体エネルギー研究所 半導体装置
JP2017157661A (ja) * 2016-03-01 2017-09-07 出光興産株式会社 半導体装置
TWI831755B (zh) * 2017-11-15 2024-02-11 日商Ｆｌｏｓｆｉａ股份有限公司 ｐ型氧化物半導體膜及其形成方法
US10573585B2 (en) * 2018-03-19 2020-02-25 Texas Instruments Incorporated Power converter having a conductive clip
JP2020004861A (ja) * 2018-06-28 2020-01-09 堺ディスプレイプロダクト株式会社 薄膜トランジスタ、表示装置及び薄膜トランジスタの製造方法
JP7139862B2 (ja) * 2018-10-15 2022-09-21 株式会社デンソー 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007165690A (ja) * 2005-12-15 2007-06-28 Fuji Electric Holdings Co Ltd ヒートスプレッダと金属板との接合方法
JP2020107636A (ja) * 2018-12-26 2020-07-09 株式会社Flosfia 結晶性酸化物膜

Also Published As

Publication number Publication date
JP7823290B2 (ja) 2026-03-04
TWI907475B (zh) 2025-12-11
CN116114061A (zh) 2023-05-12
TW202211484A (zh) 2022-03-16
WO2022030651A1 (ja) 2022-02-10
US20230290888A1 (en) 2023-09-14

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