JPWO2021234500A1 - - Google Patents

Info

Publication number
JPWO2021234500A1
JPWO2021234500A1 JP2022523739A JP2022523739A JPWO2021234500A1 JP WO2021234500 A1 JPWO2021234500 A1 JP WO2021234500A1 JP 2022523739 A JP2022523739 A JP 2022523739A JP 2022523739 A JP2022523739 A JP 2022523739A JP WO2021234500 A1 JPWO2021234500 A1 JP WO2021234500A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2022523739A
Other languages
Japanese (ja)
Other versions
JPWO2021234500A5 (https=
JP7629914B2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2021234500A1 publication Critical patent/JPWO2021234500A1/ja
Publication of JPWO2021234500A5 publication Critical patent/JPWO2021234500A5/ja
Priority to JP2025016315A priority Critical patent/JP2025065240A/ja
Application granted granted Critical
Publication of JP7629914B2 publication Critical patent/JP7629914B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443Sum of products
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/048Activation functions
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065Analogue means
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/68Floating-gate IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/69IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802Special implementations
    • G06F2207/4818Threshold devices
    • G06F2207/4824Neural networks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Biophysics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Computing Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Physics (AREA)
  • Evolutionary Computation (AREA)
  • General Health & Medical Sciences (AREA)
  • Artificial Intelligence (AREA)
  • Computational Linguistics (AREA)
  • Molecular Biology (AREA)
  • Pure & Applied Mathematics (AREA)
  • Neurology (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Semiconductor Memories (AREA)
  • Complex Calculations (AREA)
  • Thin Film Transistor (AREA)
JP2022523739A 2020-05-22 2021-05-10 半導体装置 Active JP7629914B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2025016315A JP2025065240A (ja) 2020-05-22 2025-02-03 半導体装置

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2020089279 2020-05-22
JP2020089279 2020-05-22
PCT/IB2021/053933 WO2021234500A1 (ja) 2020-05-22 2021-05-10 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2025016315A Division JP2025065240A (ja) 2020-05-22 2025-02-03 半導体装置

Publications (3)

Publication Number Publication Date
JPWO2021234500A1 true JPWO2021234500A1 (https=) 2021-11-25
JPWO2021234500A5 JPWO2021234500A5 (https=) 2024-05-07
JP7629914B2 JP7629914B2 (ja) 2025-02-14

Family

ID=78708186

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2022523739A Active JP7629914B2 (ja) 2020-05-22 2021-05-10 半導体装置
JP2025016315A Pending JP2025065240A (ja) 2020-05-22 2025-02-03 半導体装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2025016315A Pending JP2025065240A (ja) 2020-05-22 2025-02-03 半導体装置

Country Status (3)

Country Link
US (1) US20230176818A1 (https=)
JP (2) JP7629914B2 (https=)
WO (1) WO2021234500A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI842855B (zh) * 2019-03-29 2024-05-21 日商半導體能源研究所股份有限公司 半導體裝置
US20230281434A1 (en) * 2022-03-07 2023-09-07 Everspin Technologies, Inc. Systems and methods for a storage bit in an artificial neural network

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11220358A (ja) * 1998-01-29 1999-08-10 Sanyo Electric Co Ltd デジタルフィルタ
JP2008251666A (ja) * 2007-03-29 2008-10-16 Tohoku Univ 三次元構造半導体装置
JP2019036280A (ja) * 2017-08-11 2019-03-07 株式会社半導体エネルギー研究所 グラフィックスプロセッシングユニット、コンピュータ、電子機器及び並列計算機
JPWO2018189620A1 (ja) * 2017-04-14 2020-02-27 株式会社半導体エネルギー研究所 ニューラルネットワーク回路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3693367B2 (ja) * 1994-07-28 2005-09-07 富士通株式会社 積和演算器
JP2003223433A (ja) * 2002-01-31 2003-08-08 Matsushita Electric Ind Co Ltd 直交変換方法、直交変換装置、符号化方法、符号化装置、逆直交変換方法、逆直交変換装置、復号化方法、及び、復号化装置
WO2014105154A1 (en) * 2012-12-24 2014-07-03 Intel Corporation Systems, methods, and computer program products for performing mathematical operations
JP6700712B2 (ja) * 2015-10-21 2020-05-27 キヤノン株式会社 畳み込み演算装置
FR3087907B1 (fr) * 2018-10-24 2021-08-06 St Microelectronics Grenoble 2 Microcontroleur destine a executer un traitement parametrable

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11220358A (ja) * 1998-01-29 1999-08-10 Sanyo Electric Co Ltd デジタルフィルタ
JP2008251666A (ja) * 2007-03-29 2008-10-16 Tohoku Univ 三次元構造半導体装置
JPWO2018189620A1 (ja) * 2017-04-14 2020-02-27 株式会社半導体エネルギー研究所 ニューラルネットワーク回路
JP2019036280A (ja) * 2017-08-11 2019-03-07 株式会社半導体エネルギー研究所 グラフィックスプロセッシングユニット、コンピュータ、電子機器及び並列計算機

Also Published As

Publication number Publication date
JP2025065240A (ja) 2025-04-17
US20230176818A1 (en) 2023-06-08
JP7629914B2 (ja) 2025-02-14
WO2021234500A1 (ja) 2021-11-25

Similar Documents

Publication Publication Date Title
BR112023005462A2 (https=)
BR112023012656A2 (https=)
BR112021014123A2 (https=)
BR112023009656A2 (https=)
BR112022009896A2 (https=)
BR112021017747A2 (https=)
BR112022024743A2 (https=)
BR112022026905A2 (https=)
JPWO2021234500A1 (https=)
BR112023011738A2 (https=)
BR112023004146A2 (https=)
BR112023006729A2 (https=)
BR102021018859A2 (https=)
BR112023016292A2 (https=)
BR112023011610A2 (https=)
BR112023011539A2 (https=)
BR112023008976A2 (https=)
BR102021020147A2 (https=)
BR102021018926A2 (https=)
BR102021018167A2 (https=)
BR102021017576A2 (https=)
BR102021016837A2 (https=)
BR102021016551A2 (https=)
BR102021016375A2 (https=)
BR102021016200A2 (https=)

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20240423

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20240423

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20250114

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20250203

R150 Certificate of patent or registration of utility model

Ref document number: 7629914

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150