JPWO2021149780A1 - - Google Patents
Info
- Publication number
- JPWO2021149780A1 JPWO2021149780A1 JP2021572801A JP2021572801A JPWO2021149780A1 JP WO2021149780 A1 JPWO2021149780 A1 JP WO2021149780A1 JP 2021572801 A JP2021572801 A JP 2021572801A JP 2021572801 A JP2021572801 A JP 2021572801A JP WO2021149780 A1 JPWO2021149780 A1 JP WO2021149780A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
- G06N3/065—Analogue means
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0035—Evaluating degradation, retention or wearout, e.g. by counting writing cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0045—Read using current through the cell
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Theoretical Computer Science (AREA)
- General Health & Medical Sciences (AREA)
- Biophysics (AREA)
- Neurology (AREA)
- Molecular Biology (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Evolutionary Computation (AREA)
- Data Mining & Analysis (AREA)
- Computing Systems (AREA)
- Computational Linguistics (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Artificial Intelligence (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2020010097 | 2020-01-24 | ||
| JP2020010097 | 2020-01-24 | ||
| PCT/JP2021/002106 WO2021149780A1 (ja) | 2020-01-24 | 2021-01-21 | 半導体装置及びその駆動方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2021149780A1 true JPWO2021149780A1 (https=) | 2021-07-29 |
| JPWO2021149780A5 JPWO2021149780A5 (https=) | 2022-09-14 |
| JP7618593B2 JP7618593B2 (ja) | 2025-01-21 |
Family
ID=76992548
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021572801A Active JP7618593B2 (ja) | 2020-01-24 | 2021-01-21 | 半導体装置及びその駆動方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US12417802B2 (https=) |
| JP (1) | JP7618593B2 (https=) |
| WO (1) | WO2021149780A1 (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11127458B1 (en) * | 2020-04-28 | 2021-09-21 | Applied Materials, Inc. | Non-uniform state spacing in multi-state memory element for low-power operation |
| JP2023030687A (ja) * | 2021-08-23 | 2023-03-08 | 日本放送協会 | ニューロモルフィック素子及びニューラルネットワーク素子 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001525606A (ja) * | 1997-12-04 | 2001-12-11 | アクソン テクノロジーズ コーポレイション | プログラム可能なサブサーフェス集合メタライゼーション構造およびその作製方法 |
| WO2013021649A1 (ja) * | 2011-08-10 | 2013-02-14 | パナソニック株式会社 | 抵抗変化型不揮発性記憶素子の書き込み方法 |
| JP2015018591A (ja) * | 2013-07-12 | 2015-01-29 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| JP2018521400A (ja) * | 2015-07-13 | 2018-08-02 | 株式会社デンソー | メモリスタ神経形態学的回路及びメモリスタ神経形態学的回路をトレーニングするための方法 |
| JP2018166194A (ja) * | 2017-03-28 | 2018-10-25 | 学校法人慶應義塾 | クロスバー構造および最適化問題解探索システム |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6180700B2 (ja) * | 2011-09-09 | 2017-08-16 | ルネサスエレクトロニクス株式会社 | 不揮発性半導体記憶装置及びその製造方法 |
| US10268949B2 (en) | 2016-03-21 | 2019-04-23 | International Business Machines Corporation | Artificial neuron apparatus |
| WO2018013247A2 (en) * | 2016-06-02 | 2018-01-18 | Brown University | Physics informed learning machine |
| JP6602279B2 (ja) * | 2016-09-20 | 2019-11-06 | 株式会社東芝 | メムキャパシタ、ニューロ素子およびニューラルネットワーク装置 |
| JP6914342B2 (ja) * | 2017-09-07 | 2021-08-04 | パナソニック株式会社 | 半導体記憶素子を用いたニューラルネットワーク演算回路 |
| CN111052153B (zh) | 2017-09-07 | 2023-07-14 | 松下控股株式会社 | 使用半导体存储元件的神经网络运算电路及动作方法 |
| JP6569755B1 (ja) * | 2018-03-06 | 2019-09-04 | Tdk株式会社 | ニューラルネットワーク装置、信号生成方法およびプログラム |
| US10482953B1 (en) * | 2018-08-14 | 2019-11-19 | Macronix International Co., Ltd. | Multi-state memory device and method for adjusting memory state characteristics of the same |
| US11250317B2 (en) * | 2018-09-27 | 2022-02-15 | Intel Corporation | Three-dimensional oscillator structure |
| US10784313B1 (en) * | 2019-06-11 | 2020-09-22 | International Business Machines Corporation | Integrated resistive processing unit to avoid abrupt set of RRAM and abrupt reset of PCM |
| US11600325B2 (en) * | 2020-12-02 | 2023-03-07 | International Business Machines Corporation | Non volatile resistive memory logic device |
| KR102648228B1 (ko) * | 2021-05-13 | 2024-03-14 | 포항공과대학교 산학협력단 | 신경망 소자 및 이를 구성하는 단위 시냅스 소자 |
-
2021
- 2021-01-21 WO PCT/JP2021/002106 patent/WO2021149780A1/ja not_active Ceased
- 2021-01-21 JP JP2021572801A patent/JP7618593B2/ja active Active
-
2022
- 2022-03-10 US US17/691,733 patent/US12417802B2/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001525606A (ja) * | 1997-12-04 | 2001-12-11 | アクソン テクノロジーズ コーポレイション | プログラム可能なサブサーフェス集合メタライゼーション構造およびその作製方法 |
| WO2013021649A1 (ja) * | 2011-08-10 | 2013-02-14 | パナソニック株式会社 | 抵抗変化型不揮発性記憶素子の書き込み方法 |
| JP2015018591A (ja) * | 2013-07-12 | 2015-01-29 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| JP2018521400A (ja) * | 2015-07-13 | 2018-08-02 | 株式会社デンソー | メモリスタ神経形態学的回路及びメモリスタ神経形態学的回路をトレーニングするための方法 |
| JP2018166194A (ja) * | 2017-03-28 | 2018-10-25 | 学校法人慶應義塾 | クロスバー構造および最適化問題解探索システム |
Also Published As
| Publication number | Publication date |
|---|---|
| JP7618593B2 (ja) | 2025-01-21 |
| WO2021149780A1 (ja) | 2021-07-29 |
| US20220198251A1 (en) | 2022-06-23 |
| US12417802B2 (en) | 2025-09-16 |
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