JPWO2021149113A5 - - Google Patents

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JPWO2021149113A5
JPWO2021149113A5 JP2021572135A JP2021572135A JPWO2021149113A5 JP WO2021149113 A5 JPWO2021149113 A5 JP WO2021149113A5 JP 2021572135 A JP2021572135 A JP 2021572135A JP 2021572135 A JP2021572135 A JP 2021572135A JP WO2021149113 A5 JPWO2021149113 A5 JP WO2021149113A5
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JP2021572135A
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JP7315872B2 (ja
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Priority claimed from PCT/JP2020/001742 external-priority patent/WO2021149113A1/ja
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JP2021572135A 2020-01-20 2020-01-20 プロセッサ、シミュレータプログラム、アセンブラプログラム、及び情報処理プログラム Active JP7315872B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/001742 WO2021149113A1 (ja) 2020-01-20 2020-01-20 プロセッサ、シミュレータプログラム、アセンブラプログラム、及び情報処理プログラム

Publications (3)

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JPWO2021149113A1 JPWO2021149113A1 (https=) 2021-07-29
JPWO2021149113A5 true JPWO2021149113A5 (https=) 2022-07-20
JP7315872B2 JP7315872B2 (ja) 2023-07-27

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JP2021572135A Active JP7315872B2 (ja) 2020-01-20 2020-01-20 プロセッサ、シミュレータプログラム、アセンブラプログラム、及び情報処理プログラム

Country Status (5)

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US (1) US20220300288A1 (https=)
EP (1) EP4095698A4 (https=)
JP (1) JP7315872B2 (https=)
CN (1) CN114830097A (https=)
WO (1) WO2021149113A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119105799A (zh) * 2023-06-08 2024-12-10 中兴通讯股份有限公司 代码分析方法、电子设备、计算机可读介质
CN118519817B (zh) * 2024-07-19 2024-10-29 浙江大华技术股份有限公司 一种算力cpu的异常数据获取方法、装置和计算机设备

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US4021655A (en) * 1976-03-30 1977-05-03 International Business Machines Corporation Oversized data detection hardware for data processors which store data at variable length destinations
JPS63278147A (ja) * 1987-05-11 1988-11-15 Fujitsu Ltd レジスタ誤使用防止制御方式
JPS6461828A (en) * 1987-09-01 1989-03-08 Nec Corp Register reference holding mechanism
US5132972A (en) * 1989-11-29 1992-07-21 Honeywell Bull Inc. Assembly language programming potential error detection scheme sensing apparent inconsistency with a previous operation
JPH0452734A (ja) * 1990-06-14 1992-02-20 Koufu Nippon Denki Kk 汎用レジスタ例外検出回路
JP2793396B2 (ja) 1991-11-15 1998-09-03 株式会社東芝 電子計算機の演算ステータス保持装置
JPH07262032A (ja) * 1994-03-17 1995-10-13 Fujitsu Ltd 情報処理装置
US6185671B1 (en) * 1998-03-31 2001-02-06 Intel Corporation Checking data type of operands specified by an instruction using attributes in a tagged array architecture
US6289445B2 (en) * 1998-07-21 2001-09-11 Lsi Logic Corporation Circuit and method for initiating exception routines using implicit exception checking
JP3123047B2 (ja) * 1998-10-02 2001-01-09 日本電気株式会社 マイクロプロセッサ
DE19933130A1 (de) * 1999-07-19 2001-01-25 Giesecke & Devrient Gmbh Operandenstapelspeicher und Verfahren zum Betreiben eines Operandenstapelspeichers
JP2002014809A (ja) * 2000-06-28 2002-01-18 Mitsubishi Electric Corp マイクロプロセッサ並びにアセンブラ、その方法およびそのプログラムを記録した記録媒体
US20020184566A1 (en) * 2001-06-01 2002-12-05 Michael Catherwood Register pointer trap
JP2004118419A (ja) * 2002-09-25 2004-04-15 Seiko Epson Corp 半導体装置、マイクロコンピュータ、電子機器、半導体装置の制御方法
US7386690B2 (en) * 2004-04-29 2008-06-10 International Business Machines Corporation Method and apparatus for hardware awareness of data types
US8250553B2 (en) * 2006-07-27 2012-08-21 International Business Machines Corporation Method and data processing system for finding problems caused by access to uninitialized data storage in assembler programs
JP6037034B2 (ja) * 2013-09-25 2016-11-30 日産自動車株式会社 ソフトウェア検査装置、ソフトウェア検査方法、ソフトウェア検査プログラム
US10296416B2 (en) * 2016-07-02 2019-05-21 Intel Corporation Read from memory instructions, processors, methods, and systems, that do not take exception on defective data
KR102021447B1 (ko) * 2018-04-06 2019-09-16 서울대학교산학협력단 컴퓨팅 장치 및 그것의 동작 방법

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