JPWO2020170069A1 - - Google Patents

Info

Publication number
JPWO2020170069A1
JPWO2020170069A1 JP2021501130A JP2021501130A JPWO2020170069A1 JP WO2020170069 A1 JPWO2020170069 A1 JP WO2020170069A1 JP 2021501130 A JP2021501130 A JP 2021501130A JP 2021501130 A JP2021501130 A JP 2021501130A JP WO2020170069 A1 JPWO2020170069 A1 JP WO2020170069A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2021501130A
Other versions
JPWO2020170069A5 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2020170069A1 publication Critical patent/JPWO2020170069A1/ja
Publication of JPWO2020170069A5 publication Critical patent/JPWO2020170069A5/ja
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52Protection of memory contents; Detection of errors in memory contents
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B99/00Subject matter not provided for in other groups of this subclass
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4097Bit-line organisation, e.g. bit-line layout, folded bit lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0403Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals during or with feedback to manufacture
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411Online error correction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Computer Security & Cryptography (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
JP2021501130A 2019-02-22 2020-02-11 Pending JPWO2020170069A1 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019030525 2019-02-22
PCT/IB2020/051043 WO2020170069A1 (ja) 2019-02-22 2020-02-11 エラー検出機能を有する記憶装置、半導体装置、および、電子機器

Publications (2)

Publication Number Publication Date
JPWO2020170069A1 true JPWO2020170069A1 (ja) 2020-08-27
JPWO2020170069A5 JPWO2020170069A5 (ja) 2023-01-31

Family

ID=72144818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021501130A Pending JPWO2020170069A1 (ja) 2019-02-22 2020-02-11

Country Status (5)

Country Link
US (1) US20220085019A1 (ja)
JP (1) JPWO2020170069A1 (ja)
KR (1) KR20210130734A (ja)
CN (1) CN113424310A (ja)
WO (1) WO2020170069A1 (ja)

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012256821A (ja) 2010-09-13 2012-12-27 Semiconductor Energy Lab Co Ltd 記憶装置
KR101912223B1 (ko) * 2011-08-16 2019-01-04 삼성전자주식회사 적층 자기 램 장치 및 이를 포함하는 메모리 시스템
US9013921B2 (en) * 2012-12-06 2015-04-21 Samsung Electronics Co., Ltd. Semiconductor memory device
US9424953B2 (en) * 2013-06-20 2016-08-23 Samsung Electronics Co., Ltd. Semiconductor memory device including repair circuit
US9362007B2 (en) * 2013-06-20 2016-06-07 Samsung Electronics Co., Ltd. Semiconductor memory device
JP2015053096A (ja) * 2013-09-09 2015-03-19 マイクロン テクノロジー, インク. 半導体装置、及び誤り訂正方法
US9583177B2 (en) * 2014-12-10 2017-02-28 Semiconductor Energy Laboratory Co., Ltd. Memory device and semiconductor device including memory device
KR20230003301A (ko) * 2015-02-26 2023-01-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 메모리 시스템 및 정보 처리 시스템
US9728243B2 (en) * 2015-05-11 2017-08-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device or electronic component including the same
JP6901831B2 (ja) * 2015-05-26 2021-07-14 株式会社半導体エネルギー研究所 メモリシステム、及び情報処理システム
KR102336458B1 (ko) * 2015-07-30 2021-12-08 삼성전자주식회사 고속으로 결함 비트 라인을 검출하는 불휘발성 메모리 장치 및 그것의 테스트 시스템
KR102424702B1 (ko) * 2015-11-19 2022-07-25 삼성전자주식회사 불휘발성 메모리 모듈 및 이를 포함하는 전자 장치
US10097207B2 (en) * 2016-03-10 2018-10-09 Toshiba Memory Corporation ECC circuit, storage device and memory system
KR102636039B1 (ko) * 2016-05-12 2024-02-14 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 읽기 방법 및 카피백 방법
US10263119B2 (en) * 2016-09-23 2019-04-16 Semiconductor Energy Laboratory Co., Ltd. Programmable device with high reliability for a semiconductor device, display system, and electronic device
KR102648774B1 (ko) * 2016-11-10 2024-03-19 에스케이하이닉스 주식회사 랜더마이즈 동작을 수행하는 반도체 메모리 장치

Also Published As

Publication number Publication date
WO2020170069A1 (ja) 2020-08-27
US20220085019A1 (en) 2022-03-17
KR20210130734A (ko) 2021-11-01
CN113424310A (zh) 2021-09-21

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