JPWO2020122014A1 - Wiring boards for semiconductor devices, their manufacturing methods, and semiconductor devices - Google Patents

Abstract

It alleviates deformation and displacement stress between the interposer and the FC-BGA wiring board, prevents disconnection of the joint between the interposer and the FC-BGA wiring board, and improves the reliability of the connection between the interposer and the FC-BGA wiring board. It provides a high wiring board and a method for manufacturing the same. The wiring board includes an FC-BGA wiring board and an interposer, and the FC-BGA wiring board and the interposer are electrically bonded via protruding electrodes, respectively, and a sealing resin is formed in the gap between the FC-BGA wiring board and the interposer. The underfill is filled. Further, the underfill covers the entire side surface of the interposer and the peripheral edge of the surface opposite to the surface where the interposer joins the FC-BGA wiring board.

Description

The present invention relates to a wiring board for a semiconductor device, a method for manufacturing the same, and a semiconductor device.

In recent years, with the progress of high speed and high integration of semiconductors, narrowing of the pitch of connection terminals of semiconductor chips has been promoted, and correspondingly, narrowing of pitch of connection terminals on the wiring board side and miniaturization of wiring have been required. There is. On the other hand, the connection between the FC-BGA (Flip Chip Ball Grid Array) wiring board and the motherboard is required to be connected with connection terminals having a pitch that is almost the same as the conventional one. Therefore, in order to connect the FCBGA wiring board and the semiconductor chip, it is necessary to overcome the problem that the dimensions of the terminal electrodes and the pitch of the connection terminals are different from each other.

In order to narrow the pitch of the connection terminals with the semiconductor chip and miniaturize the board wiring, there is a technology to form wiring on silicon to make a chip connection board (silicon interposer) and connect it to the FC-BGA wiring board. It is disclosed in Patent Document 1.

Silicon interposers are generally manufactured using equipment for semiconductor processes on silicon wafers, but silicon wafers are limited in shape and size, and the number of interposers that can be manufactured from a single wafer is small. The equipment is also expensive. Therefore, in addition to the problem that the interposer becomes expensive, there is a problem that the transmission characteristics also deteriorate because the silicon wafer is a semiconductor.

Further, Patent Document 2 discloses a technique for forming fine wiring after flattening the surface of a wiring board by CMP (Chemical Mechanical Polishing) or the like.

According to the technique of flattening the wiring board and forming a fine wiring layer on the wiring board, the problem of deterioration of transmission characteristics that occurs in the silicon interposer can be avoided, but the manufacturing defect of the wiring board and the highly difficult fine wiring layer are avoided. In addition to the problem that the yield deteriorates due to the sum of the defects at the time of formation, there is a problem that it is difficult to mount the semiconductor chip due to warpage and distortion.

In view of the above problems, a second wiring board (interposer) provided with a fine wiring layer is formed on a flat support, and the second wiring board (interposer) provided with this support is used as the first wiring board. Patent Document 3 proposes a technique for forming a second wiring board (interposer) on a first wiring board by mounting the material via solder and then peeling off the support.

JP-A-2002-280490 Japanese Unexamined Patent Publication No. 2014-225671 International Publication No. 2018/047861

According to the technique of Patent Document 3, after the support provided with the second wiring board (interposer) is joined to the first wiring board, the stress at the joint is relaxed in the gap between the second wiring board and the first wiring board. Therefore, and when trying to fill the underfill so that the support can be easily peeled off, solder cracks and warpage (deformation) of the substrate occur due to stress concentration due to the difference in linear expansion coefficient of each member, resulting in chip mountability and chip mountability. In some cases, it became difficult to ensure joining reliability.

The present invention has been made by paying attention to the above problems, and is capable of further relaxing deformation and displacement stress between wiring boards, preventing disconnection of joints, and improving connection reliability. It is an object of the present invention to provide a method for producing the same, a method for manufacturing the same, and a semiconductor device.

According to one aspect of the present invention, the wiring board for a semiconductor device for mounting a semiconductor chip is
Equipped with a first wiring board and a second wiring board,
The first wiring board and the second wiring board are electrically joined via a protruding electrode.
The gap between the first wiring board and the second wiring board is filled with a sealing resin, and the sealing resin is used for the entire side surface of the second wiring board and the second wiring board for the first wiring. It is characterized in that it covers the peripheral edge of the surface opposite to the surface to be joined to the substrate.

According to one aspect of the present invention, the method for manufacturing a wiring board for a semiconductor device is
A process of sequentially forming a release layer, a protective layer, a seed layer, and a second wiring board on the support, and
The process of electrically joining the second wiring board and the first wiring board,
A step of sequentially peeling the support, the peeling layer, the protective layer, and the seed layer,
The gap between the first wiring board and the second wiring board is filled with a sealing resin, and the sealing resin makes the entire side surface of the second wiring board and the second wiring board with the first wiring board. It is characterized by including a step of covering the peripheral portion of the surface opposite to the surface to be joined.

According to one aspect of the present invention, the wiring board for a semiconductor device is
The first wiring board and
A second wiring board joined on one surface of the first wiring board is provided.
The first wiring board and the second wiring board are electrically bonded via the protruding electrodes.
The gap between the first wiring board and the second wiring board is filled with an insulating sealing resin.
The sealing resin is continuous from the gap between the first wiring board and the second wiring board, covers the entire side surface of the second wiring board, and is connected to the first wiring board of the second wiring board. Extends beyond the surface opposite to the surface to be joined,
The second wiring board is characterized by having a pad on a surface opposite to the surface to be joined to the first wiring board side.

According to one aspect of the present invention, the method for manufacturing a wiring board for a semiconductor device is
A release layer forming step of forming a release layer on one surface of the support,
A wiring layer for producing a second wiring board with a support by forming a wiring layer on the release layer in which the surface on the release layer side serves as the first pad and the surface opposite to the release layer serves as the second pad. The formation process and
A protrusion electrode forming step of forming a protrusion electrode on the surface of the second pad,
An electrical joining step of electrically joining the first wiring board pad of the first wiring board and the protruding electrode of the second wiring board.
From the gap between the first wiring board and the second wiring board, the entire side surface of the second wiring board is covered with the outside of the gap, and the surface of the second wiring board to be joined to the first wiring board. A sealing resin filling and injecting step of filling and injecting an insulating sealing resin so as to extend beyond the opposite side surface.
A support peeling step of peeling the support and the peeling layer from the second wiring board,
It is characterized by having a pad exposure step of exposing the first pad as a connection pad.

According to one aspect of the present invention, the wiring board for a semiconductor device is
The first wiring board and
With the second wiring board joined on one surface of the first wiring board,
The first sealing resin that seals the gap between the first wiring board and the second wiring board,
It is characterized by including at least a second sealing resin formed so as to cover a boundary between the side surface of the second wiring board and the first sealing resin.

According to one aspect of the present invention, the method for manufacturing a wiring board for a semiconductor device is
The first sealing resin sealing step of sealing the gap between the first wiring board and the second wiring board with the first sealing resin,
It is characterized by comprising at least a second sealing resin sealing step of forming the second sealing resin so as to cover the boundary between the side surface of the second wiring board and the first sealing resin.

According to the present invention, a wiring board for a semiconductor device, a manufacturing method thereof, and a semiconductor device capable of further relaxing deformation and displacement stress between wiring boards, preventing disconnection of a joint portion, and improving connection reliability. Can be provided.

FIG. 1 is a schematic cross-sectional view of a wiring board according to the first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a semiconductor device in which a semiconductor chip is mounted on the wiring substrate of FIG. 1 according to the first embodiment of the present invention. FIG. 3A is a schematic cross-sectional view illustrating a part of the manufacturing process of the wiring board of FIG. 1 according to the first embodiment of the present invention up to the manufacturing of an interposer with a support. FIG. 3B is a schematic cross-sectional view illustrating a part of the manufacturing process of the wiring board of FIG. 1 according to the first embodiment of the present invention up to the manufacturing of an interposer with a support. FIG. 3C is a schematic cross-sectional view illustrating a part of the manufacturing process of the wiring board of FIG. 1 according to the first embodiment of the present invention up to the manufacturing of an interposer with a support. FIG. 3D is a schematic cross-sectional view illustrating a part of the manufacturing process of the wiring board of FIG. 1 according to the first embodiment of the present invention up to the manufacturing of an interposer with a support. FIG. 3E is a schematic cross-sectional view illustrating a part of the manufacturing process of the wiring board of FIG. 1 according to the first embodiment of the present invention up to the manufacturing of an interposer with a support. FIG. 4A is a schematic cross-sectional view illustrating a part of the steps up to the manufacture of the interposer with a support, following FIGS. 3A to 3E. FIG. 4B is a schematic cross-sectional view illustrating a part of the steps up to the manufacture of the interposer with a support, following FIGS. 3A to 3E. FIG. 4C is a schematic cross-sectional view illustrating a part of the steps up to the manufacture of the interposer with a support, following FIGS. 3A to 3E. FIG. 4D is a schematic cross-sectional view illustrating a part of the steps up to the manufacture of the interposer with a support, following FIGS. 3A to 3E. FIG. 4E is a schematic cross-sectional view illustrating a part of the steps up to the manufacture of the interposer with a support, following FIGS. 3A to 3E. FIG. 5A is a schematic cross-sectional view illustrating a part of the steps up to the manufacture of the interposer with a support, following FIGS. 4A to 4E. FIG. 5B is a schematic cross-sectional view illustrating a part of the steps up to the manufacture of the interposer with a support, following FIGS. 4A to 4E. FIG. 5C is a schematic cross-sectional view illustrating a part of the steps up to the manufacture of the interposer with a support, following FIGS. 4A to 4E. FIG. 5D is a schematic cross-sectional view illustrating a part of the steps up to the manufacture of the interposer with a support, following FIGS. 4A to 4E. FIG. 6A is a schematic cross-sectional view illustrating a part of the manufacturing process of the wiring board of FIG. 1, following FIGS. 5A to 5D. FIG. 6B is a schematic cross-sectional view illustrating a part of the manufacturing process of the wiring board of FIG. 1, following FIGS. 5A to 5D. FIG. 7A is a schematic cross-sectional view illustrating a part of the manufacturing process of the wiring board of FIG. 1, following FIGS. 6A and 6B. FIG. 7B is a schematic cross-sectional view illustrating a part of the manufacturing process of the wiring board of FIG. 1, following FIGS. 6A and 6B. FIG. 8A is a schematic cross-sectional view illustrating the manufacturing process of the wiring board of FIG. 1 and the semiconductor device of FIG. 2, following FIGS. 7A to 7C. FIG. 8B is a schematic cross-sectional view illustrating the manufacturing process of the wiring board of FIG. 1 and the semiconductor device of FIG. 2, following FIGS. 7A to 7C. FIG. 8C is a schematic cross-sectional view illustrating the manufacturing process of the wiring board of FIG. 1 and the semiconductor device of FIG. 2, following FIGS. 7A to 7C. FIG. 9 is a schematic cross-sectional view of a wiring board which is a reference example. FIG. 10 is a schematic cross-sectional view showing an example in which a semiconductor chip is mounted on a wiring board according to a second embodiment of the present invention. FIG. 11 is a schematic cross-sectional view showing a state in which a support for a second wiring board (interposer) according to a second embodiment of the present invention is attached. FIG. 12A is a schematic explanatory view of an example of a manufacturing process of a second wiring board (interposer) having a support according to a schematic cross-sectional view according to a second embodiment of the present invention. FIG. 12B is a schematic explanatory view of an example of a manufacturing process of a second wiring board (interposer) having a support according to a schematic cross-sectional view according to a second embodiment of the present invention. FIG. 12C is a schematic explanatory view of an example of a manufacturing process of a second wiring board (interposer) having a support according to a schematic cross-sectional view according to a second embodiment of the present invention. FIG. 12D is a schematic explanatory view of an example of a manufacturing process of a second wiring board (interposer) having a support according to a schematic cross-sectional view according to a second embodiment of the present invention. FIG. 12E is a schematic explanatory view of an example of a manufacturing process of a second wiring board (interposer) having a support according to a schematic cross-sectional view according to a second embodiment of the present invention. FIG. 12F is a schematic explanatory view of an example of a manufacturing process of a second wiring board (interposer) having a support according to a schematic cross-sectional view according to a second embodiment of the present invention. FIG. 12G is a schematic explanatory view of an example of a manufacturing process of a second wiring board (interposer) having a support according to a schematic cross-sectional view according to a second embodiment of the present invention. FIG. 12H is a schematic explanatory view of an example of a manufacturing process of a second wiring board (interposer) having a support according to a schematic cross-sectional view according to a second embodiment of the present invention. FIG. 12I is a schematic explanatory view of an example of a manufacturing process of a second wiring board (interposer) having a support according to a schematic cross-sectional view according to a second embodiment of the present invention. FIG. 12J is a schematic explanatory view of an example of a manufacturing process of a second wiring board (interposer) having a support according to a schematic cross-sectional view according to a second embodiment of the present invention. FIG. 12K is a schematic explanatory view of an example of a manufacturing process of a second wiring board (interposer) having a support according to a schematic cross-sectional view according to a second embodiment of the present invention. FIG. 12L is a schematic explanatory view of an example of a manufacturing process of a second wiring board (interposer) having a support according to a schematic cross-sectional view according to a second embodiment of the present invention. FIG. 12M is a schematic explanatory view of an example of a manufacturing process of a second wiring board (interposer) having a support according to a schematic cross-sectional view according to a second embodiment of the present invention. FIG. 12N is a schematic explanatory view of an example of a manufacturing process of a second wiring board (interposer) having a support according to a schematic cross-sectional view according to a second embodiment of the present invention. FIG. 13A is a schematic explanatory view of a wiring substrate according to a schematic cross-sectional view according to a second embodiment of the present invention and an example of a manufacturing process of a semiconductor device. FIG. 13B is a schematic explanatory view of a wiring substrate according to a schematic cross-sectional view according to a second embodiment of the present invention and an example of a manufacturing process of a semiconductor device. FIG. 13C is a schematic explanatory view of a wiring substrate according to a schematic cross-sectional view according to a second embodiment of the present invention and an example of a manufacturing process of a semiconductor device. FIG. 13D is a schematic explanatory view of a wiring substrate according to a schematic cross-sectional view according to a second embodiment of the present invention and an example of a manufacturing process of a semiconductor device. FIG. 13E is a schematic explanatory view of a wiring substrate according to a schematic cross-sectional view according to a second embodiment of the present invention and an example of a manufacturing process of a semiconductor device. FIG. 13F is a schematic explanatory view of a wiring substrate according to a schematic cross-sectional view according to a second embodiment of the present invention and an example of a manufacturing process of a semiconductor device. FIG. 13G is a schematic explanatory view of a wiring substrate according to a schematic cross-sectional view according to a second embodiment of the present invention and an example of a manufacturing process of a semiconductor device. FIG. 14 is a cross-sectional view showing an example of a semiconductor package in which a semiconductor chip is mounted on a wiring board according to a third embodiment of the present invention. FIG. 15 is a cross-sectional view showing an example of a wiring board according to a third embodiment of the present invention. FIG. 16 is a cross-sectional view showing an example of a wiring board according to a third embodiment of the present invention. FIG. 17 is a cross-sectional view showing an example of a wiring board according to a third embodiment of the present invention. FIG. 18A is a cross-sectional view showing an example of a manufacturing process of a wiring board according to a third embodiment of the present invention. FIG. 18B is a cross-sectional view showing an example of a manufacturing process of a wiring board according to a third embodiment of the present invention. FIG. 18C is a cross-sectional view showing an example of a manufacturing process of a wiring board according to a third embodiment of the present invention. FIG. 18D is a cross-sectional view showing an example of a manufacturing process of a wiring board according to a third embodiment of the present invention. FIG. 18E is a cross-sectional view showing an example of a manufacturing process of a wiring board according to a third embodiment of the present invention. FIG. 19A is a cross-sectional view showing an example of a manufacturing process of a wiring board according to a third embodiment of the present invention. FIG. 19B is a cross-sectional view showing an example of a manufacturing process of a wiring board according to a third embodiment of the present invention. FIG. 19C is a cross-sectional view showing an example of a manufacturing process of a wiring board according to a third embodiment of the present invention.

Hereinafter, a wiring board for a semiconductor device (hereinafter, simply referred to as a wiring board) according to an embodiment of the present invention will be described with reference to the drawings. However, in each of the figures described below, the parts corresponding to each other are designated by the same reference numerals, and the description of the overlapping parts will be omitted as appropriate. In addition, each drawing is exaggerated as appropriate for ease of explanation.

Further, the embodiment of the present invention exemplifies a configuration for embodying the technical idea of the present invention, and does not specify the material, shape, structure, arrangement, etc. of each part as the following. The technical idea of the invention may be modified within the technical scope specified by the claims stated in the claims.

(First Embodiment)
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic cross-sectional view of a wiring board according to an embodiment of the present invention. The wiring board CB100 includes an FC-BGA wiring board (first wiring board) 1 and an interposer (second wiring board) 3. The FC-BGA wiring board 1 and the interposer 3 are electrically bonded to each other via solder bumps 25 as protrusion electrodes, and an underfill 2 is provided as a sealing resin in the gap between the FC-BGA wiring board 1 and the interposer 3. It is filled. The protruding electrode may be a copper post (copper pillar), a gold bump, or the like, in addition to the solder bump.

The underfill 2 is an adhesive material used for fixing and sealing the FC-BGA wiring board 1 and the interposer 3. The underfill 2 includes, for example, silica as a filler in a resin obtained by mixing one of epoxy resin, urethane resin, silicon resin, polyester resin, oxetane resin, and maleimide resin, or two or more of these resins. , Titanium oxide, aluminum oxide, magnesium oxide, zinc oxide and the like are added to the material. The underfill 2 is formed by filling and curing a liquid resin.

In the wiring board CB100 of the present embodiment, the underfill 2 includes not only the gap between the interposer 3 and the FC-BGA wiring board 1, but also the entire side surface of the interposer 3 and the surface where the interposer 3 joins the FC-BGA wiring board 1. It covers the peripheral edge of the opposite surface (upper surface in FIG. 1).

If the underfill 2 is applied and formed only in the gap between the interposer 3 and the FC-BGA wiring board 1, the interposer 3 is based on an organic resin, so that the thermal stress is concentrated in the plane center direction of the gap, and the FC -Deformation and displacement stress are generated between the BGA wiring board 1 and the board 1.

On the other hand, in the wiring board CB100 of the present embodiment, the underfill 2 is applied to the entire side surface of the interposer 3 and the peripheral edge of the surface opposite to the surface where the interposer 3 joins the FC-BGA wiring board 1. Since it is hardened, the thermal stress is dispersed in multiple directions, and the effect of relaxing the stress concentration is exhibited. As a result, the interposer 3 and the FC-BGA wiring board 1 can exhibit high connection reliability.

FIG. 2 is a schematic cross-sectional view of a semiconductor device in which a semiconductor chip is mounted on the wiring substrate of FIG. 1 according to the first embodiment of the present invention. In the semiconductor device SD100 of the present embodiment, the semiconductor chip 4 is joined via the copper pillar 30 on the surface of the interposer 3 in the wiring board CB100 of FIG. 1 opposite to the FC-BGA wiring board 1, and the semiconductor chip 4 and the semiconductor chip 4 are joined. The gap with the interposer 3 is filled with the underfill 32.

The underfill 32 is an adhesive used for fixing and sealing the semiconductor chip 4 and the interposer 3, and is made of the same material as the underfill 2. In this case, an anisotropic conductive film (ACF) or a film-like connecting material (NCF) may be used as the sealing resin instead of the underfill 32.

The wiring pitch of the portion of the interposer 3 to be joined to the semiconductor chip 4 is the portion to be joined to the semiconductor chip 4 of the FC-BGA wiring board 1 when the semiconductor chip 4 and the FC-BGA wiring board 1 are directly joined. It becomes narrower than the wiring pitch of. That is, the surface of the interposer 3 on which the semiconductor chip 4 is mounted has finer wiring than the FC-BGA wiring board 1 when the interposer 3 is joined to the semiconductor chip 4.

For example, in order to support the use of the current high band memory (HBM), the wiring width of the interposer 3 needs to be 2 μm or more and 6 μm or less. In order to match the characteristic impedance to 50Ω, when the wiring width is 2 μm and the wiring height is 2 μm, the insulating film thickness between the wirings is 2.5 μm. The thickness of one layer including wiring is 4.5 μm, and when forming a five-layer interposer 3 with this thickness, the interposer 3 is an ultra-thin interposer with a total thickness of about 25 μm.

As described above, since the thickness of the interposer 3 is thin and it is difficult to mount it on the FC-BGA wiring board 1 as it is, the interposer 3 is required to have rigidity. Further, in order to form a wiring having a width and height of about 2 μm, a flat support is required. Therefore, as will be described later, the interposer 3 is formed on a rigid and flat support via a release layer, a protective layer, and a seed layer. A layer other than the release layer, the protective layer, and the seed layer may be provided on the support.

Next, with reference to FIGS. 3A to 5D, in the manufacturing process of the wiring board of FIG. 1 according to the present embodiment, up to the manufacturing of the interposer 3 in the form with the support 5 will be described. First, as shown in FIG. 3A, a release layer 6 for peeling the support 5 in a subsequent step is formed on one surface of the support 5.

The peeling layer 6 may be a resin that can be peeled off by UV light or infrared light, or may be a resin that foams by heat. When a resin that can be peeled off by UV light or infrared light is used, the support 5 is irradiated with UV light or infrared light from the surface opposite to the side on which the peeling layer 6 is provided, and the interposer 3 and the interposer 3 and the support 5 are irradiated with UV light or infrared light. The support 5 is removed from the joint with the FC-BGA wiring board 1. Therefore, the support 5 needs to have transparency, and glass can be used, for example. Glass has excellent flatness and is suitable for forming a fine wiring pattern of the interposer 3, and since glass has a small coefficient of thermal expansion and is not easily distorted, pattern arrangement accuracy when joined to the FC-BGA wiring substrate 1 And it is excellent in ensuring flatness.

When glass is used as the support 5, the thickness of the glass is preferably thick from the viewpoint of suppressing the occurrence of warpage in the manufacturing process, and for example, the thickness is preferably 0.7 mm or more and 1.1 mm or less. The coefficient of thermal expansion of glass is 3 ppm / ° C. or higher and 15 ppm / ° C. or lower, and is preferably about 9 ppm / ° C. from the viewpoint of the coefficient of thermal expansion of the FC-BGA wiring board and the semiconductor chip. In one embodiment of the present invention, glass was used as the support 5.

On the other hand, when a resin that foams by heat is used for the release layer 6, the support 5 can be removed by heating the joint between the interposer 3 and the FC-BGA wiring board 1. In this case, the support 5 can be made of metal or ceramics having less distortion.

Next, as shown in FIG. 3B, a protective layer 7 is formed on the release layer 6. The protective layer 7 is a layer for protecting the interposer 3 when the support 5 is peeled off in a subsequent step, and is one of epoxy resin, acrylic resin, urethane resin, silicon resin, polyester resin, oxetane resin, or one of these. It is a resin in which two or more kinds of resins are mixed, and is a resin that can be removed after the support 5 is removed from the interposer 3. As for the method of forming the protective layer 7, it may be appropriately formed according to the shape of the resin such as spin coating and laminating. In one embodiment of the present invention, an acrylic resin is formed by a laminating method to form a protective layer 7.

Next, as shown in FIG. 3C, the seed layer 11 is formed on the protective layer 7 by a sputtering method or the like in vacuum. Regarding the material and composition of the seed layer, a titanium layer / copper layer (Ti / Cu), a chromium layer / copper layer (Cr / Cu), a nickel chromium layer / copper layer (NiCr / Cu), etc. , Thickness can be selected. In this embodiment, the seed layer 11 is formed with Ti: 50 nm thick and Cu: 300 nm thick. By forming the seed layer 11 on the protective layer 7, it is possible to form a wiring pattern by electroplating on the seed layer 11.

Next, as shown in FIG. 3D, a resist pattern 13 is formed on the seed layer, and a conductor layer 14 to be a wiring pattern is formed in the opening 13a by electrolytic plating. In this embodiment, copper Cu is formed as the conductor layer 14. After that, the resist pattern 13 is removed as shown in FIG. 3E.

Next, as shown in FIG. 4A, the photosensitive insulating resin layer 15 is formed on the seed layer 11 and the conductor layer 14. The photosensitive insulating resin layer 15 is formed so that the conductor layer 14 is embedded in the layer of the photosensitive insulating resin layer 15. In this embodiment, an epoxy resin is used as the photosensitive insulating resin and the resin is formed by a spin coating method. The photosensitive epoxy resin can be cured at a relatively low temperature, has less shrinkage due to curing after the formation of conductive vias, and is excellent in subsequent fine pattern formation.

The photosensitive insulating resin layer 15 can be formed by a spin coating method using a photosensitive epoxy resin, or can be formed by compressing and curing an insulating resin film with a vacuum laminator. In this case, the photosensitive insulating resin layer 15 can be formed by compression curing with a vacuum laminator. An insulating film having good flatness can be formed. Polyimide may be used as the photosensitive insulating resin as long as some steps can be tolerated in the exposure process. The photosensitive insulating resin layer 15 may be a positive type or a negative type.

Next, as shown in FIG. 4B, the opening 15a is provided on the conductor layer 14 of the photosensitive insulating resin layer 15 by photolithography. The opening 15a may be subjected to plasma treatment for the purpose of removing residues after development.

Next, as shown in FIG. 4C, a seed layer 18 is provided on the surface of the opening 15a. Regarding the configuration of the seed layer 18, the layer configuration and thickness can be appropriately selected depending on the application, such as Ti / Cu, Cr / Cu, NiCr / Cu, and the like. In this embodiment, the seed layer 18 is formed with Ti: 50 nm thick and Cu: 300 nm thick.

Next, as shown in FIG. 4D, a resist pattern 19 is formed on the seed layer 18, and a conductor layer 20 to be a wiring pattern is formed in the opening 19a by electrolytic plating. In this embodiment, copper Cu is formed as the conductor layer 20. Then, after removing the resist pattern 19 as shown in FIG. 4E, an unnecessary seed layer 18 (not shown) is removed by etching.

Further, the steps of FIGS. 4A to 4E are repeated to obtain the substrate on which the multilayer wiring pattern shown in FIG. 5A is formed.

Next, as shown in FIG. 5B, the insulating resin layer 23 is formed on the outermost surface of the interposer on the side to be joined to the FC-BGA wiring board 1. The insulating resin layer 23 is formed so as to cover the conductor layer 22 and the photosensitive insulating resin layer 15, and an opening 23a is formed in the insulating resin layer 23 so that the conductor layer 22 is exposed by exposure and development. In the present embodiment, the insulating resin layer 23 is formed by using a photosensitive epoxy resin as the insulating resin. The insulating resin may be the same material as the photosensitive insulating resin layer 15.

Next, as shown in FIG. 5C, a surface treatment layer 24 is provided in order to prevent oxidation of the surface of the conductor layer 22 and improve the wettability of the solder bumps. In this embodiment, electroless nickel / lead / gold (Ni / Pd / Au) plating is formed as the surface treatment layer 24. An OSP (Organic Soiderability Preservative, surface treatment with a water-soluble preflux) film may be formed on the surface treatment layer 24. Further, electroless tin plating, electroless nickel gold (Ni / Au) plating and the like may be appropriately selected and used according to the intended use.

Next, as shown in FIG. 5D, the solder bump 25 is mounted on the surface treatment layer 24 and reflowed to complete the interposer with the support 5. In contrast to flow solder, in which melted solder is applied from the beginning, reflow solder can be joined to parts by printing cream solder, etc. in advance at a designated location and heating it in a reflow furnace to melt it. Is.

Hereinafter, with reference to FIGS. 6A to 8C, the manufacturing process of the wiring board CB100 and the semiconductor device SD100 of FIG. 1 following FIG. 5D will be illustrated. First, as shown in FIG. 6A, the interposer 3 with the support 5 is attached to the FC-BGA wiring board 1 designed and manufactured so as to match the position of the solder bump 25 which is the terminal of the interposer 3 with the support 5 by a flip chip. Deploy. Next, as shown in FIG. 6B, a joint body obtained by joining the interposer 3 with the support 5 and the FC-BGA wiring board 1 via the solder bumps 25 is obtained.

Next, as shown in FIG. 7A, the laser beam 26 is transmitted from the back surface of the support 5, that is, the surface of the support 5 opposite to the FC-BGA wiring board 1 side to the interface thereof through the support 5. The formed release layer 6 is irradiated, and the support 5 is peeled off and removed as shown in FIG. 7B. At this time, since the interposer 3 and the FC-BGA wiring board 1 are joined by the solder bumps 25, they are not separated when the support 5 is removed.

Next, the release layer 6, the protective layer 7, and the seed layer 11 are removed to obtain a substrate as shown in FIG. 8A. In the present embodiment, the release layer 6 is mechanically peeled off from the protective layer 7. When an acrylic resin is used, the protective layer 7 is removed with an alkaline solvent (1% NaOH, 2.3% TMAH). Further, when titanium and copper are used from the protective layer 7 side, the seed layer 11 is dissolved and removed by an alkaline etching agent and an acid etching agent, respectively.

Further, as shown in FIG. 8B, the underfill 2 is applied to the gap between the interposer 3 and the FC-BGA wiring board 1, and the entire side surface of the interposer 3 and the surface of the interposer 3 to be joined to the FC-BGA wiring board 1 Underfill 2 is also applied to the peripheral edge of the opposite surface and heat-cured.
At this time, the underfill 2 is first filled in the gap between the interposer 3 and the FC-BGA wiring board 1 using a capillary (not shown). Subsequently, the side surface and the peripheral portion of the interposer 3 are directly formed by scanning the coating head (not shown) of the jet dispenser. In this way, the wiring board CB100 is obtained. It is preferable to apply a large amount of the underfill 2 at a time or a plurality of times so as to wrap around the outer periphery of the upper surface of the interposer 3.

In the wiring substrate CB100, on the conductor layer 14 exposed on the surface, a surface treatment layer such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, and electroless Ni / Au plating is performed in the same manner as in the process of FIG. 5C. (Not shown) may be formed.

Finally, the semiconductor device SD100 is manufactured by joining the semiconductor chip 4 to the wiring board CB100 by a known method and filling the gap between the wiring board CB100 and the semiconductor chip 4 with an underfill 32 as shown in FIG. 8C. can do.

FIG. 9 is a schematic cross-sectional view of the wiring board CB200 which is a reference example.
In the reference example of FIG. 9, an interposer 3 provided with a fine wiring layer formed by laminating resin and wiring on a flat support as in the present embodiment is produced, and the interposer 3 provided with this support is provided. After joining to the FC-BGA wiring board 1 via solder, the gap between the interposer 3 and the FC-BGA wiring board 1 is filled with the underfill 42 as a sealing resin. After that, by removing the support, the wiring board CB200 in which the interposer 3 is bonded on the FC-BGA wiring board 1 is manufactured.

By the way, since the underfill 42 is filled in the gap between the interposer 3 and the FC-BGA wiring board 1, it is necessary to select a material that does not easily damage the solder, and the degree of freedom in selecting the material is limited. On the other hand, when the underfill 42 is filled, the underfill 42 may run up (wet up) along the side surface of the interposer 3 due to surface tension and reach the middle in the thickness direction of the interposer 3. In such a case, the film thickness of the underfill 42 becomes thinner toward the upper side, and the underfill 42 is interrupted at the boundary point BD. At this time, if the linear expansion coefficient and elastic modulus of the material of the underfill 42 are different from the linear expansion coefficient and elastic modulus of the material of the interposer 3, stress concentration of the interposer 3 occurs near the boundary point BD during resin curing. , May cause cracks and peeling.

On the other hand, the wiring board manufactured by the manufacturing method according to the present embodiment is a joint body of the interposer and the FC-BGA wiring board formed on the support, and after joining the interposer and the FC-BGA wiring board, the interposer is used. The support is peeled off, and then the underfill is applied to the gap between the FC-BGA wiring board and the interposer, the entire side surface of the interposer, and the peripheral edge of the surface opposite to the surface where the interposer joins the FC-BGA wiring board. Since it is formed by filling and coating, the concentration of stress due to hardening of the underfill is alleviated, it is possible to prevent disconnection of the joint between the interposer and the FC-BGA wiring board, and thus improve the connection reliability of the joint. can.

(Second Embodiment)
Hereinafter, the wiring board according to the second embodiment will be described with reference to the drawings. However, in each of the figures described below, the parts corresponding to each other are designated by the same reference numerals, and the description of the overlapping parts will be omitted as appropriate.
Further, one embodiment of the present invention exemplifies a configuration for embodying the technical idea of the present invention, and does not specify the material, shape, structure, arrangement, etc. of each part to the following. The technical idea of the present invention may be modified within the technical scope specified by the claims stated in the claims.

FIG. 10 is a schematic cross-sectional view of a semiconductor device in which a semiconductor chip is mounted on a wiring board according to a second embodiment.

The wiring board according to the present embodiment includes a FC-BGA wiring board 101 as the first wiring board and a fine wiring layer formed only by a build-up wiring layer in which resin and wiring are laminated as the second wiring board. A thin interposer 103 is used. More specifically, the wiring board includes a second wiring board (interposer) 103 joined on the main surface of the first wiring board (FC-BGA wiring board) 101. The first wiring board (FC-BGA wiring board) 101 and the second wiring board (interposer) 103 are electrically joined via the protrusion electrode 125, and the first wiring board (FC-BGA wiring board) 101 and the second wiring board (FC-BGA wiring board) 101 and the second The gap of the wiring board (interposer) 103 is filled with an insulating sealing resin 102.

The sealing resin 102 is continuous outside the gap between the first wiring board (FC-BGA wiring board) 101 and the second wiring board (interposer) 103, and covers the entire side surface of the second wiring board (interposer) 103. It forms a bank (peripheral wall) that is the upper surface of the enclosed second wiring board at a height exceeding the upper surface. The second wiring board (interposer) 103 has a pad 140 (FIG. 13F) on a surface opposite to the first wiring board (FC-BGA wiring board) 101 side.

The protruding electrode 125 (see FIG. 13A) is composed of solder bumps or copper posts (copper pillars) or gold bumps.
Further, the semiconductor chip 104 is bonded to the surface of the second wiring board (interposer) 103 opposite to the first wiring board (FC-BGA wiring board) 101 by a copper pillar 131, and the semiconductor chip 104 and the second wiring board ( The gap with the interposer 103 is embedded in the sealing resin 132, and the height of the sealing resin 132 is formed higher than that of the second wiring board (interposer) 103.

The sealing resin 102 is an adhesive material used for fixing and sealing the first wiring board (FC-BGA wiring board) 101 and the second wiring board (interposer) 103. Examples of the sealing resin 102 include silica as a filler in a resin obtained by mixing one of epoxy resin, urethane resin, silicon resin, polyester resin, oxetane resin, and maleimide resin, or two or more of these resins. A material to which titanium oxide, aluminum oxide, magnesium oxide, zinc oxide or the like is added is used. The sealing resin 102 is formed by filling with a liquid resin.

The sealing resin 132 is an adhesive used for fixing and sealing the semiconductor chip 104 and the interposer 103, and is made of the same material as the sealing resin 102. In this case, an anisotropic conductive film (ACF: anisotropic conductive film) or a film-like connecting material (NCF: non-conductive film) may be used as the sealing resin 132.

The wiring pitch of the portion of the second wiring board (interposer) 103 that is joined to the semiconductor chip 104 is the wiring pitch of the portion that is joined to the semiconductor chip 104. This is narrower than the wiring pitch of the portion of the first wiring board (FC-BGA wiring board) 101 to be joined to the semiconductor chip 104. That is, the surface of the second wiring board (interposer) 103 on the side where the semiconductor chip 104 is mounted has finer wiring than the FC-BGA wiring board 101 when joining the semiconductor chip 104.

For example, in order to support the use of the current high band memory (HBM), the wiring width of the second wiring board (interposer) 103 needs to be 2 μm or more and 6 μm or less. In order to match the characteristic impedance to 50Ω, when the wiring width is 2 μm and the wiring height is 2 μm, the insulating film thickness between the wirings is 2.5 μm. The thickness of one layer including wiring is 4.5 μm, and when forming a five-layer second wiring board (interposer) 103 with this thickness, the total thickness of the second wiring board (interposer) 103 is about 25 μm. It becomes an ultra-thin interposer.

As described above, the thickness of the second wiring board (interposer) 103 is thin, and it is difficult to mount it on the FC-BGA wiring board 101 as it is. Therefore, the second wiring board (interposer) 103 has rigidity. Desired. Further, in order to form a wiring having a width and height of about 2 μm, a flat support is required. For the above reason, as shown in FIG. 11, the second wiring board (interposer) 103 is formed on the rigid and flat support 105 via the release layer 106, the protective layer 107, and the seed layer 108. A layer other than the release layer, the protective layer, and the seed layer may be provided on the support.

Next, an example of the manufacturing process of the second wiring board (interposer) 103 with the support 105 according to the present embodiment will be described step by step from FIGS. 12A to 12N.

First, a wiring board to be a second wiring board (interposer) 103 is produced on the support 105. As shown in FIG. 12A, a release layer 106 for peeling the support 105 is formed on one surface of the support 105 in a subsequent step (release layer forming step).

Next, as shown in FIG. 12B, a protective layer 107 is formed on the release layer 106. The protective layer 107 is a layer for protecting the second wiring substrate (interposer) 103 when the support 105 is peeled off in a later step, and is an epoxy resin, an acrylic resin, a urethane resin, a silicon resin, a polyester resin, or an oxetane resin. Is a resin obtained by mixing one of these resins or two or more of these resins, and is a resin that can be removed after peeling the second wiring substrate (interposer) 103 from the support 105. The protective layer 107 may be appropriately formed depending on the shape of the resin, such as spin coating and lamination. For example, an acrylic resin is formed by a laminating method.

The peeling layer 106 may be a resin that can be peeled off by UV light or infrared light, or may be a resin that foams by heat. When a resin that can be peeled off by UV light or infrared light is used, the support 105 is irradiated with UV light or infrared light from the surface opposite to the side on which the peeling layer 106 is provided, and the second wiring board is used. The support 105 is peeled off from the joint between the (interposer) 103 and the first wiring board (FC-BGA wiring board) 101 and removed. In this case, the support 105 needs to have transparency, and glass can be used, for example.

The glass has excellent flatness and is suitable for forming a fine pattern of the second wiring board (interposer) 103. Further, since glass has a small CTE and is not easily distorted, it is excellent in ensuring pattern arrangement accuracy and flatness when joined to the first wiring board (FC-BGA wiring board) 101. When glass is used as the support 105, the thickness of the glass is preferably thick from the viewpoint of suppressing the occurrence of warpage in the manufacturing process, and for example, the thickness is preferably 0.7 mm or more and 1.1 mm or less. Further, the coefficient of linear expansion (CTE) of glass is 3 ppm / ° C. or higher and 15 ppm / ° C. or lower, and 9 ppm from the viewpoint of the coefficient of linear expansion (CTE) of the FC-BGA wiring board and the semiconductor chip. About / ° C is desirable. Here, for example, glass is used as the support 105.

On the other hand, when a resin that foams by heat is used for the release layer 106, the support is supported by heating the joint between the second wiring board (interposer) 103 and the first wiring board (FC-BGA wiring board) 101. Remove 105. In this case, the support 105 can be made of metal or ceramics having less distortion.

Then, as shown in FIG. 12C, a seed layer 111 is formed on the protective layer 107 in vacuum. Regarding the composition of the seed layer, titanium (Ti) / copper (Cu), chromium (Cr) / copper (Cu), chromium nickel (NiCr) / copper (Cu), etc. can be appropriately configured and the thickness can be changed according to the application. be. For example, the seed layer 111 can be formed from titanium (Ti): 50 nm and copper (Cu): 300 nm. By forming the seed layer 111 on the protective layer 107, it is possible to form a fine pattern on the seed layer 111.

Next, as shown in FIG. 12D, a resist pattern 113 is formed on the seed layer 111, and a conductor layer 114 is formed in the opening 113a by electrolytic plating. For example, Cu is formed as the conductor layer 114. After that, the resist pattern 113 is removed as shown in FIG. 12E.

Next, as shown in FIG. 12F, the photosensitive insulating resin layer 115 is formed on the conductor layer 114 and the seed layer 111. The photosensitive insulating resin layer 115 is formed so that the conductor layer 114 is embedded in the layer of the photosensitive insulating resin layer 115. For example, it can be formed by a spin coating method using an epoxy resin as the photosensitive insulating resin. The photosensitive epoxy resin can be cured at a relatively low temperature, has less shrinkage due to curing after the formation of conductive vias, and is excellent in subsequent fine pattern formation. The photosensitive insulating resin layer 115 can be formed by a spin coating method using a photosensitive epoxy resin, or can be formed by compressing and curing an insulating resin film with a vacuum laminator. In this case, it is flat. An insulating film having good properties can be formed. Polyimide may be used as the insulating resin as long as some steps can be tolerated in the exposure process.

Next, as shown in FIG. 12G, an opening 115a is provided on the conductor layer 114 by photolithography. The opening 115a may be subjected to plasma treatment for the purpose of removing residues during development.

Next, as shown in FIG. 12H, a seed layer 118 is provided on the surface of the opening 115a. Regarding the composition of the seed layer, titanium (Ti) / copper (Cu), chromium (Cr) / copper (Cu), chromium nickel (NiCr) / copper (Cu), etc. can be appropriately configured and the thickness can be changed according to the application. be. For example, the seed layer 118 can be formed from titanium (Ti): 50 nm and copper (Cu): 300 nm.

Next, as shown in FIG. 12I, a resist pattern 119 is formed on the seed layer 118, and a conductor layer 120 is formed in the opening 119a by electroplating. For example, copper (Cu) is formed as the conductor layer 120. Then, as shown in FIG. 12J, the resist pattern 119 is removed, and the unnecessary seed layer 118 is removed by etching.

Next, the steps of FIGS. 12F to 12J are repeated to obtain a substrate on which the multilayer wiring pattern shown in FIG. 12K is formed. As described above, it is possible to form a wiring layer in which the surface on the release layer 106 side becomes the first pad and the surface opposite to the release layer 106 becomes the second pad (wiring layer forming step).

The photosensitive insulating resin layer 115 may be a positive type or a negative type.

Next, as shown in FIG. 12L, the insulating resin layer 123 is formed on the outermost surface of the second wiring board (interposer) 103 on the first wiring board (FC-BGA wiring board) 101 side. The insulating resin layer 123 is formed so as to cover the conductor layer 122 and the photosensitive insulating resin layer 115, and an opening 123a is formed in the insulating resin layer 123 so that the conductor layer 122 is exposed by exposure and development. For example, a photosensitive epoxy resin is used as the insulating resin to form the insulating resin layer 123. The insulating resin may be the same material as the photosensitive insulating resin layer 115.

Next, as shown in FIG. 12M, a surface treatment layer 124 is provided in order to prevent oxidation of the surface of the conductor layer 122 and improve the wettability of the solder bumps. In this embodiment, electroless nickel (Ni) / palladium (Pd) / gold (Au) plating is formed as the surface treatment layer 124. An OSP (Organic Soiderability Preservative, surface treatment with a water-soluble preflux) film may be formed on the surface treatment layer 124. Further, electroless tin plating, electroless nickel (Ni) / gold (Au) plating and the like may be appropriately selected and used according to the intended use.

Next, as shown in FIG. 12N, a solder bump is mounted on the surface treatment layer 124 as a protrusion electrode 125 and reflowed to form a protrusion electrode on the surface of the second pad (protrusion electrode forming step) to form a support. The second wiring board (interposer) with 105 is completed.

Next, in order from FIG. 13A to FIG. 13G, the joining process and sealing of the second wiring board (interposer) 103 with the support 105 and the first wiring board (FC-BGA wiring board) 101 according to the present embodiment are performed. An example of a series of manufacturing processes including filling and injecting the resin 102, peeling the support 105, exposing the pad of the wiring board, and mounting the semiconductor chip will be described.

As shown in FIG. 13A, the first wiring board (FC-BGA wiring board) designed and manufactured according to the position of the terminal of the second wiring board (interposer) 103 with the support 105, that is, the protruding electrode (solder bump) 125. ) 101, a second wiring board (interposer) 103 with a support 105 is arranged by a flip chip. Next, as shown in FIG. 13B, the protruding electrode 125 of the second wiring board (interposer) 103 with the support 105 and the first wiring board pad of the first wiring board (FC-BGA wiring board) 101 are electrically connected. Join (electrical joining process).

Next, as shown in FIG. 13C, the sealing resin 102 is injected into the gap between the first wiring board (FC-BGA wiring board) 101 and the second wiring board (interposer) 103 to protect the solder joint (soldering joint). Sealing resin filling injection process). The injection amount of the sealing resin 102 may be appropriately set from the volume of the gap between the first wiring board (FC-BGA wiring board) 101 and the second wiring board (interposer) 103. However, preferably, the height of the sealing resin 102 is set to 1.2 times or more the volume of the gap between the first wiring board (FC-BGA wiring board) 101 and the second wiring board (interposer) 103. It can be formed higher than the bi-wiring board (interposer) 103.

At this time, the sealing resin 102 travels up to the side surface of the support 105 via the side surface of the second wiring board (interposer) 103, the seed layer 111, the protective layer 107, and the side surface of the release layer 106 due to wetting. Although the figure shows that the upper end of the sealing resin 102 is sharp, it may actually be rounded to some extent.

Further, in order to improve the peelability of the support 105, the support 105 may be subjected to a repellent underfill treatment. Examples of the repellent underfill treatment include fluorine coating and silicone coating treatment, which may be appropriately set according to the intended use.

Next, as shown in FIG. 13D, the laser beam 126 is applied to the support 105 from the back surface of the support 105, that is, from the surface of the support 105 opposite to the first wiring board (FC-BGA wiring board) 101. The release layer 106 formed at the interface is irradiated with the permeated layer 106, and the support 105 is peeled off together with the release layer 106 as shown in FIG. 13E (support release step).
The sealing resin filling / injecting step may not be performed before the support peeling step, and the sealing resin filling / injecting step may be performed after the support peeling step.

Next, the release layer 106, the protective layer 107, and the seed layer 111 are removed, that is, the pad 140 of the wiring board is exposed (pad exposure step) to obtain a wiring board as shown in FIG. 13F. For example, the release layer 106 can be mechanically peeled off from the protective layer 107. When an acrylic resin is used as the protective layer 107, it is removed with an alkaline solvent (1% sodium hydroxide (NaOH)) and 2.3% tetramethylammonium hydroxide (TMAH). Further, the seed layer 111 is removed. , Titanium (Ti) and copper (Cu) are used from the protective layer 107 side, and the wiring substrate CB100 is obtained by dissolving and removing them with an alkaline etching agent and an acid etching agent, respectively.

In the wiring substrate CB100, as described above, electroless nickel (Ni) / palladium (Pd) / gold (Au) plating, OSP (Organic Soiderability Preservative, surface treatment with water-soluble preflux), Surface treatments such as electroless tin (Sn) plating and electroless nickel (Ni) / gold (Au) plating may be performed.

Finally, as shown in FIG. 13G, the semiconductor device SD100 can be manufactured by connecting the semiconductor chip 104 to the wiring board CB100 and filling the gap between the wiring board CB100 and the semiconductor chip 104 with the sealing resin 132. ..
At this time, the sealing resin 102 does not come into contact with the surface of the second wiring board 103 opposite to the surface to be joined to the first wiring board 101.

By protecting the entire side surface of the joint between the first wiring board (FC-BGA wiring board) and the second wiring board (interposer) with a sealing resin, and making the height of the sealing resin higher than that of the second wiring board. , Stress concentration due to the difference in linear expansion coefficient of each member is relaxed, which makes it possible to provide a wiring board with improved mountability and joining reliability.

(Third Embodiment)
Hereinafter, a wiring board according to an embodiment of the present invention will be described with reference to the drawings. However, in each of the figures described below, the parts corresponding to each other are designated by the same reference numerals, and the description below will be omitted as appropriate in the overlapping parts. In addition, each drawing is exaggerated as appropriate for ease of explanation.

Further, the embodiment of the present invention exemplifies a configuration for embodying the technical idea of the present invention, and specifies the material, shape, structure, arrangement, dimensions, etc. of each part as follows. Not. The technical idea of the present invention may be modified in various ways within the technical scope specified by the claims stated in the claims.

FIG. 14 is a cross-sectional view showing an example of a semiconductor package in which a semiconductor chip is mounted on the wiring board according to the present embodiment. FIG. 15 is a cross-sectional view showing a wiring board before mounting a semiconductor chip.

The semiconductor package according to the present embodiment includes a thin interposer 203 having a fine wiring layer formed only of a build-up wiring layer in which resin and wiring are laminated on one surface of the FC-BGA wiring board 201. It is electrically connected by an electrode 211 composed of solder bumps or copper (Cu) posts (Cu pillars) or gold bumps. Further, the gap between the FC-BGA wiring board 201 and the interposer 203 is filled with the sealing resin (first sealing resin) 202 as an insulating adhesive member, and the sealing resin (1st sealing resin) 202 is covered with the sealing resin 202. It is filled with 242 (second sealing resin). The sealing resin 242 preferably covers at least the boundary between the interposer 203 and the sealing resin 202.
Further, the semiconductor chip 204 is joined to the surface of the interposer 203 opposite to the FC-BGA wiring board 201 by an electrode 231 made of solder bumps or Cu pillars or gold bumps, and the gap between the semiconductor chip 204 and the interposer 203 is closed. It is filled with a waterproof resin 232.

The sealing resins 202 and 242 are adhesives used for fixing and sealing the FC-BGA wiring board 201 and the interposer 203. Examples of the sealing resin 202 and 242 include silica as a filler in a resin obtained by mixing one of epoxy resin, polyurethane resin, silicon resin, polyester resin, oxetane resin, and maleimide resin, or two or more of these resins. , Titanium oxide, aluminum oxide, magnesium oxide, zinc oxide and the like are added to the material.

The sealing resin 202 and 242 may be formed by filling with a liquid resin. Further, an anisotropic conductive film (ACF: Anisotropic Conductive Film) as an insulating adhesive member, or a non-conductive film (NCF: Non Conductive Film) which is a film-like connecting material having both adhesive and insulating functions is sealed. By using it as the resin 202, the FC-BGA wiring board 201 and the interposer 203 may be fixed and sealed between them.

The sealing resin 232 is an adhesive used for fixing and sealing the semiconductor chip 204 and the interposer 203, and is made of the same material as the sealing resins 202 and 242. In this case as well, an anisotropic conductive film (ACF) or a non-conductive film (NCF) which is a film-like connecting material may be used instead of the sealing resin 232.

The wiring pitch (wiring width and distance between wirings) of the portion of the interposer 203 joined to the semiconductor chip 204 is the semiconductor of the FC-BGA wiring board 201 when the semiconductor chip 204 and the FC-BGA wiring board 201 are directly connected. It is narrower than the wiring pitch (wiring width and distance between wirings) of the portion connected to the chip 204. That is, the surface of the interposer 203 on which the semiconductor chip 204 is mounted has finer wiring than the FC-BGA wiring board 201 when the interposer 203 is joined to the semiconductor chip 204.

For example, in order to support the use of the current high bandwidth memory (HBM: High Bandwidth Memory), it is necessary to set the wiring width of the interposer 203 to 2 μm or more and 6 μm or less. In particular, in order to match the impedance to 50Ω, when the wiring width is 2 μm and the wiring height is 2 μm, the insulating film thickness between the wirings is 2.5 μm. The thickness of one layer including wiring is 4.5 μm, and when a five-layer interposer is created with this thickness, the interposer 203 is an ultra-thin interposer with a total thickness of about 25 μm.

Generally, the FC-BGA wiring board 201 is rigid, and if there is a CTE (Coefficient of Thermal Expansion) difference from the interposer 203, the joint is likely to break. Therefore, in order to protect the joint portion, the gap between the FC-BGA wiring board 201 and the interposer 203 is filled with the sealing resin 202. In addition, the sealing resin 202 gets wet and forms a portion called a fillet on the side surface portion of the interposer 203. Due to the difference in CTE (coefficient of thermal expansion) between the interposer 203 and the sealing resin 202, stress is concentrated on the fillet end due to the use of the sealing resin, causing peeling and cracking on the side surface of the interposer 203, resulting in reduced reliability. do.

Therefore, by forming the sealing resin 242 so as to cover the sealing resin 202, the stress concentrated on the fillet end can be relaxed and high reliability can be obtained. As the sealing resin 242, a resin having an elastic modulus, CTE (coefficient of thermal expansion), or both values between the sealing resin 202 and the interposer 203 is used.

Next, an example of a manufacturing process of the wiring board CB100 provided with the interposer 203 according to the present embodiment will be described with reference to FIGS. 18A to 19C.

Solder is pre-formed on the connection electrodes of the interposer 203 and the FC-BGA wiring board 201. As the solder material, an alloy composed of 96.5 wt% Sn, 3.0 wt% Ag and 0.5 wt% Cu is used. However, the solder material is not limited to this, and for example, a binary system containing silver, copper, indium, antimony, etc., or a ternary system or more solder alloy may be used. Further, as long as it is conductive, it is not limited to solder particles, and other metal particles may be used. Further, the particle shape is not limited to the spherical shape, and other shapes such as granular, flaky, and square may be used.

Flux (not shown) is applied to the area on the FC-BGA wiring board 201 where the electrode terminals 224 connected to the interposer 203 are arranged. The flux agent has, for example, at least one acid selected from the aggregate consisting of (meth) acrylic acid, maleic acid, oxalic acid, malonic acid, citric acid, trimellitic acid, and tetramellitic acid, and a chelating agent. Etc. can be used.

As shown in FIG. 18A, the interposer 203 is supported by a head (not shown) so that the electrode terminals 234 and the electrode terminals 224 arranged on the surface of the interposer 203 corresponding to the surface of the FC-BGA wiring board 201 correspond to each other. Align. Then, the interposer 203 is lowered until it hits the FC-BGA wiring board 201. This completes the placement of the interposer 203. Further, heating is performed at a temperature higher than the melting point of the solder, and the solder is melt-bonded to form the electrode 211, and the electrical connection between the FC-BGA wiring board 201 and the interposer 203 is completed. Become. Here, reference numeral 212 indicates wiring, and reference numeral 213 indicates an insulating layer.

The flux between the FC-BGA wiring board 201 and the interposer 203 is removed by cleaning. Since there is also a low-residue type of flux, it is not always necessary to remove it, but it is desirable to remove it because it causes voids in the sealing resin described later and reduces reliability.

A gap is created between the FC-BGA wiring board 201 and the interposer 203 based on the height of the electrode 211. An uncured thermosetting resin composition (liquid resin) to be a sealing resin 202 is injected into the gap between the FC-BGA wiring substrate 201 and the interposer 203, and this is cured and cured. As a result, a sealing resin 202 made of a thermosetting resin is formed (see the first sealing resin sealing step, FIG. 18C). In this way, the interposer 203 is fixed to the FC-BGA wiring board 201 while protecting the electrode 211 with the sealing resin 202.
The first sealing resin sealing step includes a step of dropping the sealing resin 202 onto the main surface of the FC-BGA wiring board 201, and mounting the interposer 203 on the FC-BGA wiring board 201 and simultaneously with the FC-BGA board 201. It is preferable to include a step of filling the gap between the interposers 203. Alternatively, the first sealing resin sealing step includes the step of installing the insulating film-like resin on the main surface of the FC-BGA wiring board 201 and the step of mounting the interposer 203 on the FC-BGA wiring board 201 at the same time. It may include a step of filling the gap between the FC-BGA wiring board 201 and the interposer 203.
Further, an uncured thermosetting resin composition (liquid resin) to be the sealing resin 242 is applied along the sealing resin 202 arranged on the side surface of the interposer 203, cured, and cured. A sealing resin 242 made of a thermosetting resin is formed (second sealing resin sealing step).
In the above process, the wiring board CB100 as shown in FIG. 18D (FIG. 15) is formed.

The semiconductor chip 204 is placed on the interposer 203 side of the wiring board CB100 via an electrode terminal (not shown) and an electrode terminal (not shown) formed on the side of the semiconductor chip 204 facing the wiring board CB100. Electrodes 231 are formed by applying heating above the melting temperature of the solder to melt-bond them, and the electrical connection between the wiring board CB100 and the semiconductor chip 204 is completed.

A gap is created between the semiconductor chip 204 and the interposer 203 based on the height of the electrode 231. An uncured thermosetting resin composition (liquid resin) to be a sealing resin 232 is injected into the gap between the semiconductor chip 204 and the interposer 203, and this is cured and cured. A sealing resin 232 made of a thermosetting resin is formed (see FIG. 18E).
Further, by forming the electrode terminal 233 on the pad on the opposite surface of the semiconductor chip 204 mounting surface of the wiring board CB100, the semiconductor package as shown in FIG. 14 can be produced.

In one example of this embodiment, the electrode terminal 233 is formed by solder paste, but the present invention is not limited to this. For example, a solder ball may be formed as the electrode terminal 233 by a melt forming method, or Cu, Al, or gold may be used alone. Metal pins formed of a single metal or made of a composite material can be used.

As described above, according to the uniform state of the present invention, as shown in FIG. 14, the sealing resin 202 is formed in the gap between the FC-BGA wiring board 201 and the interposer 203 and a part of the side surface portion of the interposer 203. Will be done. Further, by forming the sealing resin 242 over the side surface portion of the interposer 203 so as to cover the sealing resin 202, the stress applied to the end portion of the sealing resin 202 formed on the side surface portion of the interposer 203 is relaxed and the sealing resin 202 is sealed. It is possible to suppress cracks and peeling from the end of the stop resin 202 as a base point.

According to the uniform state of the present invention, by changing the position of the end portion of the sealing resin 242 at the contact portion between the side surface of the interposer 203 and the sealing resin 242, the stress received by the side surface of the interposer 203 from the end portion of the sealing resin 242 is applied. You can control the position. For example, as shown in FIG. 16, when the laminated interface of the interposer 203 is vulnerable to external stress, peeling and cracking from the side surface of the interposer 203 can be suppressed by covering the entire side surface of the interposer 203 with the sealing resin 242.

Further, by selecting the material of the sealing resin 242 so that the linear expansion coefficient A2 of the sealing resin 242 is between the linear expansion coefficient A3 of the interposer 203 and the linear expansion coefficient A1 of the sealing resin 202, the interposer 203 The stress relaxation effect from the end portion of the sealing resin 202 applied to the side surface portion of the above can be effectively obtained.
Here, the coefficient of linear expansion A1 of the sealing resin 202 is 18 to 35 ppm / ° C. (preferably 29 ppm / ° C.) below the glass transition point Tg, and 65 to 125 ppm / ° C. (preferably) above the glass transition point Tg. Is 110 ppm / ° C.). On the other hand, the coefficient of linear expansion A3 of the interposer 203 is a general value of the organic resin used. Therefore, the coefficient of linear expansion A2 of the sealing resin 242 can be appropriately selected so as to be between the coefficients of linear expansion A1 and A3.

Further, by selecting the material of the sealing resin 242 so that the elastic modulus B2 of the sealing resin 242 is between the elastic modulus B3 of the interposer 203 and the elastic modulus B1 of the sealing resin 202, the side surface of the interposer 203 is formed. The stress relaxation effect from the two ends of the sealing resin applied to the portion can be effectively obtained.
Here, the elastic modulus B1 of the sealing resin 202 is 6.5 to 13.5 GPa (preferably 9.5 GPa) below the glass transition point Tg, and 0.03 to 0. It is 33 GPa (preferably 0.12 GPa). On the other hand, the elastic modulus B3 of the interposer 203 is a general value of the organic resin used. Therefore, the elastic modulus B2 of the sealing resin 242 can be appropriately selected so as to be between the elastic moduli B1 and B3.

(Fourth Embodiment)
The fourth embodiment will be described below. FIG. 17 is a cross-sectional view showing an example of the wiring board according to the present embodiment. In this embodiment, the fillet shape of the sealing resin 242 is different from that in the third embodiment. The points other than the fillet shape of the sealing resin 242 can be the same as those in the third embodiment, and thus the description thereof will be omitted.

After forming the sealing resin 202 of the third embodiment, as shown in FIG. 19A, a removable frame 220 is formed on the outer periphery of the fillet of the sealing resin 202. The thickness of the frame 220 at this time is preferably higher than that of the mounted interposer 203. For the frame 220, for example, a photosensitive dry film resist can be used because of the ease of patterning and removal.

Subsequently, as shown in FIG. 19B, an uncured thermosetting resin composition (liquid resin) to be a sealing resin 242 was injected into the gap between the frame 220 and the interposer 203, and this was cured. Let it cure. Further, by removing the frame 220, a sealing resin 242 made of a thermosetting resin as shown in FIG. 19C is formed in contact with the side surface of the interposer 203.

According to the present embodiment, by using the frame 220, the dimension (thickness) in the plane direction of the sealing resin 242 located in the plane direction of the interposer 203 from the side surface of the interposer 203 can be made uniform over the entire circumference. .. As a result, the stress in the plane direction generated by the temperature change between the interposer 203 and the sealing resin 242 becomes uniform over the thickness direction of the interposer 203. Therefore, the gradient of stress received from the sealing resin 242 on the side surface of the interposer 203 due to the temperature change can be reduced, and the reliability can be improved. Further, it is preferable that the height of the sealing resin 242 is made uniform over the entire circumference.

Further, according to the present embodiment, the material of the interposer 203 is not specified, a resin insulating layer containing an organic material may be used, an insulating layer containing silicon Si may be used, and an insulating layer containing ceramic is used. However, the effect of the present invention can be obtained.

Further, according to the present embodiment, the combination to be mounted is not limited to the FC-BGA wiring board 201 and the interposer 203, but may be the FC-BGA wiring board 201 and the semiconductor chip 204, the interposer 203 and the semiconductor chip 204, and the semiconductor chip 204 may be mounted. The effects of the present invention can also be obtained with the mounted wiring board and semiconductor device.

Although the embodiments of the present invention have been illustrated above, the present invention is not limited to the above embodiments, and as long as the technical idea of the embodiments of the present invention does not deviate, the present invention is required in consideration of the use as a wiring substrate. Needless to say, other layers and structures can be arbitrarily formed for the purpose of improving other physical properties such as rigidity, strength, and impact resistance.

The present invention can be used in a semiconductor device including a wiring board in which an interposer is interposed between a main board and a semiconductor chip.

1 ... FC-BGA wiring board, 2, 42, 52 ... underfill, 3 ... interposer, 4 ... semiconductor chip, 5 ... support, 6 ... peeling layer, 7 ... .. Protective layer, 11 ... Seed layer, 13 ... Resist pattern, 13a ... Resist pattern opening, 14 ... Conductor layer, 15 ... Photosensitive insulating resin layer, 15a ... Opening Part, 18 ... seed layer, 19 ... resist pattern, 20 ... conductor layer, 21 ... conductor layer, 22 ... conductor layer, 23 ... insulating resin layer, 23a ... opening Part, 24 ... Surface treatment layer, 25 ... Solder bump, 26 ... YAG laser beam, 30 ... Copper pillar, 32 ... Underfill, CB100 wiring board, SD100 semiconductor device, 101 ...・ First wiring board (FC-BGA wiring board), 102 ・ ・ ・ sealing resin, 103 ・ ・ ・ second wiring board (interposer), 104 ・ ・ ・ semiconductor chip, 105 ・ ・ ・ support, 106 ・ ・-Release layer, 107 ... Protective layer, 111 ... Seed layer, 113 ... Resist pattern, 113a ... Resist pattern opening, 114 ... Conductor layer, 115 ... Photosensitive insulating resin layer , 115a ... opening, 118 ... seed layer, 119 ... resist pattern, 119a ... opening, 120 ... conductor layer, 121 ... conductor layer, 122 ... conductor layer, 123 ... Insulation resin layer, 123a ... Opening, 124 ... Surface treatment layer, 125 ... Projection electrode, 126 ... YAG laser light, 131 ... Copper pillar, 132 ... Seal Stop resin, 201 ... FCBGA wiring board, 202 ... Sealing resin, 203 ... Interposer, 204 ... Semiconductor chip, 211 ... Electrode, 212 ... Wiring, 213 ... Insulation Layer, 220 ... frame, 224 ... electrode terminal, 231 ... electrode, 232 ... sealing resin, 233 ... electrode terminal, 234 ... electrode terminal, 242 ... sealing resin , 251 ... electrode terminal, 252 ... electrode terminal,

Claims (25)

A wiring board for semiconductor devices for mounting semiconductor chips.
Equipped with a first wiring board and a second wiring board,
The first wiring board and the second wiring board are electrically joined via a protruding electrode.
The gap between the first wiring board and the second wiring board is filled with a sealing resin, and the sealing resin is used for the entire side surface of the second wiring board and the second wiring board for the first wiring. A wiring board for a semiconductor device, characterized in that it covers the peripheral edge of a surface opposite to the surface to be joined to the substrate. A process of sequentially forming a release layer, a protective layer, a seed layer, and a second wiring board on the support, and
The process of electrically joining the second wiring board and the first wiring board,
A step of sequentially peeling the support, the peeling layer, the protective layer, and the seed layer,
The gap between the first wiring board and the second wiring board is filled with a sealing resin, and the sealing resin makes the entire side surface of the second wiring board and the second wiring board with the first wiring board. A method for manufacturing a wiring board for a semiconductor device, which comprises a step of covering the peripheral portion of a surface opposite to the surface to be joined. The wiring board for a semiconductor device according to claim 1,
A semiconductor device characterized in that the second wiring board has a semiconductor chip mounted on a surface opposite to a surface to be joined to the first wiring board. The first wiring board and
A second wiring board joined on one surface of the first wiring board is provided.
The first wiring board and the second wiring board are electrically bonded via the protruding electrodes.
The gap between the first wiring board and the second wiring board is filled with an insulating sealing resin.
The sealing resin is continuous from the gap between the first wiring board and the second wiring board, covers the entire side surface of the second wiring board, and is connected to the first wiring board of the second wiring board. Extends beyond the surface opposite to the surface to be joined,
The second wiring board is a wiring board for a semiconductor device, characterized in that the second wiring board has a pad on a surface opposite to the surface to be joined to the first wiring board side. The wiring board for a semiconductor device according to claim 4, wherein the sealing resin does not come into contact with a surface of the second wiring board opposite to the surface to be joined to the first wiring board. The wiring board for a semiconductor device according to claim 4 or 5, wherein the distance between the wirings of the wiring provided by the second wiring board is smaller than the distance between the wirings of the wiring provided by the first wiring board. The wiring board for a semiconductor device according to any one of claims 4 to 6, wherein the second wiring board is made of a member containing an organic material. The wiring board for a semiconductor device according to any one of claims 4 to 7, wherein the second wiring board is made of a member containing Si. The wiring board for a semiconductor device according to any one of claims 4 to 8.
A semiconductor device comprising a semiconductor chip mounted on a surface of the second wiring board opposite to a surface to be joined to the first wiring board. A release layer forming step of forming a release layer on one surface of the support,
A wiring layer for producing a second wiring board with a support by forming a wiring layer on the release layer in which the surface on the release layer side serves as the first pad and the surface opposite to the release layer serves as the second pad. The formation process and
A protrusion electrode forming step of forming a protrusion electrode on the surface of the second pad,
An electrical joining step of electrically joining the first wiring board pad of the first wiring board and the protruding electrode of the second wiring board.
From the gap between the first wiring board and the second wiring board, the entire side surface of the second wiring board is covered with the outside of the gap, and the surface of the second wiring board to be joined to the first wiring board. A sealing resin filling and injecting step of filling and injecting an insulating sealing resin so as to extend beyond the opposite side surface.
A support peeling step of peeling the support and the peeling layer from the second wiring board,
A method for manufacturing a wiring board for a semiconductor device, which comprises a pad exposure step of exposing the first pad as a connection pad. The method for manufacturing a wiring board for a semiconductor device according to claim 10, wherein the support peeling step is executed after the sealing resin filling / injecting step. The method for manufacturing a wiring board for a semiconductor device according to claim 10, further comprising the sealing resin filling / injecting step after the support peeling step. The method for manufacturing a wiring board for a semiconductor device according to any one of claims 10 to 12, wherein the support is a glass substrate. The first wiring board and
With the second wiring board joined on one surface of the first wiring board,
The first sealing resin that seals the gap between the first wiring board and the second wiring board,
A wiring board for a semiconductor device, comprising at least a second sealing resin formed so as to cover a boundary between a side surface of the second wiring board and the first sealing resin. The wiring board for a semiconductor device according to claim 14, wherein the dimensions of the wiring width and the distance between the wirings of the second wiring board are smaller than the dimensions of the wiring width and the distance between the wirings of the first wiring board. 14. The linear expansion coefficient A2 of the second sealing resin is between the linear expansion coefficient A1 of the first sealing resin and the linear expansion coefficient A3 of the second wiring substrate. Alternatively, the wiring substrate for a semiconductor device according to 15. A 14th to 16th claims, wherein the elastic modulus B2 of the second sealing resin is between the elastic modulus B1 of the first sealing resin and the elastic modulus B3 of the second wiring substrate. The wiring substrate for a semiconductor device according to any one of the items. The wiring board for a semiconductor device according to any one of claims 14 to 17, wherein the second sealing resin covers the entire side surface of the second wiring board. The semiconductor according to any one of claims 14 to 18, wherein at least one of the wall thickness and the height of the portion of the second sealing resin formed on the side surface of the second wiring board is uniform. Wiring board for equipment. The wiring board for a semiconductor device according to any one of claims 14 to 19, wherein the second wiring board is made of a member containing an organic material. The wiring board for a semiconductor device according to any one of claims 14 to 20, wherein the second wiring board is made of a member containing ceramic. The wiring board for a semiconductor device according to any one of claims 14 to 21, wherein the second wiring board is made of a member containing Si. The first sealing resin sealing step of sealing the gap between the first wiring board and the second wiring board with the first sealing resin,
A semiconductor device comprising at least a second sealing resin sealing step of forming a second sealing resin so as to cover a boundary between a side surface of the second wiring board and the first sealing resin. Manufacturing method of wiring board for resin. The first sealing resin sealing step includes a step of dropping the first sealing resin onto the main surface of the first wiring board and the first mounting of the second wiring board on the first wiring board at the same time. The method for manufacturing a wiring board for a semiconductor device according to claim 23, wherein the step of filling the gap between the wiring board and the second wiring board is included. The first sealing resin sealing step includes a step of installing the first sealing resin in the form of an insulating film on the main surface of the first wiring board and the second wiring board of the first wiring board. The method for manufacturing a wiring board for a semiconductor device according to claim 23, further comprising a step of filling a gap between the first wiring board and the second wiring board at the same time as mounting the wiring board.

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