JPWO2019195435A5 - - Google Patents
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- JPWO2019195435A5 JPWO2019195435A5 JP2020554400A JP2020554400A JPWO2019195435A5 JP WO2019195435 A5 JPWO2019195435 A5 JP WO2019195435A5 JP 2020554400 A JP2020554400 A JP 2020554400A JP 2020554400 A JP2020554400 A JP 2020554400A JP WO2019195435 A5 JPWO2019195435 A5 JP WO2019195435A5
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- 239000004065 semiconductor Substances 0.000 claims 19
- 239000000758 substrate Substances 0.000 claims 19
- 238000005530 etching Methods 0.000 claims 9
- 229920002120 photoresistant polymer Polymers 0.000 claims 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N Silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 8
- 239000007800 oxidant agent Substances 0.000 claims 7
- 230000001590 oxidative Effects 0.000 claims 7
- 239000011248 coating agent Substances 0.000 claims 5
- 238000000576 coating method Methods 0.000 claims 5
- 239000002019 doping agent Substances 0.000 claims 5
- 238000000151 deposition Methods 0.000 claims 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 4
- 239000001301 oxygen Substances 0.000 claims 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N oxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims 3
- 229910052760 oxygen Inorganic materials 0.000 claims 3
- 238000001020 plasma etching Methods 0.000 claims 3
- 210000002381 Plasma Anatomy 0.000 claims 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims 2
- 239000012159 carrier gas Substances 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 claims 2
- 230000003647 oxidation Effects 0.000 claims 2
- 238000007254 oxidation reaction Methods 0.000 claims 2
- 235000012239 silicon dioxide Nutrition 0.000 claims 2
- 239000000377 silicon dioxide Substances 0.000 claims 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N Fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims 1
- 229910052786 argon Inorganic materials 0.000 claims 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 1
- 229910052799 carbon Inorganic materials 0.000 claims 1
- 229910052731 fluorine Inorganic materials 0.000 claims 1
- 239000011737 fluorine Substances 0.000 claims 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims 1
- 239000008246 gaseous mixture Substances 0.000 claims 1
- 239000001257 hydrogen Substances 0.000 claims 1
- 229910052739 hydrogen Inorganic materials 0.000 claims 1
- 150000002431 hydrogen Chemical class 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
Claims (20)
半導体基板上に第１の厚さを有する２酸化シリコンの第１の誘電体層を形成することと、
前記第１の誘電体層上に障壁層を堆積することと、
前記障壁層上に反射防止コーティングを堆積することと、
フォトレジスト層を堆積することと、
前記フォトレジスト層におけるパターンを放射に曝すことと、
前記フォトレジスト層に開口を提供するために前記パターンに従って前記フォトレジスト層をエッチングすることと、
前記フォトレジスト層における開口の下の前記反射防止コーティングの一部をエッチングすることと、
前記第１の誘電体層の一部を露出させるために前記開口の下の前記障壁層の一部をエッチングすることと、
前記第１の誘電体層の露出された一部の前記第１の厚さを第２の厚さに選択的に増加させて酸化物領域を成長させるために、前記開口の下の前記障壁層の一部をエッチングすることの後に雰囲気酸化剤を提供することと、
前記雰囲気酸化剤を提供することの後に前記障壁層を除去することと、
前記障壁層を除去することの後に前記半導体基板内にドーパントを注入することと、
前記半導体基板にドーパントを注入することの後に前記酸化物領域の横方向の広がりの外側の前記第１の誘電体層を除去することによって前記半導体基板の露出された一部を形成することと、
前記第１の誘電体層を除去することの後に、前記半導体基板の露出された領域上に第３の厚さを有する２酸化シリコンの第２の誘電体層を形成することであって、前記酸化物領域の第２の厚さが前記第２の誘電体層の第３の厚さよりも大きい、前記第２の誘電体層を形成すことと、
前記酸化物領域と前記第２の誘電体層との上に第１のゲート電極を形成することと、
を含む、方法。 It ’s a method of manufacturing transistors.
Forming a first dielectric layer of silicon dioxide with a first thickness on a semiconductor substrate,
By depositing a barrier layer on the first dielectric layer ,
By depositing an antireflection coating on the barrier layer ,
Placing a photoresist layer and
Exposing the pattern in the photoresist layer to radiation and
Etching the photoresist layer according to the pattern to provide an opening in the photoresist layer.
Etching a portion of the antireflection coating under the opening in the photoresist layer and
Etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer.
The barrier layer below the opening in order to selectively increase the first thickness of the exposed portion of the first dielectric layer to the second thickness to grow the oxide region. To provide an atmospheric oxidizer after etching a portion of the
Removing the barrier layer after providing the atmospheric oxidant ,
After removing the barrier layer, injecting a dopant into the semiconductor substrate
By injecting a dopant into the semiconductor substrate and then removing the first dielectric layer outside the lateral extent of the oxide region to form an exposed portion of the semiconductor substrate. ,
After removing the first dielectric layer, a second dielectric layer of silicon dioxide having a third thickness is formed on the exposed region of the semiconductor substrate . To form the second dielectric layer in which the second thickness of the oxide region is larger than the third thickness of the second dielectric layer.
Forming a first gate electrode on the oxide region and the second dielectric layer,
Including the method.
前記半導体基板上に第３の誘電体層を形成することであって、前記第３の誘電体層が前記第２の誘電体層よりもより厚い、前記第３の誘電体層を形成することと、
前記第３の誘電体層の上に第２のゲート電極を形成することと、
を更に含む、方法。 The method of claim 1
Forming the third dielectric layer on the semiconductor substrate , wherein the third dielectric layer is thicker than the second dielectric layer. And ,
Forming a second gate electrode on the third dielectric layer and
Further including, methods.
前記雰囲気酸化剤を提供することが、約９００℃より高い温度で前記半導体基板を前記雰囲気酸化剤に曝すことを含む、方法。 The method of claim 1
A method of providing the atmospheric oxidant comprising exposing the semiconductor substrate to the atmospheric oxidant at a temperature above about 900 ° C.
前記酸化剤が酸素又は蒸気を含む、方法。 The method of claim 1
A method in which the oxidant comprises oxygen or vapor.
前記雰囲気酸化剤を提供することが、前記半導体基板の中と前記半導体基板上とに前記酸化物領域を少なくとも４００オングストロームの厚みまで成長させることを含む、方法。 The method of claim 1
A method comprising providing the atmospheric oxidant to grow the oxide region in and on the semiconductor substrate to a thickness of at least 400 angstroms.
前記前記障壁層が３００オングストローム～１０００オングストロームの厚みを有する、方法。 The method of claim 1
The method, wherein the barrier layer has a thickness of 300 angstroms to 1000 angstroms.
前記前記障壁層がシリコン窒化物を含む、方法。 The method of claim 1
A method in which the barrier layer comprises silicon nitride.
前記反射防止コーティングをエッチングすることと前記前記障壁層の一部をエッチングすることとが、プラズマ反応性イオンエッチング（ＲＩＥ）を含む、方法。 The method of claim 1
A method comprising etching the antireflection coating and etching a portion of the barrier layer comprising plasma reactive ion etching (RIE).
前記プラズマＲＩＥが、酸素（Ｏ２）、キャリア気体、又は、ｘ＝１又は２、ｙ＝０、１、２、３又は４、及び、ｚ＝１、２、３又は４の化学量論ＣｘＨｙＦｚを有する炭素（Ｃ）と水素（Ｈ）とフッ素（Ｆ）とを含むフッ化炭素の気体混合物を用いることを含む、方法。 The method of claim 8
The plasma RIE is oxygen (O 2 ), a carrier gas, or x = 1 or 2, y = 0, 1, 2, 3 or 4, and z = 1, 2, 3 or 4 chemical quantitative theory CxHyFz. A method comprising the use of a gaseous mixture of fluorocarbon comprising carbon (C) , hydrogen (H) and fluorine (F) having .
前記キャリア気体がアルゴンを含む、方法。 The method of claim 9 .
A method in which the carrier gas comprises argon.
前記前記障壁層が、３００オングストローム～１０００オングストロームの厚みを有するシリコン窒化物を含む、方法。 The method of claim 7 .
The method, wherein the barrier layer comprises a silicon nitride having a thickness of 300 angstroms to 1000 angstroms.
前記雰囲気酸化剤を提供することが、前記半導体基板の中と前記半導体基板上とに前記酸化物領域を成長させることを含み、前記酸化物領域が少なくとも４００オングストロームの厚みを有する、方法。 The method of claim 11
A method of providing the atmospheric oxidant comprising growing the oxide region in and on the semiconductor substrate , wherein the oxide region has a thickness of at least 400 angstroms.
前記第２の厚さが少なくとも４０ｎｍであり、前記第３の厚さが４０ｎｍより小さい、方法。A method in which the second thickness is at least 40 nm and the third thickness is less than 40 nm.
半導体基板上に犠牲酸化物層を形成することと、
前記犠牲酸化物層上にシリコン窒化物層を堆積することと、
前記シリコン窒化物層上に反射防止コーティングを堆積することと、
フォトレジスト層を堆積することと、
前記フォトレジスト層におけるパターンを放射に曝すことと、
前記フォトレジスト層内に開口を提供するために前記パターンに従って前記フォトレジスト層をエッチングすることと、
前記開口の下の前記反射性防止コーティングの一部をエッチングすることと、
前記犠牲酸化物層の一部を露出させるために前記開口の下の前記シリコン窒化物層の一部をエッチングすることと、
前記犠牲酸化物層の露出された一部の厚さを増加させることによって酸化物領域を形成することと、
前記酸化物領域を形成することの後に前記シリコン窒化物層を取り除くことと、
前記シリコン窒化物層を取り除くことの後に前記半導体基板にドーパントを注入することと、
前記半導体基板にドーパントを注入することの後に前記酸化物領域の横方向の広がりの外側の前記犠牲酸化物層を取り除くことによって前記半導体基板の一部を露出させることと、
前記犠牲酸化物層を取り除くことの後に前記半導体基板の露出された一部上にゲート酸化物層を形成することであって、前記酸化物領域が前記ゲート酸化物層の厚みよりも厚く成長される、前記ゲート酸化物層を形成することと、
を含む、方法。 It ’s a method of manufacturing transistors.
Forming a sacrificial oxide layer on a semiconductor substrate and
By depositing a silicon nitride layer on the sacrificial oxide layer ,
By depositing an antireflection coating on the silicon nitride layer ,
Placing a photoresist layer and
Exposing the pattern in the photoresist layer to radiation and
Etching the photoresist layer according to the pattern to provide an opening in the photoresist layer.
Etching a portion of the antireflection coating under the opening and
Etching a portion of the silicon nitride layer under the opening to expose a portion of the sacrificial oxide layer.
Forming an oxide region by increasing the thickness of the exposed portion of the sacrificial oxide layer
After forming the oxide region , removing the silicon nitride layer,
After removing the silicon nitride layer, injecting a dopant into the semiconductor substrate,
Part of the semiconductor substrate is exposed by removing the sacrificial oxide layer outside the lateral spread of the oxide region after injecting the dopant into the semiconductor substrate.
By forming a gate oxide layer on an exposed portion of the semiconductor substrate after removing the sacrificial oxide layer, the oxide region is thicker than the thickness of the gate oxide layer. To form the gate oxide layer to be grown,
Including the method.
前記酸化物領域を形成することが、前記酸化物領域の厚さを少なくとも４００オングストロームまで増加させることを含む、方法。 The method according to claim 14 .
A method comprising forming the oxide region increasing the thickness of the oxide region to at least 400 angstroms .
半導体基板上に第１の酸化物層を形成することと、Forming the first oxide layer on the semiconductor substrate and
前記第１の酸化物層の上に障壁層を形成することと、Forming a barrier layer on the first oxide layer and
前記第１の酸化物層内に開口を形成することによって前記第１の酸化物層の露出された部分を露出させることと、To expose the exposed portion of the first oxide layer by forming an opening in the first oxide layer,
前記第１の酸化物層の露出された部分の下の前記半導体基板を熱酸化することによって前記露出された部分の厚さを第１の厚さまで増加させることと、Increasing the thickness of the exposed portion to the first thickness by thermally oxidizing the semiconductor substrate under the exposed portion of the first oxide layer.
前記第１の酸化物層を介して前記半導体基板にドーパントを注入することと、Injecting a dopant into the semiconductor substrate via the first oxide layer,
前記第１の酸化物層の露出された部分の外側の前記第１の酸化物層を除去することによって前記半導体基板の第２の部分を露出させることと、To expose the second portion of the semiconductor substrate by removing the first oxide layer outside the exposed portion of the first oxide layer.
前記第２の部分上に第２の厚さを有する第２の酸化物層を形成することであって、前記第１の厚さが前記第２の厚さよりも大きい、前記第２の酸化物層を形成することと、By forming a second oxide layer having a second thickness on the second portion, the second oxide having the first thickness larger than the second thickness. Forming layers and
を含む、方法。Including, how.
前記第１の厚さが少なくとも４０ｎｍであり、前記第２の厚さが４０ｎｍより小さい、方法。A method in which the first thickness is at least 40 nm and the second thickness is less than 40 nm.
前記熱酸化物と前記第２の酸化物層との上にゲート電極を形成することを更に含む、方法。A method further comprising forming a gate electrode on the thermal oxide and the second oxide layer.
前記障壁層がシリコン窒化物を含む、方法。A method in which the barrier layer comprises silicon nitride.
前記第１の酸化物層の露出された部分の下の前記半導体基板を熱酸化することが、酸素又は蒸気環境での酸化を含む、方法。A method in which thermal oxidation of the semiconductor substrate under an exposed portion of the first oxide layer comprises oxidation in an oxygen or vapor environment.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/944,550 US10566200B2 (en) | 2018-04-03 | 2018-04-03 | Method of fabricating transistors, including ambient oxidizing after etchings into barrier layers and anti-reflecting coatings |
| US15/944,550 | 2018-04-03 | ||
| PCT/US2019/025599 WO2019195435A1 (en) | 2018-04-03 | 2019-04-03 | Method of fabricating transistors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2021521629A JP2021521629A (en) | 2021-08-26 |
| JPWO2019195435A5 true JPWO2019195435A5 (en) | 2022-04-08 |
Family
ID=68055429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020554400A Pending JP2021521629A (en) | 2018-04-03 | 2019-04-03 | How to make a transistor |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US10566200B2 (en) |
| EP (1) | EP3776637A4 (en) |
| JP (1) | JP2021521629A (en) |
| CN (1) | CN112074932A (en) |
| WO (1) | WO2019195435A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11227926B2 (en) * | 2020-06-01 | 2022-01-18 | Nanya Technology Corporation | Semiconductor device and method for fabricating the same |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4040168A (en) | 1975-11-24 | 1977-08-09 | Rca Corporation | Fabrication method for a dual gate field-effect transistor |
| US5512495A (en) * | 1994-04-08 | 1996-04-30 | Texas Instruments Incorporated | Method of manufacturing extended drain resurf lateral DMOS devices |
| JPH1167904A (en) * | 1997-08-15 | 1999-03-09 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
| US6121133A (en) * | 1997-08-22 | 2000-09-19 | Micron Technology, Inc. | Isolation using an antireflective coating |
| JP2000353804A (en) * | 1999-06-11 | 2000-12-19 | Mitsubishi Electric Corp | Semiconductor device and manufacture of the same |
| JP2001196578A (en) * | 1999-10-29 | 2001-07-19 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method therefor |
| KR100867574B1 (en) * | 2002-05-09 | 2008-11-10 | 페어차일드코리아반도체 주식회사 | Power device and method for manufacturing the same |
| JP2004200359A (en) * | 2002-12-18 | 2004-07-15 | Ricoh Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2005123314A (en) * | 2003-10-15 | 2005-05-12 | Semiconductor Leading Edge Technologies Inc | Pattern forming method |
| KR101125707B1 (en) * | 2004-01-29 | 2012-03-27 | 에이에스엠엘 네덜란드 비.브이. | T-gate formation |
| DE102004031741B4 (en) | 2004-06-30 | 2010-04-01 | Qimonda Ag | Method for producing a contact arrangement for field effect transistor structures with gate electrodes with a metal layer and use of the method for producing field effect transistor arrangements in a cell array |
| KR20060070334A (en) | 2004-12-20 | 2006-06-23 | 삼성전자주식회사 | Method for manufacturing thin film transistor array panel |
| CN101218675A (en) * | 2005-07-07 | 2008-07-09 | 密克罗奇普技术公司 | ESD structure having different thickness gate oxides |
| US20070018199A1 (en) | 2005-07-20 | 2007-01-25 | Cree, Inc. | Nitride-based transistors and fabrication methods with an etch stop layer |
| JP5272410B2 (en) * | 2008-01-11 | 2013-08-28 | 富士電機株式会社 | Semiconductor device and manufacturing method thereof |
| EP2244299A1 (en) * | 2009-04-22 | 2010-10-27 | STMicroelectronics S.r.l. | MOS transistor for power applications and corresponding integrated circuit and manufacturing method |
| JP5754334B2 (en) * | 2011-10-04 | 2015-07-29 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| JP5887233B2 (en) * | 2012-09-10 | 2016-03-16 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| JP2014192361A (en) * | 2013-03-27 | 2014-10-06 | Sharp Corp | Semiconductor device and manufacturing method of the same |
| US9218978B1 (en) * | 2015-03-09 | 2015-12-22 | Cypress Semiconductor Corporation | Method of ONO stack formation |
-
2018
- 2018-04-03 US US15/944,550 patent/US10566200B2/en active Active
-
2019
- 2019-04-03 EP EP19781451.0A patent/EP3776637A4/en not_active Withdrawn
- 2019-04-03 JP JP2020554400A patent/JP2021521629A/en active Pending
- 2019-04-03 CN CN201980029913.7A patent/CN112074932A/en active Pending
- 2019-04-03 WO PCT/US2019/025599 patent/WO2019195435A1/en unknown
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