KR20060070334A - Method for manufacturing thin film transistor array panel - Google Patents

Abstract

According to an embodiment of the present invention, a gate line is formed on a substrate, a gate insulating layer and a semiconductor layer are sequentially formed on the gate line, a data line including a source electrode on the gate insulating layer and the semiconductor layer, and a predetermined distance from the source electrode. Forming a drain electrode facing each other; and forming a pixel electrode connected to the drain electrode, wherein at least one of forming the gate line and forming the data line and the drain electrode Forming a diffusion barrier layer and a metal layer including copper, forming and patterning a photosensitive resin film on the metal layer including copper, and wet etching the metal layer including the copper using the photosensitive resin film as a mask. And dry etching the diffusion barrier layer. Provided is a method of manufacturing a thin film transistor array panel.

Copper, Wet Etch, Dry Etch, Photosensitive Resin Film

Description

Method for manufacturing thin film transistor array panel {Method for manufacturing thin film transistor array panel}

1 is a layout view illustrating a structure of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along line II-II ',

3 to 15B are layout or cross-sectional views of a thin film transistor array panel sequentially illustrating a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 and 2 according to an exemplary embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

110: substrate 121: gate line

124: gate electrode 81, 82: contact auxiliary member

140: gate insulating film 151: intrinsic amorphous silicon layer

161: impurity amorphous silicon layer 171: data line

173: source electrode 175: drain electrode

177: conductor for holding capacitor 180: protective film

181, 182, 185, and 187: contact hole 190: pixel electrode

The present invention relates to a method of manufacturing a thin film transistor array panel, and more particularly, to a method of manufacturing a thin film transistor array panel including low resistance wiring.

Liquid crystal display is one of the most widely used flat panel displays. It consists of two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween. The display device is applied to rearrange the liquid crystal molecules of the liquid crystal layer to control the amount of light transmitted.

Among the liquid crystal display devices, a field generating electrode is provided in each of two display panels. Among them, a structure in which a plurality of pixel electrodes are arranged in a matrix form on one display panel and one common electrode on the entire display panel on the other display panel is mainstream. The display of an image in such a liquid crystal display is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal element for switching a voltage applied to a pixel electrode, is connected to each pixel electrode, and a gate line for transmitting a signal for controlling the thin film transistor and a voltage to be applied to the pixel electrode. Data lines to be transferred are formed on the display panel, respectively. The thin film transistor serves as a switching element that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line. Such a thin film transistor also serves as a switching element for individually controlling each light emitting element in an active organic light emitting diode (AM-OLED) which is a self-luminous element.

In such a thin film transistor, chromium (Cr) is mainly used as a material for a gate line including a gate electrode, a data line including a source electrode, and a drain electrode.

However, as the area of the liquid crystal display device becomes larger and larger, the length of the gate line and the data line becomes longer. Accordingly, when using the existing chromium wire, a problem such as signal delay occurs due to a relatively high resistance.

In order to overcome this problem, copper (Cu) having a low specific resistance is known as a suitable metal for a large area liquid crystal display device, but copper (Cu) is an actual process depending on the adhesion to the substrate and the difficulty of etching. There is a problem of low reliability to apply to.

Accordingly, the present invention has been made to solve the above problems, and provides a method for forming a display device wiring which can ensure low resistance and reliability of wiring at the same time, and a method for manufacturing a thin film transistor array panel including the wiring formed by the method. do.

According to another aspect of the present invention, there is provided a method of forming a wiring for a display device, the method comprising sequentially forming a conductive layer including a diffusion barrier layer and copper on a substrate, forming and patterning a photosensitive resin film on the conductive layer including copper, and the photosensitive layer. Wet etching the conductive layer containing copper using a resin film as a mask, and dry etching the diffusion barrier layer.

In addition, the diffusion barrier layer is chromium (Cr), titanium (Ti), tantalum (Ta), vanadium (V), tungsten (W), cobalt (Co), nickel (Ni), platinum (Pt) and palladium (Pd) It is preferable to form with any one or an alloy thereof selected from.

In addition, the method of manufacturing a thin film transistor array panel according to the present invention may include forming a gate line on a substrate, sequentially forming a gate insulating film and a semiconductor layer on the gate line, and including a source electrode on the gate insulating film and the semiconductor layer. Forming a data line, a drain electrode facing the source electrode at a predetermined interval, and forming a pixel electrode connected to the drain electrode; forming the gate line; At least one of forming a drain electrode includes sequentially forming a diffusion barrier layer and a conductive layer including copper, forming and patterning a photosensitive resin film on the conductive layer including copper, and using the photosensitive resin film as a mask. Wet etching the conductive layer containing the copper by And dry etching the diffusion barrier layer.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.                     

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

Example 1

First, the structure of a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view illustrating a structure of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II ′ of the thin film transistor array panel of FIG. 1.

As shown in FIGS. 1 and 2, a plurality of gate lines 121 are formed on the insulating substrate 110 to transfer gate signals. The gate line 121 extends in the horizontal direction, and a part of each gate line 121 forms a plurality of gate electrodes 124. In addition, another portion of each gate line 121 protrudes downward to form a plurality of expansions 127.

The gate line 121 includes chromium (Cr), titanium (Ti), tantalum (Ta), vanadium (V), tungsten (W), cobalt (Co), nickel (Ni), platinum (Pt), and palladium ( Lower conductive layers 124p, 127p and 129p made of any one or alloys thereof or nitrides thereof selected from Pd) and upper conductive layers 124q, 127q and 129q made of copper (Cu) or copper alloys (Cu-alloy); )

Side surfaces of the lower conductive layers 124p, 127p, and 129p and the upper conductive layers 124q, 127q, and 129q are formed at an inclination angle of about 30 to 80 degrees.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear semiconductor layers 151 made of hydrogenated amorphous silicon or the like are formed on the gate insulating layer 140. The linear semiconductor layer 151 extends in the vertical direction, from which a plurality of extensions 154 extend toward the gate electrode 124. Further, the linear semiconductor layer 151 increases in width near the point where the linear semiconductor layer 151 meets the gate line 121 to cover a large area of the gate line 121.

On the semiconductor layer 151, a linear ohmic contact 161 made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of silicide or n-type impurities, and a plurality of island-type ohmic contacts ( 163 and 165 are formed. The islands of ohmic contact 163 and 165 are paired and positioned on the protrusion 154 of the semiconductor layer 151. Side surfaces of the semiconductor layers 151 and 154 and the ohmic contacts 161, 163 and 165 are also inclined, and the inclination angle is 30 to 80 ° with respect to the substrate 110.                     

The source electrode 173, the plurality of data lines 171, and the plurality of drain electrodes 175 are respectively formed on the islands ohmic contact layers 163 and 165 and the gate insulating layer 140. And a plurality of storage capacitor conductors 177 are formed.

The data line 171 extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 124.

The data line 171 and the drain electrode 175 including the source electrode 173 include chromium (Cr), titanium (Ti), tantalum (Ta), vanadium (V), tungsten (W), and cobalt (Co). ), Nickel (Ni), platinum (Pt), and palladium (Pd), any one or an alloy thereof or a nitride thereof, or a lower conductive layer (171p, 173p, 175p, 177p, 179p) and copper (Cu) or The upper conductive layers 171q, 173q, 175q, 177q, and 179q made of a copper alloy (Cu-alloy) are formed.

The gate electrode 124, the source electrode 173, and the drain electrode 175 together with the protrusion 154 of the semiconductor 151 form a thin film transistor (TFT), and a channel of the thin film transistor It is formed on the surface of the protrusion 154 of the semiconductor between the source electrode 173 and the drain electrode 175. The storage capacitor conductor 177 overlaps the extension portion 127 of the gate line 121.                     

Similarly to the gate line 121, the data line 171, the drain electrode 175, and the storage capacitor conductor 177 are also inclined with respect to the substrate 110 at an angle of about 30 to 80 °.

The island-type ohmic contact layers 163 and 165 exist between the lower semiconductor layer 154 and the source electrode 173 and the drain electrode 175 thereon, and serve to lower the contact resistance. In addition, the linear semiconductor layer 151 has a portion exposed between the source electrode 173 and the drain electrode 175, and is not covered by the data line 171 and the drain electrode 175, and in most regions, the linear semiconductor layer 151 has a linear semiconductor layer. Although the width of the layer 151 is smaller than the width of the data line 171, as described above, the width of the layer 151 increases to increase the insulation between the gate line 121 and the data line 171.

On the data line 171, the drain electrode 175, the storage capacitor conductor 177, and the exposed semiconductor layer 151, an organic material having excellent planarization characteristics and photosensitivity, and plasma enhanced chemical vapor deposition (Plasma Enhanced) A passivation layer 180 made of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or an inorganic material silicon nitride formed by Chemical Vapor Deposition (PECVD) is formed. have. In addition, when the passivation layer 180 is formed of an organic material, the organic material of the passivation layer 180 is prevented from coming into contact with a portion of the semiconductor layer 154 exposed between the source electrode 173 and the drain electrode 175. To this end, an insulating film (not shown) made of silicon nitride (SiNx) or silicon oxide (SiO ₂ ) may be further formed below the organic film.

The passivation layer 180 includes a plurality of contact holes 181 and 185 respectively exposing the gate portion 129, the drain electrode 175, the storage capacitor conductor 177, and the data portion 179. , 187, 182 are formed.

A plurality of pixel electrodes 190 and a plurality of contact assistants 81 and 82 made of ITO or IZO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 and the storage capacitor conductor 177 through the contact holes 185 and 187, respectively, to receive the data voltage from the drain electrode 175 and to maintain the storage capacitor. The data voltage is transmitted to the existing conductor 177.

The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules of the liquid crystal layer by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. .

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gator line and the end portion 179 of the data line through the contact holes 181 and 182, respectively. The contact assistants 81 and 82 compensate for and protect the adhesion between the end portion 129 of the gate line or the end portion 179 of the data line and an external device such as a driving integrated circuit.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 and 2 according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3A to 15B and FIGS. 1 and 2.                     

First, as shown in FIG. 3, chromium (Cr), titanium (Ti), tantalum (Ta), vanadium (V), tungsten (W), cobalt (Co), and nickel (Ni) on the insulating substrate 110. , The lower conductive layer 120p made of any one or an alloy thereof selected from platinum (Pt) and palladium (Pd) and the upper conductive layer 120q made of copper or a copper alloy (hereinafter referred to as 'copper layer') Laminate sequentially.

Here, the conductor is formed by co-sputtering. In this embodiment, tantalum (Ta) and copper (Cu) were used as targets for the sputtering of the cavity.

Cavity sputtering initially does not apply power to a copper (Cu) target, but applies power only to a tantalum (Ta) target to form a tantalum layer on the substrate 110. It is also possible to form tantalum nitride (TaN) during tantalum sputtering, for example by exposure to a nitrogen supply gas such as nitrogen (N ₂ ) gas, ammonia (NH ₃ ) gas or nitrous oxide (N ₂ O). In this case, the nitride layer may be nitrided between the tantalum layer and the copper layer formed thereafter, thereby preventing the copper layer from diffusing into the tantalum layer. The tantalum layer is formed to a thickness of about 50 to 500 kPa.

Next, after the power applied to the tantalum target is turned off, the power applied to copper (Cu) is applied to form a copper layer. In this case, the copper layer is formed to a thickness of about 1500 to 3000 kPa.

Next, as shown in FIG. 4, the photosensitive resin film 40 is apply | coated by the spin coating method.                     

Subsequently, the photosensitive resin film 40 is exposed and developed using a mask 50 having a predetermined pattern formed thereon to form the photosensitive resin pattern 40a.

Next, as shown in FIG. 5, the copper layer 120q in the region except for the portion where the photosensitive resin pattern 40a remains is etched using an etching solution. In this case, an etchant containing phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and demineralized water in an appropriate ratio may be used, or a hydrogen peroxide (H ₂ O ₂ ) -based etchant.

The copper layer 120q is weak in chemical resistance and should be etched under the condition of weak acid. However, such a weak acid etchant cannot etch the lower conductive layer 120p made of most other metals except copper. Generally, chromium (Cr), titanium (Ti), tantalum (Ta), vanadium (V), tungsten (W), cobalt (Co), nickel (Ni), platinum (Pt) or palladium (Pd), etc. The metal cannot be etched under the conditions of a weak acid such as an etchant consisting of phosphoric acid, nitric acid and acetic acid, hydrogen peroxide etchant. The metals may exceptionally be etched in hydrofluoric acid (HF), but in the case of hydrofluoric acid they are not available in the actual process because they react with the glass in contact with the glass substrate.

Conventionally, in addition to the metal, molybdenum (Mo), which may be collectively etched with the same etching solution as copper, may be used as a lower layer. However, molybdenum has a weak diffusion barrier compared to the metals.

In the present invention, in order to take advantage of low resistance wiring using copper, chromium (Cr), titanium (Ti), tantalum (Ta), vanadium (V), and tungsten (W) are significantly more excellent in preventing diffusion than molybdenum. , Metals such as cobalt (Co), nickel (Ni), platinum (Pt), or palladium (Pd) or alloys thereof are used as the diffusion barrier layer.

However, since the metals cannot be wet etched using the same etching solution as the copper layer, the lower conductive layer 120p is etched by the following method.

As shown in FIG. 6, dry etching using plasma is performed using the photosensitive resin pattern 40a and the copper layer patterns 124q, 127q, and 129q remaining after the wet etching of the copper layer 120p as a mask. do. Alternatively, after removing the photosensitive resin pattern 40a, dry etching may be performed using the copper layer patterns 124q, 127q, and 129q as masks. As the etching gas, a mixed gas of Cl ₂ and O ₂ or a mixed gas of HCl and O ₂ may be used. As a result, the lower conductive layer 120p is etched to form a pattern as illustrated in FIG. 7.

Next, the photosensitive resin pattern 40a is removed using a photosensitive resin release agent, thereby including the gate electrode 124, the extension 127, and the end portion 129 of the gate line, as shown in FIGS. 8A and 8B. The gate line 121 is formed.

Next, as illustrated in FIGS. 9A and 9B, silicon nitride (SiNx) or silicon oxide (SiNx) may be covered to cover the gate line 121 including the gate electrode 124, the extension 127, and the end portion 129 of the gate line. SiO ₂ ) is deposited to form a gate insulating layer 140. The stacking temperature of the gate insulating layer 140 is preferably about 250 to 500 ° C., and the thickness is about 2,000 to 5,000 kPa.

In addition, a three-layer film of intrinsic amorphous silicon and an impurity doped amorphous silicon layer is sequentially stacked on the gate insulating layer 140, and the amorphous silicon layer and the intrinsic amorphous silicon layer doped with impurities are successively stacked. Photo etching is performed to form the linear intrinsic semiconductor layer 151 including the plurality of protrusions 154 and the plurality of impurity semiconductor patterns 164, and the amorphous silicon layer 161 doped with impurities.

Next, as shown in FIG. 10, chromium (Cr), titanium (Ti), tantalum (Ta), vanadium (V), and tungsten (W) on the amorphous silicon layer 161 doped with impurities by sputtering or the like. ), Cobalt (Co), nickel (Ni), platinum (Pt) and palladium (Pd) any one or an alloy thereof selected from the lower conductive layer (170p) and the upper conductive layer (170q) made of copper or copper alloy (Hereinafter referred to as 'copper layer').

The lower conductive layer 170p and the copper layer 170q are also formed by cavity sputtering like the gate lines.

Next, as shown in FIG. 11, the photosensitive resin film 41 is apply | coated on the copper layer 120q by spin coating or the like. Subsequently, after exposing using the mask 51, it develops and the photosensitive resin pattern 41a is formed.

Next, the copper layer 170q in the region except for the portion where the photosensitive resin pattern 41a remains is etched. At this time, the etchant is an etchant or hydrogen peroxide-based etchant containing phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH) and demineralized water in an appropriate ratio.

Next, as shown in FIG. 12, the lower metal layer 170p using the photosensitive resin pattern 41a remaining after the wet etching of the copper layer 170q and the copper layer patterns 171q, 173q, 175q, 177q, and 179q as a mask. ) Is subjected to dry etching using plasma. Alternatively, after the photosensitive resin pattern 41a is removed, dry etching may be performed using only the copper layer patterns 171q, 173q, 175q, 177q, and 179q as a mask. As the etching gas, a mixed gas of Cl ₂ and O ₂ or a mixed gas of HCl and O ₂ may be used. As a result, the lower conductive layer 170p is etched to form a source electrode 173, a drain electrode 175, a storage capacitor conductor 177, and an end portion 179 of the data line.

Subsequently, the semiconductor layer 164 that is not covered by the source electrode 173, the drain electrode 175, and the storage capacitor conductor 177 and doped with the exposed impurities is removed by dry etching using plasma to form a plurality of protrusions ( A plurality of linear ohmic contact layers 161 and a plurality of island type ohmic contact layers 165 each including 163 are completed, while portions of the intrinsic semiconductor 154 thereunder are exposed. In this case, it is preferable to perform oxygen (O ₂ ) plasma to stabilize the surface of the exposed intrinsic semiconductor 154.

Subsequently, the photosensitive resin film pattern 41a is removed using a photosensitive resin release agent to complete the data line pattern as shown in FIGS. 14A and 14B.

Next, as illustrated in FIGS. 15A and 15B, organic materials having excellent planarization characteristics and photosensitivity, a-Si: C: O, a formed by plasma enhanced chemical vapor deposition (PECVD) A low dielectric constant insulating material such as Si: O: F, or silicon nitride (SiNx), which is an inorganic material, is formed in a single layer or in a plurality of layers to form a passivation layer 180.

Then, after the photoresist is coated on the passivation layer 180, the photoresist is irradiated with light through a photomask and developed to form a plurality of contact holes 181, 185, 187, and 182. In this case, in the case of the organic film having photosensitivity, the contact hole may be formed only by a photolithography process, and the gate opening 140 and the passivation layer 180 may be formed under etching conditions having substantially the same etching ratio.

Next, as shown in FIGS. 1 and 2, ITO or IZO is stacked on the substrate by sputtering, and a plurality of pixel electrodes 190 and a plurality of contact assistants 81 and 82 are formed by a photolithography process. .

Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

As described above, the wet etching and the dry etching are successively performed on the wiring formed of the copper layer and the diffusion barrier layer to overcome the limitations of the conventional wet etching of metals such as molybdenum (Mo) as the lower layer of the copper layer. And effective diffusion prevention properties can be secured.

Claims (15)

Sequentially forming a metal layer including a diffusion barrier layer and a copper layer on the substrate, Forming and patterning a photosensitive resin film on the metal layer including copper; Wet etching the metal layer containing copper using the photosensitive resin film as a mask, and And dry etching the diffusion barrier layer. The diffusion barrier layer is chromium (Cr), titanium (Ti), tantalum (Ta), vanadium (V), tungsten (W), cobalt (Co), nickel (Ni), platinum (Pt) and A method of forming a wiring for a display device, which is formed of any one selected from palladium (Pd), alloys thereof, and nitrides thereof. The method of claim 1, wherein the wet etching of the metal layer including copper uses a hydrogen peroxide-based etching solution or an etching solution containing phosphoric acid, nitric acid, and acetic acid. The method of claim 1, wherein the dry etching of the diffusion barrier layer is performed by etching the patterned photosensitive resin layer as a mask. The method of claim 1, further comprising removing the patterned photosensitive resin film after the wet etching of the metal layer including copper. Forming a gate line on the substrate, Sequentially forming a gate insulating film and a semiconductor layer on the gate line; Forming a data line including a source electrode and a drain electrode facing the source electrode at a predetermined interval on the gate insulating layer and the semiconductor layer, and Forming a pixel electrode connected to the drain electrode; At least one of forming the gate line and forming the data line and the drain electrode may be performed by sequentially forming a metal layer including a diffusion barrier layer and copper, and forming a photosensitive resin film on the metal layer including copper. Patterning, wet etching the metal layer including copper using the photosensitive resin film as a mask, and dry etching the diffusion barrier layer. The diffusion barrier layer is chromium (Cr), titanium (Ti), tantalum (Ta), vanadium (V), tungsten (W), cobalt (Co), nickel (Ni), platinum (Pt) and A method for manufacturing a thin film transistor array panel formed of any one or alloys thereof selected from palladium (Pd). The method of claim 7, wherein the forming of the diffusion barrier layer comprises exposing the metal to a nitrogen supply gas. The method of claim 6, wherein the wet etching of the metal layer including copper uses a hydrogen peroxide-based etching solution or an etching solution containing phosphoric acid, nitric acid, and acetic acid. The method of claim 6, wherein the dry etching of the diffusion barrier layer is performed by etching the patterned photosensitive resin layer as a mask. The method of claim 6, further comprising removing the patterned photosensitive resin layer after the wet etching of the metal layer including copper. The method of claim 6, further comprising forming a semiconductor layer doped with impurities after the forming of the semiconductor layer. The method of claim 12, further comprising dry etching the semiconductor layer doped with the impurity after the dry etching of the diffusion barrier layer. Board, A gate line formed on the substrate, A gate insulating film formed on the gate line, A data line including a source electrode formed on the gate insulating film, a drain electrode facing the source electrode, and A pixel electrode connected to the drain electrode; The at least one of the gate line, the data line, and the drain electrode includes a diffusion barrier layer and a metal layer including copper. The method of claim 14, wherein the diffusion barrier layer is chromium (Cr), titanium (Ti), tantalum (Ta), vanadium (V), tungsten (W), cobalt (Co), nickel (Ni), platinum (Pt), A thin film transistor array panel formed of any one selected from palladium (Pd), alloys thereof, and nitrides thereof.

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