KR20060079706A - Wiring for display device, thin film transistor array panel comprising the wiring and method for manufacturing the same - Google Patents

Abstract

The present invention provides a substrate, a gate line formed on the substrate and including a gate electrode, a gate insulating film formed on the gate line, a semiconductor layer formed in a predetermined region on the gate insulating film, the gate insulating film and the semiconductor layer. A data line formed thereon and including a drain electrode facing the source electrode at a predetermined interval and a pixel electrode connected to the drain electrode, and at least one of the gate line, the data line, and the drain electrode The thin film transistor includes a first metal layer made of a low resistance metal and a second metal layer formed on at least one of a lower portion and an upper portion of the first metal layer, wherein the first metal layer has a narrower width than that of the second metal layer. A display panel and a method of manufacturing the same are provided.

Low resistance wiring, aluminum, hillock, crack

Description

Wiring for display device, thin film transistor array panel comprising the wiring and method for manufacturing the same}

1 is a layout view illustrating a structure of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along line II-II ',

3A, 4A, 5A, and 6A are layout views of a thin film transistor array panel sequentially showing a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 and 2 according to an embodiment of the present invention.

3B is a cross-sectional view taken along the line IIIb-IIIb 'of FIG. 3A,

4B is a cross-sectional view taken along the line IVb-IVb ′ of FIG. 4A;

5B is a cross-sectional view taken along the line Vb-Vb ′ of FIG. 5A;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ of FIG. 6A.

* Explanation of symbols for main parts of the drawings

110: insulating substrate 121: gate line

124: gate electrode                 

140: gate insulating film 151: intrinsic amorphous silicon layer

161: impurity amorphous silicon layer 171: data line

173: source electrode 175: drain electrode

177: conductor for holding capacitor 180: protective film

181, 182, 185, and 187: contact hole 190: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device wiring, a thin film transistor array panel including the wiring, and a manufacturing method thereof.

Liquid crystal display is one of the most widely used flat panel displays. It consists of two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween. The display device is applied to rearrange the liquid crystal molecules of the liquid crystal layer to control the amount of light transmitted.

Among the liquid crystal display devices, the one currently used is a structure in which a field generating electrode is provided in each of the two display panels. Among them, a structure in which a plurality of pixel electrodes are arranged in a matrix form on one display panel and one common electrode on the entire display panel on the other display panel is mainstream. The display of an image in such a liquid crystal display is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal device for switching the voltage applied to the pixel electrode, is connected to each pixel electrode, and a gate line for transmitting a signal for controlling the thin film transistor and a voltage to be applied to the pixel electrode. Data lines for transmitting the data lines are formed on the display panel. The thin film transistor serves as a switching element that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line. Such a thin film transistor also serves as a switching element for individually controlling each light emitting element in an active organic light emitting diode (AM-OLED) which is a self-luminous element.

In such a thin film transistor, chromium (Cr) is mainly used as a material for a gate line including a gate electrode, a data line including a source electrode, and a drain electrode.

However, as the area of the display device becomes larger and larger, the lengths of the gate lines and the data lines become longer, and thus the wirings need to be formed of a material having a low specific resistance. However, since chromium has a high specific resistance, there is a limit to use in a large area display device.

Therefore, aluminum (Al) having a low specific resistance is known as a metal suitable for application to a large area display device. However, aluminum (Al) is thermally expanded in a high temperature process, causing problems such as hillock. In this case, not only the electrical characteristics are deteriorated, but also cracks occur in the insulating layers formed on the lower and upper portions, and in particular, in the case of the wiring connected to the transparent pixel electrode, the etching liquid used for patterning the transparent electrode through the cracks There is a problem of flowing in and opening the wiring. Therefore, there is a limit to apply to the actual process.

Accordingly, the present invention provides a display device wiring, a thin film transistor display panel including the wiring, and a method of manufacturing the same, for solving the above problems, which can solve a problem caused by thermal expansion while maintaining low resistance. do.

The wiring for a display device according to the present invention includes a first metal layer and a second metal layer formed on at least one of a lower portion and an upper portion of the first metal layer, wherein the first metal layer is formed to have a smaller width than the second metal layer. It is.

The thin film transistor array panel according to the present invention further includes a substrate, a gate line formed on the substrate and including a gate electrode, a gate insulating film formed on the gate line, and a semiconductor layer formed on a predetermined region on the gate insulating film. And a data line formed on the gate insulating layer and the semiconductor layer, the data line including a source electrode, a drain electrode facing the source electrode at a predetermined interval, and a pixel electrode connected to the drain electrode. At least one of the data line and the drain electrode includes a first metal layer and a second metal layer formed on at least one of a lower portion and an upper portion of the first metal layer, wherein the first metal layer is formed to have a narrower width than the second metal layer. have.

In addition, the method of manufacturing a thin film transistor array panel according to the present invention includes forming a gate line on a substrate, sequentially forming a gate insulating film and a semiconductor layer on the gate line, and including a source electrode on the gate insulating film and the semiconductor layer. Forming a data line, a drain electrode facing the source electrode at a predetermined interval, and forming a pixel electrode connected to the drain electrode; forming the gate line and the data line And forming at least one of the drain electrodes includes forming a first metal layer and forming a second metal layer on at least one of a lower portion and an upper portion of the first metal layer, wherein the first metal layer is formed on the second metal layer. It is formed in a narrower width than the metal layer.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, the structure of a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view illustrating a structure of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II ′ of the thin film transistor array panel of FIG. 1.

As shown in FIGS. 1 and 2, a plurality of gate lines 121 are formed on the insulating substrate 110 to transfer gate signals. The gate line 121 extends in the horizontal direction, and a part of each gate line 121 forms a plurality of gate electrodes 124. In addition, another portion of each gate line 121 protrudes downward to form a plurality of expansions 127.

The gate line 121 is a lower metal layer 124p or 127p formed of any one selected from chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), tungsten (W), alloys thereof, and nitrides thereof. , 129p), and a low resistance metal layer 124q, 127q, 129q made of a low resistance metal such as aluminum or an aluminum alloy, and chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), and tungsten (W), their alloys, and their nitrides, which are formed of the upper metal layers 124r, 127r, and 129r.

Although the lower metal layers 124p, 127p, and 129p and the upper metal layers 124r, 127r, and 129r are all formed in this embodiment, only one of them may be formed.

In general, low-resistance metals such as aluminum (Al) are suitable for large-area display devices because they do not cause problems such as signal delay, but are difficult to apply to actual processes due to expansion such as hillocks occurring on the surface of the metal layer. The hillock is a stress between the substrate and the metal layer having different thermal expansion coefficients due to high temperature heating and cooling of about 300 degrees or more, and the migration of atoms occurs in the metal layer to solve the formation of protrusions. Say something. When a hillock occurs, not only a problem of lowering electrical characteristics but also a problem of generating a crack in the gate insulating layer 140 covering the gate line 121.

Accordingly, in the present invention, in order to solve this problem, the coefficient of thermal expansion is different by forming the lower metal layers 124p, 127p, and 129p and / or the upper metal layers 124r, 127r, and 129r on and under the low resistance metal layer. The stress generated between the substrate 110 and the low resistance metal layers 124q, 127q, and 129q made of aluminum may be alleviated to reduce the occurrence of hillock.

In addition, the lower metal layers 124p, 127p, and 129p and the upper metal layers 124r, 127r, and 129r are formed to oxidize the metal forming the low resistance metal layers 124q, 127q, and 129q to form the substrate 110 and / or the gate. The diffusion into the insulating layer 140 is prevented.

In addition, the low resistance metal layers 124q, 127q, and 129q according to the present invention are formed to have a narrower width than the lower metal layers 124p, 127p, and 129p or the upper metal layers 124r, 127r, and 129r. This is to crack cracks in the gate insulating layer 140 covering the gate line 121 by the expansion of the low resistance metal layers 124q, 127q, and 129q. As a result, the problem of expansion in the side of the low resistance metal layers 124q, 127q, and 129q not covered by the lower metal layers 124p, 127p, and 129p or the upper metal layers 124r, 127r, and 129r can be solved. In this case, even if expansion occurs to the side of the low-resistance metal layer, the gate insulating film 140 is formed thicker by the width difference between the lower metal layers 124p, 127p, and 129p and the upper metal layers 124r, 127r, and 129r. Cracks can be prevented from occurring in the 140.

Side surfaces of the lower metal layers 124p, 127p, and 129p, the low resistance metal layers 124q, 127q, and 129q, and the upper metal layers 124r, 127r, and 129r are inclined, respectively, and the inclination angle is about 30 to about the surface of the substrate 110. 80 degrees.

A gate insulating layer 140 made of silicon nitride (SiNx) or the like is formed on the gate line 121.

A plurality of linear semiconductor layers 151 made of hydrogenated amorphous silicon or the like are formed on the gate insulating layer 140. The linear semiconductor layer 151 extends in the vertical direction, from which a plurality of extensions 154 extend toward the gate electrode 124. Further, the linear semiconductor layer 151 increases in width near the point where the linear semiconductor layer 151 meets the gate line 121 to cover a large area of the gate line 121.

A plurality of linear ohmic contacts 161 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration on the semiconductor layer 151 and a plurality of island-type ohmic contacts. Layers 163 and 165 are formed. The islands of ohmic contact 163 and 165 are paired and positioned on the protrusion 154 of the semiconductor layer 151. Side surfaces of the semiconductor layer 151 and the ohmic contact layers 161, 163, and 165 are also inclined, and the inclination angle is 30 to 80 ° with respect to the substrate 110.

A plurality of data lines 171 and a plurality of drain electrodes including a source electrode 173 on the ohmic contacts 161, 163, and 165 and the gate insulating layer 140, respectively. 175, a plurality of storage capacitor conductors 177 and an end portion 179 of the data line having an extended width for connection with an external circuit are formed.

The data line 171 extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source and drain electrodes 173 and 175 are separated from each other and positioned opposite to the gate electrode 124.

The data line 171 and the drain electrode 175 including the source electrode 173 include chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), tungsten (W), and alloys thereof. And lower metal layers 171p, 173p, 175p, 177p, and 179p made of any one selected from nitrides thereof, and low resistance metal layers 171q, 173q, 175q, 177q, and 179q made of a low resistance metal such as aluminum or an aluminum alloy. And upper metal layers 171r, 173r, 175r, 177r, which include any one selected from chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), tungsten (W), alloys thereof, and nitrides thereof. 179r).

Although the lower metal layers 171p, 173p, 175p, 177p, and 179p and the upper metal layers 171r, 173r, 175r, 177r, and 179r are all formed in this embodiment, they may be formed only in one of them.

In general, low-resistance metals such as aluminum (Al) are suitable for large-area display devices because they do not cause problems such as signal delay, but are difficult to apply to actual processes due to expansion such as hillocks occurring on the surface of the metal layer. The hillock is a stress between the substrate and the metal layer having different thermal expansion coefficients due to high temperature heating and cooling of about 300 degrees or more, and the migration of atoms occurs in the metal layer to solve the formation of protrusions. Say something. When the hillock occurs, not only causes a problem of electrical signal delay due to high resistance, but also cracks in the passivation layer 180 covering the data line 171 and the drain electrode 175 due to expansion. There is also a problem that the etchant used to form the pixel electrode 190 pattern flows into the data line through the crack.

In the present invention, to solve this problem, the lower metal layer 171p, 173p, 175p, 177p, 179p and / or the upper metal layer (171p, 173q, 175q, 177q, 179q) and / or the upper metal layer (171p, 173q, 175q, 179q). By forming 171r, 173r, 175r, 177r, and 179r, stress generated between the lower layer having different thermal expansion coefficients and the low-resistance metal layer can be reduced to reduce the occurrence of hillock.

In addition, the lower metal layers 171p, 173p, 175p, 177p, and 179p and the upper metal layers 171r, 173r, 175r, 177r, and 179r form the low resistance metal layers 171q, 173q, 175q, 177q, and 179q. The oxide is prevented from being diffused to the lower semiconductor layer 154 or the upper passivation layer 180 at the same time.

Further, in the present invention, the low resistance metal layers 171q, 173q, 175q, 177q, and 179q are narrower than the lower metal layers 171p, 173p, 175p, 177p, and 179p or the upper metal layers 171r, 173r, 175r, 177r, and 179r. It is formed in width. As a result, the low-resistance metal layers 171q, 173q, 175q, 177q, and 179q that are not covered by the lower metal layers 171p, 173p, 175p, 177p, and 179p or the upper metal layers 171r, 173r, 175r, 177r, and 179r. It can solve the expansion problem that occurs. In this case, even if expansion occurs to the side of the low resistance metal layers 171q, 173q, 175q, 177q, and 179q, the lower metal layers 171p, 173p, 175p, 177p, and 179p or the upper metal layers 171r, 173r, 175r, 177r, Since the passivation layer 180 is formed to be thicker than the width of the passivation layer 179r, cracks may be prevented from occurring in the passivation layer 180.

Similarly to the gate line 121, the data line 171, the drain electrode 175, and the storage capacitor conductor 177 are also inclined with respect to the substrate 110 at an angle of about 30 to 80 °.

The gate electrode 124, the source electrode 173, and the drain electrode 175 together with the protrusion 154 of the semiconductor 151 form a thin film transistor (TFT), and the channel of the thin film transistor is a source. The protrusion 154 is formed between the electrode 173 and the drain electrode 175. The storage capacitor conductor 177 overlaps the extension portion 127 of the gate line 121.

The island-type ohmic contact layers 163 and 165 exist between the semiconductor layer 154 below and the source electrode 173 and the drain electrode 175 thereon, and serve to lower the contact resistance. The linear semiconductor layer 151 has an exposed portion between the source electrode 173 and the drain electrode 175, and is not covered by the data line 171 and the drain electrode 175, and in most regions, the linear semiconductor layer ( Although the width of the 151 is smaller than the width of the data line 171, as described above, the width of the 151 increases to increase the insulation between the gate line 121 and the data line 171.

On the data line 171, the drain electrode 175, the storage capacitor conductor 177, and the exposed semiconductor layer 151, an organic material having excellent planarization characteristics and photosensitivity, and plasma chemical vapor deposition ( A passivation layer made of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F formed by Plasma Enhanced Chemical Vapor Deposition (PECVD), or silicon nitride (SiNx), an inorganic material ( 180 is formed of a single layer or a plurality of layers. For example, when formed of an organic material, a portion of the semiconductor layer 154 between the source electrode 173 and the drain electrode 175 is exposed to prevent the organic material of the passivation layer 180 from contacting the lower portion of the organic layer. An insulating film (not shown) made of silicon nitride (SiNx) or silicon oxide (SiO ₂ ) may be further formed.

The passivation layer 180 includes an end portion 129 of an extended gate line for mounting an external circuit, a drain electrode 175, a conductor for a storage capacitor 177, and an end portion of an extended data line for mounting an external circuit. A plurality of contact holes 181, 185, 187, and 182 exposing 179 are respectively formed.

A plurality of pixel electrodes 190 and a plurality of contact assistants 81 and 82 made of ITO or IZO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 and the storage capacitor conductor 177 through the contact holes 185 and 187, respectively, to receive and maintain a data voltage from the drain electrode 175. The data voltage is transmitted to the conductor 177 for the capacitor.

The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules of the liquid crystal layer by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. .

In addition, as described above, the pixel electrode 190 and the common electrode form a liquid crystal capacitor to maintain an applied voltage even after the thin film transistor is turned off. There is another capacitor connected in parallel with the capacitor, which is called the "storage electrode". The storage capacitor is formed by overlapping the pixel electrode 190 and the neighboring gate line 121 (which is referred to as a "previous gate line"), and the like, to increase the capacitance of the storage capacitor, that is, the storage capacitor. In order to increase the overlapped area by providing an extension part 127 extending the gate line 121, a protective film conductor 177 connected to the pixel electrode 190 and overlapping the extension part 127 is provided as a protective film. 180) Place it underneath to bring the distance between the two closer.

When the passivation layer 180 is formed of a low dielectric constant organic material, the aperture ratio may be increased by overlapping the pixel electrode 190 with the neighboring gate line 121 and the data line 171.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line and the end portion 179 of the data line through the contact holes 181 and 182. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portion 129 of the gate line and the end portion 179 of the data line and an external device such as a driving integrated circuit.

Hereinafter, a method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 2 according to an embodiment of the present invention will be described in detail with reference to FIGS. 3A to 6B and FIGS. 1 and 2.

3A, 4A, 5A, and 6A are layout views sequentially illustrating a method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 2 according to an embodiment of the present invention, and FIG. 3B is IIIb- of FIG. 3A. 4B is a cross-sectional view taken along the line IVb-IVb 'of FIG. 4A, FIG. 5B is a cross-sectional view taken along the line Vb-Vb' of FIG. 5A, and FIG. 6B is a VIb of FIG. 6A. This is a cross-sectional view taken along the line -VIb '.

First, as shown in FIGS. 3A and 3B, a metal layer is formed on an insulating substrate 110 such as transparent glass.

The metal layer is here formed by co-sputtering. In the embodiment of the present invention, aluminum-neodymium alloys (Al-Nd) and molybdenum (Mo) are used as targets of the cavity sputtering.

Initially, no power is applied to the aluminum-neodymium (Al-Nd) target and only the molybdenum (Mo) target is applied to form a lower metal layer made of molybdenum (Mo) on the substrate 110. In this case, molybdenum nitride (MoN) may be formed by supplying nitrogen gas (N ₂ ) during molybdenum sputtering. When molybdenum nitride is formed, nitriding is exhibited between the molybdenum layer and the aluminum layer to prevent aluminum from diffusing downward. In this case, the lower metal layer is formed to have a thickness of about 200 to 1000 kPa.

Then, after the power applied to molybdenum is turned off, a low resistance metal layer is formed by applying power applied to aluminum-neodymium (Al-Nd). In this case, the low resistance metal layer is formed to a thickness of about 2000 to 2500 kPa.

Subsequently, after the power is turned off to the aluminum-neodymium (Al-Nd) target, only the molybdenum (Mo) target is again powered to form an upper metal layer made of molybdenum (Mo). In this case, molybdenum nitride (MoN) may be formed by supplying nitrogen gas (N ₂ ) during molybdenum sputtering. When molybdenum nitride is formed, nitriding is exhibited between the molybdenum layer and the aluminum layer to prevent aluminum from diffusing downward. In this case, the upper metal layer is formed to have a thickness of about 200 to 1000 kPa.

Then, wet etching is performed using an etchant having a different etching ratio with respect to aluminum and molybdenum. At this time, as an etchant, phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH) and demineralized water are mixed in an appropriate ratio to use an etchant having a higher etching ratio with respect to aluminum.

By the etching, a width narrower than that of the lower metal layers 124p, 127p and 129p, the upper metal layers 124r, 127r and 129r, and the lower metal layers 124p, 127p and 129p and the upper metal layers 124r, 127r and 129r is achieved. The gate line 121 including the gate electrode 124 made of the low resistance metal layers 124q, 127q, and 129q, the extension 127, and the end portion 129 of the gate line is formed.

 Next, a gate insulating layer 140 made of silicon nitride (SiNx) or the like is formed to cover the entire surface of the gate line 121. The gate insulating layer 140 is formed by chemical vapor deposition (CVD) at a temperature of about 320 to 400 ° C.

In general, when the gate line 121 is formed of a low resistance metal such as aluminum, a large amount of hillock is formed on the surface of the wiring due to exposure to high temperatures of about 320 to 400 degrees or more in a subsequent step of forming the gate insulating layer 140. Occurs. When the metal layer formed on the substrate is exposed to a high temperature of about 320 degrees or more in the gate insulating layer 140 forming step, the hilar is stress between the metal and the substrate 110 having different thermal expansion coefficients due to heating and cooling. Is generated and migration of atoms occurs in the metal layer in order to solve the problem. This is one of the reasons why low resistance wiring such as aluminum cannot be applied to actual wiring alone.

Accordingly, in the present invention, in order to solve this problem, the lower metal layers 124p, 127p, 129p and / or the upper metal layers 124r, 127r, 129r are disposed below and / or on the low resistance metal layers 124q, 127q, and 129q. By reducing the stress, the stress generated between the substrate 110 having different coefficients of thermal expansion and the low resistance metal layers 124q, 127q, and 129q made of aluminum may be reduced to reduce the occurrence of hillock.                     

In addition, in the present invention, the low-resistance metal layer (124q, 127q, 129q) and the lower metal layer (124p, 127p, 129p) or the upper metal layer (124r, 127r, 129r) during the etching of the metal during etching the low-resistance metal layer ( 124q, 127q, and 129q are formed to have a narrower width than the lower metal layers 124p, 127p, and 129p or the upper metal layers 124r, 127r, and 129r. In this case, the lower metal layers 124p, 127p, and 129p are expanded to the side of the lower resistance metal layers 124q, 127q, and 129q, which are not covered by the lower metal layers 124p, 127p, and 129p, or the upper metal layers 124r, 127r, and 129r. ) And the gate insulating layer 140 is formed thicker by the width difference between the upper metal layers 124r, 127r, and 129r. Thus, cracks may be prevented from occurring in the gate insulating layer 140.

Subsequently, a three-layer film of intrinsic amorphous silicon and an impurity doped amorphous silicon layer is successively stacked on the gate insulating layer 140, and an amorphous silicon layer doped with impurities and an intrinsic amorphous layer The silicon layer is photo-etched to form a linear intrinsic semiconductor layer 151 each including a plurality of protrusions 154 and a plurality of impurity semiconductor patterns 164.

Subsequently, as shown in FIGS. 5A and 5B, a metal layer is stacked on the amorphous silicon layer 161 doped with impurities by sputtering or the like.

Here, similarly to the gate line 121, it is formed by cavity sputtering.

Initially, no power is applied to the aluminum-neodymium (Al-Nd) target, and only the molybdenum (Mo) target is applied to the amorphous silicon layers 161, 163, and 165 doped with impurities and the molybdenum ( A lower metal layer made of Mo) is formed. In this case, the lower metal layer is formed to have a thickness of about 200 to 1000 kPa.

Then, after the power applied to molybdenum is turned off, a low resistance metal layer is formed by applying power applied to aluminum-neodymium (Al-Nd). In this case, the low resistance metal layer is formed to a thickness of about 2000 to 2500 kPa.

Subsequently, after the power is turned off to the aluminum-neodymium (Al-Nd) target, only the molybdenum (Mo) target is again powered to form an upper metal layer made of molybdenum (Mo). In this case, the upper metal layer is formed to have a thickness of about 200 to 1000 kPa.

Then, wet etching is performed using an etchant having a different etching ratio with respect to aluminum and molybdenum. At this time, as an etchant, phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and demineralized water are mixed at an appropriate ratio to use an etchant having a higher etching ratio with respect to aluminum.

In the etching, the upper metal layers 171r, 173r, 175r, 177r, and 179r and the lower metal layers 171p, 173p, 175p, 177p, and 179p, the upper metal layers 171r, 173r, 175r, 177r, and 179r, and the lower metal layer ( Triple-layer source electrode 173, drain electrode 175, and storage capacitor conductive material including low-resistance metal layers 171q, 173q, 175q, 177q, and 179q narrower than 171p, 173p, 175p, 177p, and 179p. The sieve 177 and the end portion 179 of the data line are formed.

Next, a plurality of protrusions 163 each including a plurality of protrusions 163 are removed by removing portions of the impurity semiconductor layer 161 that are not covered by the source electrode 173, the drain electrode 175, and the storage capacitor conductor 177. The linear ohmic contact layer 161 and the plurality of islands of ohmic contact 165 are completed, while the portion of the intrinsic semiconductor 154 beneath it is exposed. In this case, it is preferable to perform oxygen (O ₂ ) plasma to stabilize the surface of the exposed intrinsic semiconductor 154.

Next, as shown in FIGS. 6A and 6B, an organic material having excellent planarization characteristics and photosensitivity, a-Si: C: O, a formed by plasma enhanced chemical vapor deposition (PECVD) A low dielectric constant insulating material such as -Si: O: F, or silicon nitride (SiNx), which is an inorganic material, is formed in a single layer or a plurality of layers to form a passivation layer.

Next, after the photoresist is coated on the passivation layer 180, the photoresist is irradiated with light through a photomask and developed to form a plurality of contact holes 181, 185, 187, and 182. In this case, in the case of the organic film having photosensitivity, the contact hole may be formed only by a photolithography process, and the gate opening 140 and the passivation layer 180 may be formed under etching conditions having substantially the same etching ratio.

Next, as shown in FIGS. 1 and 2, ITO or IZO is stacked on the substrate by sputtering, and a plurality of pixel electrodes 190 and a plurality of contact assistants 81 and 82 are formed by a photolithography process. .

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

As described above, in the wiring of the double film or the triple film including the upper metal layer, the low resistance metal layer, and the lower metal layer, the low resistance metal layer is formed to have a narrower width than the upper metal layer and the lower metal layer, thereby expanding by hillock or the like in the low resistance metal layer. It is possible to prevent cracks in the insulating film, which can be prevented from flowing into the data line the etchant used in the pixel electrode patterning.

Claims (13)

And a second metal layer formed on at least one of a first metal layer and a lower portion and an upper portion of the first metal layer, wherein the first metal layer is formed to have a narrower width than the second metal layer. The wiring of claim 1, wherein the first metal layer is made of aluminum or an aluminum alloy. The wiring of claim 2, wherein the aluminum alloy includes aluminum (Al) and niodymium (Nd). The display device of claim 1, wherein the second metal layer is formed of any one selected from chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), tungsten (W), alloys thereof, and nitrides thereof. Wiring for the device. Board, A gate line formed on the substrate and including a gate electrode, A gate insulating film formed on the gate line, A semiconductor layer formed in a predetermined region on the gate insulating film, A data line formed on the gate insulating layer and the semiconductor layer and having a drain electrode facing the source electrode at a predetermined interval, and A pixel electrode connected to the drain electrode; At least one of the gate line, the data line, and the drain electrode includes a first metal layer and a second metal layer formed on at least one of a lower portion and an upper portion of the first metal layer, wherein the first metal layer is narrower than the second metal layer. A thin film transistor array panel formed in a width. The thin film transistor array panel of claim 5, wherein the first metal layer comprises aluminum or an aluminum alloy. The thin film transistor array panel of claim 5, wherein the first metal layer is formed of an aluminum alloy including aluminum (Al) and neodymium (Nd). The thin film of claim 5, wherein the second metal layer is formed of any one selected from chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), tungsten (W), alloys thereof, and nitrides thereof. Transistor display panel. The thin film transistor array panel of claim 5, wherein the first metal layer is thicker than the second metal layer. The thin film transistor array panel of claim 5, further comprising an ohmic contact layer doped with impurities on the semiconductor layer. Forming a gate line on the substrate, Sequentially forming a gate insulating film and a semiconductor layer on the gate line; Forming a data line including a source electrode and a drain electrode facing the source electrode at a predetermined interval on the gate insulating layer and the semiconductor layer, and Forming a pixel electrode connected to the drain electrode; At least one of forming the gate line and forming the data line and the drain electrode may include forming a first metal layer and forming a second metal layer on at least one of a lower portion and an upper portion of the first metal layer. And forming the first metal layer in a narrower width than the second metal layer. The method of claim 11, wherein the first metal layer is formed of aluminum or an aluminum alloy. The method of claim 11, wherein the second metal layer is formed of any one selected from chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), tungsten (W), alloys thereof, and nitrides thereof. The manufacturing method of the thin film transistor array panel.

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