JPWO2019177895A5 - - Google Patents

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JPWO2019177895A5
JPWO2019177895A5 JP2020571333A JP2020571333A JPWO2019177895A5 JP WO2019177895 A5 JPWO2019177895 A5 JP WO2019177895A5 JP 2020571333 A JP2020571333 A JP 2020571333A JP 2020571333 A JP2020571333 A JP 2020571333A JP WO2019177895 A5 JPWO2019177895 A5 JP WO2019177895A5
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JP
Japan
Prior art keywords
dies
map
deviation
die
die comparison
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JP2020571333A
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English (en)
Japanese (ja)
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JP2021515993A (ja
JP7097466B2 (ja
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Priority claimed from US16/273,876 external-priority patent/US10585049B2/en
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Publication of JPWO2019177895A5 publication Critical patent/JPWO2019177895A5/ja
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JP2020571333A 2018-03-10 2019-03-08 プロセス誘起逸脱特性評価 Active JP7097466B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201862641297P 2018-03-10 2018-03-10
US62/641,297 2018-03-10
US16/273,876 2019-02-12
US16/273,876 US10585049B2 (en) 2018-03-10 2019-02-12 Process-induced excursion characterization
PCT/US2019/021389 WO2019177895A1 (en) 2018-03-10 2019-03-08 Process-induced excursion characterization

Publications (3)

Publication Number Publication Date
JP2021515993A JP2021515993A (ja) 2021-06-24
JPWO2019177895A5 true JPWO2019177895A5 (ko) 2022-03-10
JP7097466B2 JP7097466B2 (ja) 2022-07-07

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020571333A Active JP7097466B2 (ja) 2018-03-10 2019-03-08 プロセス誘起逸脱特性評価

Country Status (8)

Country Link
US (1) US10585049B2 (ko)
JP (1) JP7097466B2 (ko)
KR (1) KR102443351B1 (ko)
CN (1) CN111937129B (ko)
IL (1) IL277250B2 (ko)
SG (1) SG11202008760WA (ko)
TW (1) TWI797271B (ko)
WO (1) WO2019177895A1 (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11656274B2 (en) * 2021-02-15 2023-05-23 Kla Corporation Systems and methods for evaluating the reliability of semiconductor die packages
US20230128335A1 (en) * 2021-10-22 2023-04-27 Nanya Technology Corporation Manufacturing and measuring system for semiconductor structures

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3698075B2 (ja) * 2001-06-20 2005-09-21 株式会社日立製作所 半導体基板の検査方法およびその装置
US6885977B2 (en) 2002-12-20 2005-04-26 Applied Materials, Inc. System to identify a wafer manufacturing problem and method therefor
JP3896996B2 (ja) * 2003-06-27 2007-03-22 株式会社日立製作所 回路パターンの検査装置および検査方法
US7394534B1 (en) 2003-11-19 2008-07-01 Kla-Tencor Corporation Process excursion detection
KR100909474B1 (ko) * 2005-08-10 2009-07-28 삼성전자주식회사 웨이퍼 결함지수를 사용하여 국부성 불량 모드를 갖는결함성 반도체 웨이퍼의 검출 방법들 및 이에 사용되는장비들
US7570796B2 (en) 2005-11-18 2009-08-04 Kla-Tencor Technologies Corp. Methods and systems for utilizing design data in combination with inspection data
KR101789004B1 (ko) 2005-11-18 2017-10-20 케이엘에이-텐코 코포레이션 검사 데이터와 조합하여 설계 데이터를 활용하는 방법 및 시스템
EP1982160A4 (en) 2006-02-09 2016-02-17 Kla Tencor Tech Corp METHOD AND SYSTEMS FOR DETERMINING A WAFER FEATURE
US8611639B2 (en) * 2007-07-30 2013-12-17 Kla-Tencor Technologies Corp Semiconductor device property extraction, generation, visualization, and monitoring methods
US7937234B2 (en) 2008-08-29 2011-05-03 Intel Corporation Classification of spatial patterns on wafer maps
US8275564B2 (en) * 2009-02-03 2012-09-25 Qcept Technologies, Inc. Patterned wafer inspection system using a non-vibrating contact potential difference sensor
US10192303B2 (en) * 2012-11-12 2019-01-29 Kla Tencor Corporation Method and system for mixed mode wafer inspection
US10101386B2 (en) 2014-02-14 2018-10-16 Texas Instruments Incorporated Real time semiconductor process excursion monitor
KR102574171B1 (ko) * 2014-08-29 2023-09-06 에이에스엠엘 네델란즈 비.브이. 메트롤로지 방법, 타겟 및 기판
US9401313B2 (en) * 2014-11-19 2016-07-26 Deca Technologies, Inc. Automated optical inspection of unit specific patterning
US10747830B2 (en) * 2014-11-21 2020-08-18 Mesh Labs Inc. Method and system for displaying electronic information
US9779202B2 (en) * 2015-06-22 2017-10-03 Kla-Tencor Corporation Process-induced asymmetry detection, quantification, and control using patterned wafer geometry measurements

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