JPWO2019138546A1 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
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Abstract
Description
図1〜図3は第1実施形態に係る容量セルのレイアウト構造の例を示す図であり、図1は平面図、図2(a),(b)は層別の平面図、図3(a)〜(d)は断面図である。具体的には、図2(a)はVNW FETおよびその下の層を示し、図2(b)はVNW FETよりも上の層を示す。図3(a)〜(b)は図1の平面視縦方向の断面図、図3(c)〜(d)は図1の平面視横方向の断面図であり、図3(a)は線X1−X1’の断面、図3(b)は線X2−X2’の断面、図3(c)は線Y1−Y1’の断面、図3(d)は線Y2−Y2’の断面である。
図5は本変形例に係る容量セルのレイアウト構造の例を示す平面図である。本変形例では、図1のレイアウト構造に、並列にX方向に延びるM1配線41,42,43,44を追加している。M1配線41は、電源電圧VDDが与えられるローカル配線31,33,35,37と、ビアを介して接続されている。M1配線42は、電源電圧VSSが与えられるローカル配線32,36と、ビアを介して接続されている。M1配線43は、電源電圧VDDが与えられる33,37と、ビアを介して接続されている。M1配線44は、電源電圧VSSが与えられるローカル配線32,34,36,38と、ビアを介して接続されている。
図6〜図8は第2実施形態に係る容量セルのレイアウト構造の例を示す図であり、図6は平面図、図7(a),(b)は層別の平面図、図8(a)〜(d)は断面図である。具体的には、図7(a)はVNW FETおよびその下の層を示し、図7(b)はVNW FETよりも上の層を示す。図8(a)〜(b)は図6の平面視縦方向の断面図、図8(c)〜(d)は図6の平面視横方向の断面図であり、図8(a)は線X1−X1’の断面、図8(b)は線X2−X2’の断面、図8(c)は線Y1−Y1’の断面、図8(d)は線Y2−Y2’の断面である。
図10および図11は本変形例に係る容量セルのレイアウト構造の例を示す図であり、図10は平面図、図11(a),(b)は層別の平面図である。具体的には、図11(a)はVNW FETおよびその下の層を示し、図11(b)はVNW FETよりも上の層を示す。
図13は本変形例に係る容量セルのレイアウト構造の例を示す平面図である。図13では、P型トランジスタ領域において、ボトム領域11が一体に形成されており、N型トランジスタ領域において、ボトム領域12が一体に形成されている。それ以外の構成は、図6と同様である。
図14〜図16は第3実施形態に係る容量セルのレイアウト構造の例を示す図であり、図14は平面図、図15(a)〜(c)は層別の平面図、図16(a)〜(d)は断面図である。具体的には、図15(a)はVNW FETおよびその下の層を示し、図15(b)はローカル配線およびM1配線を示し、図15(c)はM1配線およびM2配線を示す。図16(a)〜(b)は図14の平面視縦方向の断面図、図16(c)〜(d)は図14の平面視横方向の断面図であり、図16(a)は線X1−X1’の断面、図16(b)は線X2−X2’の断面、図16(c)は線Y1−Y1’の断面、図16(d)は線Y2−Y2’の断面である。
図18は本変形例に係る容量セルのレイアウト構造の例を示す平面図である。本変形例では、トランジスタP1,P2,P3,P4およびトランジスタN1,N2,N3,N4は、1個のVNWを有している。そして、ゲート配線221,222,223,224とM1配線242とを接続するローカル配線235a,236a,237a,238aが、Y方向に延びるように形成されている。また、ゲート配線225,226,227,228とM1配線243とを接続するローカル配線235b,236b,237b,238bが、Y方向に延びるように形成されている。
図19および図20は第4実施形態に係る容量セルのレイアウト構造の例を示す図であり、図19は平面図、図20(a),(b)は層別の平面図である。具体的には、図20(a)はVNW FETおよびその下の層を示し、図20(b)はVNW FETよりも上の層を示す。
図22および図23は本変形例に係る容量セルのレイアウト構造の例を示す図であり、図22は平面図、図23(a),(b)は層別の平面図である。具体的には、図23(a)はVNW FETおよびその下の層を示し、図23(b)はVNW FETよりも上の層を示す。
(その1)
上述したレイアウト構造の例では、VNWの平面形状は円形であるものとしたが、VNWの平面形状は円形に限られるものではない。例えば、矩形、長円形などであってもかまわない。例えば、VNWの平面形状を長円形にした場合は、単位面積当たりのVNWの面積が大きくなるので、容量セルの容量値をより大きくすることができる。なお、VNWの平面形状を長円形のように一方向に長く延びる形状である場合には、延びる方向は同一であるのが好ましい。また、端の位置はそろっていることが好ましい。
上述したレイアウト構造の例では、VNW FETについては、1個または2個のVNWによって構成するものとしたが、VNW FETを構成するVNWの個数はこれに限られるものではない。
上述のレイアウト構造の例では、X方向に4個のトランジスタを並べた、セル幅(X方向のサイズ)が4グリッドの容量セルを例にとって説明した。ただし、容量セルのセル幅はこれに限られるものではない。また、レイアウト設計において、セル幅が異なる複数の容量セルを用意してもよい。これにより、レイアウト設計の自由度が向上する。
図24は本開示に係る容量セルを用いた半導体集積回路装置における回路ブロックのレイアウトの一例を示す平面図である。図24に示す回路ブロックでは、複数のセルCがX方向に並ぶ複数のセル列CR1,CR2,CR3が、Y方向に並べて配置されている。複数のセルCの中で、CAPは容量セルであり、ここでは第1実施形態に係るレイアウト構造を有するものとしている。ND2は2入力NANDセル、NR2は2入力NORセル、ND3は3入力NANDセルであり、VNW FETを含むレイアウト構造を有している。その他のセルについては、詳細なレイアウト構造は図示を省略している。複数のセル列CR1,CR2,CR3のY方向における両側に、X方向に延びる電源配線VSS1,VDD1,VSS2,VDD2が配置されている。電源配線VSS1,VSS2は電源電圧VSSを供給し、電源配線VDD1,VDD2は電源電圧VDDを供給する。
VSS 第2電源配線、第2電源電圧
P1,P2,P3,P4 P型VNW FET
N1,N2,N3,N4 N型VNW FET
11,111,113,211,212 ボトム領域
31,35,131,135,232a,233a,234a,231b、232b、233b ローカル配線
21,22,23,24,121,122,123,124,222,223,224,225,226,227 ゲート配線
Claims (10)
- 容量セルであるスタンダードセルを含む半導体集積回路装置であって、
前記スタンダードセルは、
第1方向に延び、第1電源電圧を供給する第1電源配線と、
前記第1方向に延び、前記第1電源電圧と異なる第2電源電圧を供給する第2電源配線と、
前記第1電源配線と前記第2電源配線との間に設けられ、前記第1方向に並ぶ複数の第1導電型VNW(Vertical Nanowire:縦型ナノワイヤ) FETとを備え、
前記複数の第1導電型VNW FETは、
トップおよびボトムが前記第1電源配線と接続されており、ゲートが前記第2電源配線と接続された、少なくとも1つの第1VNW FETを含む
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第1VNW FETのボトムと接続されたボトム領域と、
前記第1VNW FETのトップと接続されたローカル配線と、
前記第1VNW FETのゲートと接続されたゲート配線とを備え、
平面視で、前記第1VNW FETの領域において、前記ボトム領域、前記ローカル配線、および、前記ゲート配線が、重なりを有している
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記複数の第1導電型VNW FETは、
2個の前記第1VNW FETと、
前記第1VNW FET同士の間に配置されており、トップ、ボトムおよびゲートが前記第1電源配線と接続された第2VNW FETとを含む
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記複数の第1導電型VNW FETは、
2個の前記第1VNW FETと、
前記第1VNW FET同士の間に配置されており、ゲートが前記第1電源配線と接続されており、トップが前記第2電源配線と接続された第2VNW FETとを含む
ことを特徴とする半導体集積回路装置。 - 請求項3または4記載の半導体集積回路装置において、
前記第1VNW FETのゲートに接続されたゲート配線、および、前記第2VNW FETのゲートに接続されたゲート配線は、前記第1方向と垂直をなす第2方向に延びるように、並列に形成されている
ことを特徴とする半導体集積回路装置。 - 容量セルであるスタンダードセルを含む半導体集積回路装置であって、
前記スタンダードセルは、
第1方向に延び、第1電源電圧を供給する第1電源配線と、
前記第1方向に延び、前記第1電源電圧と異なる第2電源電圧を供給する第2電源配線と、
前記第1電源配線と前記第2電源配線との間に設けられ、前記第1方向に並ぶ複数の第1導電型VNW(Vertical Nanowire:縦型ナノワイヤ) FETを有する第1容量部と、
前記第1電源配線と前記第2電源配線との間に設けられた第2導電型VNW FETを有し、前記第1容量部に前記第2電源電圧を供給する固定値出力部とを備え、
前記第1容量部が有する前記複数の第1導電型VNW FETは、
トップおよびボトムが前記第1電源配線と接続されており、ゲートが、前記固定値出力部が有する前記第2導電型VNW FETのトップと接続された、少なくとも1つの第1VNW FETを含む
ことを特徴とする半導体集積回路装置。 - 請求項6記載の半導体集積回路装置において、
前記第1VNW FETのボトムと接続されたボトム領域と、
前記第1VNW FETのトップと接続されたローカル配線と、
前記第1VNW FETのゲートと接続されたゲート配線とを備え、
平面視で、前記第1VNW FETの領域において、前記ボトム領域、前記ローカル配線、および、前記ゲート配線が、重なりを有している
ことを特徴とする半導体集積回路装置。 - 請求項6記載の半導体集積回路装置において、
前記スタンダードセルは、
前記第1電源配線と前記第2電源配線との間に設けられ、前記第1方向に並ぶ複数の第2導電型VNW(Vertical Nanowire:縦型ナノワイヤ) FETを有する第2容量部を備え、
前記固定値出力部は、前記第1電源配線と前記第2電源配線との間に設けられた第1導電型VNW FETを有し、前記第2容量部に前記第1電源電圧を供給するものであり、
前記第2容量部が有する前記複数の第2導電型VNW FETは、
トップおよびボトムが前記第2電源配線と接続されており、ゲートが、前記固定値出力部が有する前記第1導電型VNW FETのトップと接続された、少なくとも1つの第2VNW FETを含む
ことを特徴とする半導体集積回路装置。 - 請求項8記載の半導体集積回路装置において、
前記第2VNW FETのボトムと接続されたボトム領域と、
前記第2VNW FETのトップと接続されたローカル配線と、
前記第2VNW FETのゲートと接続されたゲート配線とを備え、
平面視で、前記第1VNW FETの領域において、前記ボトム領域、前記ローカル配線、および、前記ゲート配線が、重なりを有している
ことを特徴とする半導体集積回路装置。 - 請求項8記載の半導体集積回路装置において、
前記固定値出力部が有する前記第1導電型VNW FETは、前記第1容量部が有する前記複数の前記第1導電型VNW FETと、前記第1方向に並ぶように配置されており、
前記固定値出力部が有する前記第2導電型VNW FETは、前記第2容量部が有する前記複数の前記第2導電型VNW FETと、前記第1方向に並ぶように配置されている
ことを特徴とする半導体集積回路装置。
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