JPS649684A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS649684A
JPS649684A JP16575887A JP16575887A JPS649684A JP S649684 A JPS649684 A JP S649684A JP 16575887 A JP16575887 A JP 16575887A JP 16575887 A JP16575887 A JP 16575887A JP S649684 A JPS649684 A JP S649684A
Authority
JP
Japan
Prior art keywords
layer
type
oeic
laser
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16575887A
Other languages
Japanese (ja)
Inventor
Kaoru Inoue
Masato Ishino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP16575887A priority Critical patent/JPS649684A/en
Publication of JPS649684A publication Critical patent/JPS649684A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To facilitate the microscopical formation of a pattern dimension and to obtain an OEIC of a planar structure suitable to contrive the improvement of a manufacturing yield by a method wherein a transverse current injection type semiconductor laser formed providing p-type and n-type impurity diffused layers at a prescribed interval and the integrated circuit of a field-effect transistor formed on a high resistance semiconductor layer are formed. CONSTITUTION:A transverse current injection type laser diode 16 is formed of p-type and n-type impurity diffused layers 8 and 7 and a laser active layer 4c held between these two layers. An optical confinement in a lateral direction is performed in this layer 4c through an ALzGa1-zAs layer 10a and an ALz'Ga1-z' As layer 10b. Si ions are implanted in a non-doped GaAs layer 6 to form an n-type FET active layer 9 of a field effect transistor 17 formed by performing a heat treatment. A source electrode 15, a drain electrode 13, a Schottky barrier gate electrode 14 are formed on this layer 9 and a GaAs MESFET is formed. In such a way, an OEIC comprising the semiconductor laser 16 and the FET 17, which are integrated on a flat substrate surface, can be obtained.
JP16575887A 1987-07-02 1987-07-02 Semiconductor device Pending JPS649684A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16575887A JPS649684A (en) 1987-07-02 1987-07-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16575887A JPS649684A (en) 1987-07-02 1987-07-02 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS649684A true JPS649684A (en) 1989-01-12

Family

ID=15818492

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16575887A Pending JPS649684A (en) 1987-07-02 1987-07-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS649684A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5311046A (en) * 1990-11-19 1994-05-10 Mitsubishi Denki Kabushiki Kaisha Long wavelength transmitter opto-electronic integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5311046A (en) * 1990-11-19 1994-05-10 Mitsubishi Denki Kabushiki Kaisha Long wavelength transmitter opto-electronic integrated circuit

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