JPS648739U - - Google Patents

Info

Publication number
JPS648739U
JPS648739U JP10300087U JP10300087U JPS648739U JP S648739 U JPS648739 U JP S648739U JP 10300087 U JP10300087 U JP 10300087U JP 10300087 U JP10300087 U JP 10300087U JP S648739 U JPS648739 U JP S648739U
Authority
JP
Japan
Prior art keywords
flat package
wiring board
printed wiring
subcarrier
screwed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10300087U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10300087U priority Critical patent/JPS648739U/ja
Publication of JPS648739U publication Critical patent/JPS648739U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案サブキヤリアの外観斜視図、第
2図は本考案のサブキヤリアのPCBへの実装拡
大側面図、第3図はPCBへのはんだ付けのため
にリード成形されたフラツトパツケージの外観斜
視図、第4図はフラツトパツケージの従来のPC
Bへの実装拡大側面図を示す。 1:パツケージ本体、2:リード、3:PCB
、4:サブキヤリア本体、5:ねじ部、6:ナツ
ト。
Fig. 1 is an external perspective view of the subcarrier of the present invention, Fig. 2 is an enlarged side view of the subcarrier of the present invention mounted on a PCB, and Fig. 3 is an external appearance of a flat package with lead molding for soldering to a PCB. The perspective view, Figure 4, shows a conventional PC in a flat package.
An enlarged side view of the mounting on B is shown. 1: Package body, 2: Lead, 3: PCB
, 4: Subcarrier body, 5: Threaded part, 6: Nut.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体集積回路を内部に実装するフラツトパツ
ケージをプリント配線基板上に実装する場合にお
いて、プリント配線基板とフラツトパツケージ間
にフラツトパツケージ本体に固定が可能で、且つ
プリント配線基板にねじ止め可能な構造をもつサ
ブキヤリア。
When a flat package with a semiconductor integrated circuit mounted inside is mounted on a printed wiring board, the flat package can be fixed to the flat package body between the printed wiring board and the flat package, and can be screwed to the printed wiring board. Subcarrier with structure.
JP10300087U 1987-07-03 1987-07-03 Pending JPS648739U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10300087U JPS648739U (en) 1987-07-03 1987-07-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10300087U JPS648739U (en) 1987-07-03 1987-07-03

Publications (1)

Publication Number Publication Date
JPS648739U true JPS648739U (en) 1989-01-18

Family

ID=31333422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10300087U Pending JPS648739U (en) 1987-07-03 1987-07-03

Country Status (1)

Country Link
JP (1) JPS648739U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012094687A (en) * 2010-10-27 2012-05-17 Opnext Japan Inc Optical transceiver

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61190963A (en) * 1984-12-06 1986-08-25 テキサス インスツルメンツ インコ−ポレイテツド Apparatus for mounting ceramic leadless chip carrier mounting apparatus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61190963A (en) * 1984-12-06 1986-08-25 テキサス インスツルメンツ インコ−ポレイテツド Apparatus for mounting ceramic leadless chip carrier mounting apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012094687A (en) * 2010-10-27 2012-05-17 Opnext Japan Inc Optical transceiver

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